Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Acknowledgment of Amendment
Acknowledgment is made of applicant's amendment, filed on 5/26/2026. The changes and remarks disclosed therein have been considered. Claims 1, 11, 13 have been amended. Therefore, claims 1-20 remain pending in the application.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1-6, 8-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over BIJIVEMULA PG PUB 20220284945 (hereinafter BIJIVEMULA), in view of Jiang US Patent 5351208 (hereinafter Jiang), further in view of Hu US Patent 7307860 (hereinafter Hu).
Regarding independent claim 1, BIJIVEMULA teaches a content addressable memory ([0005] of BIJIVEMULA, “…a CAM array…”) comprising:
a plurality of word lines (202 in figure 2 of BIJIVEMULA, [0025] of BIJIVEMULA, “…CAM array 200 including a row 202 of compare memory cell circuits 204…”);
a bit line bus ([0029] of BIJIVEMULA, “…A column compare circuit 232 receives a compare true bit 234T and a compare complement bit 234C…”, the compare true and complement lines function as bit lines used to communicate data to memory cells);
a plurality of memory cells (204 in figure 2 of BIJIVEMULA, [0025] of BIJIVEMULA, “…CAM array 200 including a row 202 of compare memory cell circuits 204…”) coupled with each of the word lines and the bit line bus;
a timing control circuit (“set clock circuit 530” indicated in [0042] of BIJIVEMULA, “…dynamic comparator circuit 524 includes a set clock circuit 530 that generates, to each decode column 502, a set clock signal 532…”, set clock circuit controls timing of comparison operations in the CAM array);
an address line control circuit (“set address circuit 236” in figure 2 and [0030] of BIJIVEMULA, “…set clock signal 222 is generated by a set address circuit 236 and is activated by the clock signal CLK…”) coupled with the timing control circuit (“set clock circuit 530 “ indicated in [0042] of BIJIVEMULA), the word lines (202 in figure 2 of BIJIVEMULA) and the bit line bus and configured to activate a corresponding word line and the bit line bus based on the control signal ([0005] of BIJIVEMULA, “…a CAM array includes at least one decode column…”); and
a processing and output circuit coupled with the bit line bus ([0029] of BIJIVEMULA, “…column compare circuit 232 generates the compare true data 216T and compare complement data 216C...”) and configured to read out data stored in the memory cells from the bit line bus in the read mode ([0026] of BIJIVEMULA, “…If the compare tag CT matches one of the binary tags BT stored in the CAM array 200, data corresponding to the binary tag BT can be accessed in the CAM array 200…”, BIJIVEMULA teaches memory cells storing binary data which may be accessed during operation, stored data is read for comparison operations), write data to be written from the bit line bus to the memory cells in the write mode (CAM memory cells inherently support write operations for storing tags), and compare data to be compared inputted from the bit line bus with data already stored in the memory cells and output a compare result in the compare mode ([0029] of BIJIVEMULA, “…column compare circuit 232 generates the compare true data 216T and compare complement data 216C...”, abstract of BIJIVEMULA, “…A row match circuit generates, for each row, in response to the set match signal, a row match signal indicating the compare tag matches the binary tag stored in the row…”, thus BIJIVEMULA teaches generating a matching signal based on comparison results).
But BIJIVEMULA does not teach the timing control circuit is configured to determine an operation mode according to a received bus command and generate a control signal for a corresponding operation mode, the operation mode comprising one of a read mode, a write mode, or a compare mode, and an address line control circuit to perform a conversion of a number of data bits according to the control signal for the corresponding operation mode
However, Jiang teaches control circuitry determining operation modes based on received command (abstract of Jiang, “…first and second plurality of lines each perform different functions during read, write, and comparison modes...”, thus Jiang provides explicit mode selection logic determining memory operations). Hu teaches in column 3 that “command data received at the I/O buffer is provided on a command bus 112 to control logic 114. The command data received by the control logic 114 is then translated into internal timing and data signals that control the functionality of the CAM 100”. Hu further teaches write operation (para(15) of Hu, “…To write data to the CAM memory cell 200, the word line…”), read operation (para(16) of Hu, “…To read data from the CAM memory cell 200, the word line…”) and compare operation (para(17) of Hu, “…the match circuit 250 compares the data stored at the data node 212 to a compare data value provided by the data line 270…”). Hu teaches operation-mode dependent processing of data through complementary data nodes 212/214, complementary data lines 270/271, read operations, write operation, and compare operations controlled by control logic 114. During a compare mode, stored data at nodes 212/214 are transformed into complementary compare representation on lines 270/271 and evaluated by match circuitry 250 according to the selected operation mode. Such processing transforms stored data into complementary representations used during the selected read, write, or compare operations. Complementary representation of stored data constitutes a transformation of plural data bits from one representation to another representation used by the selected mode. Therefore, Hu teaches or at least suggests performing a conversion of data according to a control signal corresponding to an operation mode.
BIJIVEMULA, Jiang and Hu are analogous art because all three related to memory device performing comparison operation between stored data and input data. At the time of the effective filing, it would have been obvious to one of ordinary skill in the art, having the teachings of BIJIVEMULA, Jiang and Hu before him, to modify the CAM architecture of BIJIVEMULA to include the control circuit of Jiang, to incorporate command-bus-controlled control logic and data conversion scheme of Hu, such that the timing control circuit is configured to determine an operation mode according to a received bus command and generate a control signal for a corresponding operation mode, the operation mode comprising one of a read mode, a write mode, or a compare mode, these read/write/compare are standard functions in CAM system, in order to enable the CAM device to receive commands from a system bus and control read, write and compare functions accordingly, further, Jiang’s comparison circuitry provides well-known techniques for implementing data comparison logic in memory devices, improving matching accuracy and reliability.
Regarding claim 2, the combination of BIJIVEMULA, Jiang and Hu teaches the content addressable memory according to claim 1, wherein the timing control circuit (Hu teaches timing/control circuitry and address decoding circuitry) comprises:
a timing generation circuit configured to determine the operation mode according to the received bus command and generate the control signal and a reset signal for the corresponding mode according to the determined operation mode (para(9) of Hu, “…command data received at the I/O buffer is provided on a command bus 112 to control logic 114. The command data received by the control logic 114 is then translated into internal timing and data signals that control the functionality of the CAM 100…”);
an address counting circuit coupled with the timing generation circuit and configured to receive a clock signal and the reset signal, and based on the reset signal, output a row address signal of a next row of a current processed row according to an edge change of the clock signal (Para(9) of Hu, “…Address data provided to the I/0 buffer is provided to an address decoder 120 from the control logic 114 on an address bus 124. The address data is decoded and the appropriate rows of memory cells of the CAM array 104 are activated for accessing…”); and
a word line decoding circuit coupled with the address counting circuit and configured to receive the row address signal outputted by the address counting circuit, decode a row address in the row address signal, and output the decoded signal (Para(9) of Hu, “…Address data provided to the I/0 buffer is provided to an address decoder 120 from the control logic 114 on an address bus 124. The address data is decoded and the appropriate rows of memory cells of the CAM array 104 are activated for accessing…”)
Regarding claim 3, the combination of BIJIVEMULA, Jiang and Hu teaches the content addressable memory according to claim 2, wherein the address line control circuit comprises:
a word line control circuit coupled with the word line decoding circuit and configured to receive the decoded signal and generate a word line drive signal according to the decoded signal to activate the corresponding word line (para(15) of Hu, “… To write data to the CAM memory cell 200, the word line 272 is…activated…”); and
a data conversion circuit configured to receive the control signal for the corresponding mode, and according to the control signal for the corresponding mode, perform a conversion of data bit on read data in the read mode, perform a conversion of data bit and differential processing on data to be written in the write mode, and perform differential processing on data to be compared in the compare mode (Hu teaches complementary data lines and differential data storage, (16) of Hu, “…couple the data nodes 212 and 214 to the respective data line 270 and 271…”, Hu’s complementary data node 212/214 and complementary data line 270/271 inherently perform differential processing during read, write and compare operations under the control of operation-mode control logic 114).
Regarding claim 4, the combination of BIJIVEMULA, Jiang and Hu teaches the content addressable memory according to claim 1, wherein the processing and output circuit comprises: a processing circuit coupled with the bit line bus and the memory cells and configured to compare a first data to be compared inputted from the bit line bus with a second data already stored in the memory cells and output a data matching signal according to the compare result in the compare mode (BIJIVEMULA teaches comparing stored data with input data, [0041] of BIJIVEMULA, “…Comparison of the compare tag CT to the binary tag BT in the row 510 and generation of an indication that the compare tag CT matches the binary tag BT are performed by a dynamic comparator circuit 524…”, Abstract of BIJIVEMULA, “…A row match circuit generates, for each row, in response to the set match signal, a row match signal indicating the compare tag matches the binary tag stored in the row…”, [0041] of BIJIVEMULA, “…Comparison of the compare tag CT to the binary tag BT in the row 510 and generation of an indication…”), wherein according to the first data being the same as the second data, the data matching signal outputted is a third data already stored in the memory cells ([0024] of BIJIVEMULA, “…match line 106 will remain charged to indicate that all bits of the binary tag stored in the CAM array match the corresponding bits of the compare tag…”, BIJIVEMULA teaches that a match condition produces a specific signal state), and according to the first data being different from the second data, the data matching signal outputted is a fourth data ([0022]-[0024] of BIJIVEMULA, “…if there is a mismatch between the true data 108T and the compare true data 112T, such that the true data 108T and the compare complement data 112C are both a binary “1”, both of the transistors 114A and 114B will be turned on and the match line 106 will be discharged to the ground voltage V.sub.SS, indicating the mismatch…”, thus BIJIVEMULA teaches compare operation, match/mismatch signals and match line logic states), and each bit of data of the fourth data is in a preset logical state (BIJIVEMULA inherently teaches logical states representing mismatch, e.g., ground state represents a preset logical state); and
a decision circuit coupled with the processing circuit and configured to receive the data matching signal and output the compare result according to the data matching signal (BIJIVEMULA teaches circuitry that produces match results based on the match line), wherein according to the data matching signal being the third data, the compare result outputted is in a first logical state which represents a successful comparison, and according to the data matching signal being the fourth data, the compare result outputted is in a second logical state which represents a failed comparison ([0042] of BIJIVEMULA, “…row match circuit 534 generates, for each row 510, in response to the set match signal 508 in the row 510, a row match signal 536 indicating that the compare tag CT matches the binary tag BT stored in the row 510...”, thus the row match circuit functions as the decision circuit).
Regarding claim 5, the combination of BIJIVEMULA, Jiang and Hu teaches the content addressable memory according to claim 4, wherein the processing circuit is further configured to: in the write mode, write the data to be written after being processed by a data conversion circuit to the memory cells coupled with an n-th word line to an (n+3)-th word line within four clock cycles, wherein data bits of the data to be written are m bits, data bits of the data to be written after being processed by the data conversion circuit are 2m bits, a first bit to an m-th bit and an (m+1)-th bit to a 2m-th bit of the second data respectively represent data stored in an (n+2)-th word line and the (n+3)-th word line, and an m-th bit and an (m+1)-th bit of the third data respectively represent data stored in the n-th word line and an (n+1)-th word line, where the m and the n are both natural numbers, and the m is a multiple of 8 (BIJIVEMULA teaches storing binary tag bits in memory cells arranged in rows, [0006] of BIJIVEMULA, “…each row of the plurality of rows configured to store a binary tag…”, para(15) of Hu, “…To write data to the CAM memory cell 200, the word line is activated…”, Hu teaches writing data to memory cells through bit lines and word lines, par(9) of Hu, “… Address data provided to the I/0 buffer is provided to an address decoder 120 from the control logic 114 on an address bus 124. The address data is decoded and the appropriate rows of memory cells of the CAM array 104 are activated for accessing…”, thus Hu teaches sequential address and activation of wordlines to perform memory write operation controlled by clock-driven control logic, it would have been obvious to modify the CAM architecture of BIJIVEMULA to incorporate the sequential row-activation control of Hu, in order to perform controlled write operations across multiple word lines using clock-driven addressing, such modification would allow writing processed data across successive row of memory cells (e.g., from an n-th wor line to an (n+3)-th word line) within clock cycles).
Regarding claim 6, the combination of BIJIVEMULA, Jiang and Hu teaches the content addressable memory according to claim 5, wherein the processing circuit comprises:
a first processing circuit (comparison circuitry responsible for comparison operation, [0022] of BIJIVEMULA, “…true compare circuit 104T and the complement compare circuit 104C are employed for comparing the true data 108T in the true data node 110T and complement data 108C in the complement data node 110C…”) coupled with the bit line bus and the memory cells and configured to compare the first data with the second data and output a matching signal according to the compare result in the compare mode (BIJIVEMULA teaches comparing stored data with input data, [0041] of BIJIVEMULA, “…Comparison of the compare tag CT to the binary tag BT in the row 510 and generation of an indication that the compare tag CT matches the binary tag BT are performed by a dynamic comparator circuit 524…”, Abstract of BIJIVEMULA, “…A row match circuit generates, for each row, in response to the set match signal, a row match signal indicating the compare tag matches the binary tag stored in the row…”, [0041] of BIJIVEMULA, “…Comparison of the compare tag CT to the binary tag BT in the row 510 and generation of an indication…”), wherein according to the first data being the same as the second data, the matching signal outputted is in the first logical state ([0024] of BIJIVEMULA, “…match line 106 will remain charged to indicate that all bits of the binary tag stored in the CAM array match the corresponding bits of the compare tag…”, BIJIVEMULA teaches that a match condition produces a specific signal state), and according to the first data (e.g., input compare data) being different from the second data (e.g., stored data), the matching signal outputted is in the second logical state ([0022]-[0024] of BIJIVEMULA, “…if there is a mismatch between the true data 108T and the compare true data 112T, such that the true data 108T and the compare complement data 112C are both a binary “1”, both of the transistors 114A and 114B will be turned on and the match line 106 will be discharged to the ground voltage V.sub.SS, indicating the mismatch…”, thus BIJIVEMULA teaches compare operation, match/mismatch signals and match line logic states, BIJIVEMULA inherently teaches logical states representing mismatch, e.g., ground state represents a preset logical state); and
a second processing circuit (circuitry performs logic decision/aggregation based on comparison results, e.g., row match circuit/match line logic in BIJIVEMULA, [0042] of BIJIVEMULA, “…row match circuit 534 generates, for each row 510, in response to the set match signal 508 in the row 510, a row match signal 536 indicating that the compare tag CT matches the binary tag BT stored in the row 510 …”) coupled with the first processing circuit and configured to receive the matching signal and output the data matching signal according to the matching signal, wherein according to the matching signal being in the first logical state, the data matching signal outputted is the third data (e.g., logic match state), and according to the matching signal being in the second logical state, the data matching signal outputted is the fourth data (e.g., logic mismatch state), and each bit of data of the fourth data is in the second logical state.
Regarding claim 8, the combination of BIJIVEMULA, Jiang and Hu teaches the content addressable memory according to claim 6, wherein the second processing circuit (circuitry performs logic decision/aggregation based on comparison results, e.g., row match circuit/match line logic in BIJIVEMULA, [0042] of BIJIVEMULA, “…row match circuit 534 generates, for each row 510, in response to the set match signal 508 in the row 510, a row match signal 536 indicating that the compare tag CT matches the binary tag BT stored in the row 510 …”) comprises: a plurality of memory cell inverting circuits (BIJIVEMULA teaches memory cells and comparison circuitry arranged in rows of a CAM array, Jiang teaches CAM memory cells having complementary nodes that represent inverted logic state, Para(10) of Jiang, “…Memory cell 216 has two states: logic state "0" and logic state "1". For example, if logic state "0" is designated by node 204 having a high voltage and node 205 having a low voltage, then logic state "1" has the opposite stored voltages, i.e. node 204 having a low voltage and node 205 having a high voltage…”), each of which is coupled with one of the memory cells and configured to perform a inverting processing on the data stored in the memory cells and output an inverted result (it is inherent for a SRAM operation); and
a second logic operation circuit (BIJIVEMULA teaches combining output from comparison circuitry to generate a match signal) coupled with the plurality of memory cell inverting circuits and configured to receive the inverted result outputted by each memory cell inverting circuit corresponding to the memory cells coupled with the n-th word line to the (n+1)-th word line, and perform a second logic operation on each inverted result to generate the data matching signal (BIJIVEMULA teaches combining output from comparison circuitry to generate a match signal, [0042], “…row match circuit 534 generates, for each row 510, in response to the set match signal 508 in the row 510, a row match signal 536 indicating that the compare tag CT matches the binary tag BT stored in the row 510…”, thus BIJIVEMULA teaches a logic circuitry that processes comparison outputs).
Regarding claim 9, the combination of BIJIVEMULA, Jiang and Hu teaches the content addressable memory according to claim 4, wherein the third data is storage address data corresponding to the second data (Jiang teaches identifying and outputting the address of a matching CAM entry, para(8) of Jiang, “…Match detector 5 detects a "no match" or "match" condition. Priority encoder 6 encodes the address of the location in CAM cell array 11 when a "match" condition occurs…”, it would have been obvious to incorporate the address encoding mechanism of Jiang into the CAM architecture of BIJIVEMULA in order to identify the storage location of matching data, since CAM systems commonly output the address of a matching entry for subsequent processing).
Regarding claim 10, the combination of BIJIVEMULA, Jiang and Hu teaches the content addressable memory according to claim 1, wherein the bit line bus comprises a first bit line bus and a first complementary bit line bus ([0029] of BIJIVEMULA, “…A column compare circuit 232 receives a compare true bit 234T and a compare complement bit 234C…”, the compare true and complement lines function as bit lines used to communicate data to memory cells), and the memory cell (figure 1 of BIJIVEMULA) comprises: a first transistor (access transistor in figure 1), a second transistor (second access transistor in figure 1), a first inverter, and a second inverter, wherein: a control end of the first transistor is connected with the word line, a first controlled end of the first transistor is connected with the first bit line bus, and a second controlled end of the first transistor is connected with both of an input end of the first inverter and an output end of the second inverter; and a control end of the second transistor is connected with the word line, a first controlled end of the second transistor is connected with the first complementary bit line bus, and a second controlled end of the second transistor is connected with both of an output end of the first inverter and an input end of the second inverter (BIJIVEMULA teaches the CAM cell include SRAM storage structure, [0022] of BIJIVEMULA, “…compare memory cell circuit 100 includes a six (6) transistor (6T) static random-access memory cell circuit 102...”)
Regarding independent claim 11, the combination of BIJIVEMULA, Jiang and Hu teaches a processor comprising one or more content addressable memories ([0005] of BIJIVEMULA, “…a CAM array…”, Hu teaches integrating memory devices into a processor system, para(9) of Hu, “…command data received at the I/O buffer is provided on a command bus 112 to control logic 114. The command data received by the control logic 114 is then translated into internal timing and data signals that control the functionality of the CAM 100…”), wherein the one or more content addressable memory comprises:
a plurality of word lines (202 in figure 2 of BIJIVEMULA, [0025] of BIJIVEMULA, “…CAM array 200 including a row 202 of compare memory cell circuits 204…”);
a bit line bus ([0029] of BIJIVEMULA, “…A column compare circuit 232 receives a compare true bit 234T and a compare complement bit 234C…”, the compare true and complement lines function as bit lines used to communicate data to memory cells);
a plurality of memory cells (204 in figure 2 of BIJIVEMULA, [0025] of BIJIVEMULA, “…CAM array 200 including a row 202 of compare memory cell circuits 204…”) coupled with each of the word lines and the bit line bus;
a timing control circuit (“set clock circuit 530” indicated in [0042] of BIJIVEMULA, “…dynamic comparator circuit 524 includes a set clock circuit 530 that generates, to each decode column 502, a set clock signal 532…”, set clock circuit controls timing of comparison operations in the CAM array) configured to determine an operation mode according to a received bus command and generate a control signal for a corresponding operation mode, the operation mode comprising one of a read mode, a write mode, or a compare mode (Jiang teaches control circuitry determining operation modes based on received command, abstract of Jiang, “…first and second plurality of lines each perform different functions during read, write, and comparison modes...”, thus Jiang provides explicit mode selection logic determining memory operations, Hu teaches in col 3 that “command data received at the I/O buffer is provided on a command bus 112 to control logic 114. The command data received by the control logic 114 is then translated into internal timing and data signals that control the functionality of the CAM 100”. Hu further teaches write operation (para(15) of Hu), read operation (para(16) of Hu), and compare operation (para(17) of Hu);
an address line control circuit (“set address circuit 236” in figure 2 and [0030] of BIJIVEMULA, “…set clock signal 222 is generated by a set address circuit 236 and is activated by the clock signal CLK…”) coupled with the timing control circuit (“set clock circuit 530 “ indicated in [0042] of BIJIVEMULA), the word lines (202 in figure 2 of BIJIVEMULA) and the bit line bus and configured to activate a corresponding word line and the bit line bus based on the control signal ([0005] of BIJIVEMULA, “…a CAM array includes at least one decode column…”) and to perform a conversion of a number of data bits according to the control signal for the corresponding operation mode (Hu teaches in column 3 that “command data received at the I/O buffer is provided on a command bus 112 to control logic 114. The command data received by the control logic 114 is then translated into internal timing and data signals that control the functionality of the CAM 100”. Hu further teaches write operation (para(15) of Hu, “…To write data to the CAM memory cell 200, the word line…”), read operation (para(16) of Hu, “…To read data from the CAM memory cell 200, the word line…”) and compare operation (para(17) of Hu, “…the match circuit 250 compares the data stored at the data node 212 to a compare data value provided by the data line 270…”). Hu teaches operation-mode dependent processing of data through complementary data nodes 212/214, complementary data lines 270/271, read operations, write operation, and compare operations controlled by control logic 114. Such processing converts stored data representations and compare data representations dependent upon the selected operation mode. Therefore, Hu teaches or at least suggests performing a conversion of data according to a control signal corresponding to an operation mode); and
a processing and output circuit coupled with the bit line bus ([0029] of BIJIVEMULA, “…column compare circuit 232 generates the compare true data 216T and compare complement data 216C...”) and configured to read out data stored in the memory cells from the bit line bus in the read mode ([0026] of BIJIVEMULA, “…If the compare tag CT matches one of the binary tags BT stored in the CAM array 200, data corresponding to the binary tag BT can be accessed in the CAM array 200…”, BIJIVEMULA teaches memory cells storing binary data which may be accessed during operation, stored data is read for comparison operations), write data to be written from the bit line bus to the memory cells in the write mode (CAM memory cells inherently support write operations for storing tags), and compare data to be compared inputted from the bit line bus with data already stored in the memory cells and output a compare result in the compare mode ([0029] of BIJIVEMULA, “…column compare circuit 232 generates the compare true data 216T and compare complement data 216C...”, abstract of BIJIVEMULA, “…A row match circuit generates, for each row, in response to the set match signal, a row match signal indicating the compare tag matches the binary tag stored in the row…”, thus BIJIVEMULA teaches generating a matching signal based on comparison results).
Regarding claim 12, the combination of BIJIVEMULA, Jiang and Hu teaches the processor according to claim 11, wherein the processor comprises a microprocessor unit (MCU) (Hu teaches processor-controlled CAM operations. It would have been obvious to implement the process as a microprocessor unit, sinch MCUs are conventional processors used to control memory system).
Regarding independent claim 13, the combination of BIJIVEMULA, Jiang and Hu teaches a memory system comprising:
at least one memory device and a memory controller coupled with and controlling the memory device (Hu teaches memory controllers communicating with memory arrays), wherein: the memory device comprises:
a memory cell array and a peripheral circuit coupled with and controlling the memory cell array; at least one of the peripheral circuit or the memory controller comprises one or more processors, the one or more processors comprising one or more content addressable memories, wherein the content addressable memory comprises:
a plurality of word lines (202 in figure 2 of BIJIVEMULA, [0025] of BIJIVEMULA, “…CAM array 200 including a row 202 of compare memory cell circuits 204…”);
a bit line bus ([0029] of BIJIVEMULA, “…A column compare circuit 232 receives a compare true bit 234T and a compare complement bit 234C…”, the compare true and complement lines function as bit lines used to communicate data to memory cells);
a plurality of memory cells (204 in figure 2 of BIJIVEMULA, [0025] of BIJIVEMULA, “…CAM array 200 including a row 202 of compare memory cell circuits 204…”) coupled with each of the word lines and the bit line bus;
a timing control circuit (“set clock circuit 530” indicated in [0042] of BIJIVEMULA, “…dynamic comparator circuit 524 includes a set clock circuit 530 that generates, to each decode column 502, a set clock signal 532…”, set clock circuit controls timing of comparison operations in the CAM array) configured to determine an operation mode according to a received bus command and generate a control signal for a corresponding operation mode, the operation mode comprising one of a read mode, a write mode, or a compare mode (Jiang teaches control circuitry determining operation modes based on received command, abstract of Jiang, “…first and second plurality of lines each perform different functions during read, write, and comparison modes...”, thus Jiang provides explicit mode selection logic determining memory operations, Hu teaches in col 3 that “command data received at the I/O buffer is provided on a command bus 112 to control logic 114. The command data received by the control logic 114 is then translated into internal timing and data signals that control the functionality of the CAM 100”. Hu further teaches write operation (para(15) of Hu), read operation (para(16) of Hu), and compare operation (para(17) of Hu);
an address line control circuit (“set address circuit 236” in figure 2 and [0030] of BIJIVEMULA, “…set clock signal 222 is generated by a set address circuit 236 and is activated by the clock signal CLK…”) coupled with the timing control circuit (“set clock circuit 530 “ indicated in [0042] of BIJIVEMULA), the word lines (202 in figure 2 of BIJIVEMULA) and the bit line bus and configured to activate a corresponding word line and the bit line bus based on the control signal ([0005] of BIJIVEMULA, “…a CAM array includes at least one decode column…”) and to perform a conversion of a number of data bits according to the control signal for the corresponding operation mode (Hu teaches in column 3 that “command data received at the I/O buffer is provided on a command bus 112 to control logic 114. The command data received by the control logic 114 is then translated into internal timing and data signals that control the functionality of the CAM 100”. Hu further teaches write operation (para(15) of Hu, “…To write data to the CAM memory cell 200, the word line…”), read operation (para(16) of Hu, “…To read data from the CAM memory cell 200, the word line…”) and compare operation (para(17) of Hu, “…the match circuit 250 compares the data stored at the data node 212 to a compare data value provided by the data line 270…”). Hu teaches operation-mode dependent processing of data through complementary data nodes 212/214, complementary data lines 270/271, read operations, write operation, and compare operations controlled by control logic 114. Such processing converts stored data representations and compare data representations dependent upon the selected operation mode. Therefore, Hu teaches or at least suggests performing a conversion of data according to a control signal corresponding to an operation mode); and
a processing and output circuit coupled with the bit line bus ([0029] of BIJIVEMULA, “…column compare circuit 232 generates the compare true data 216T and compare complement data 216C...”) and configured to read out data stored in the memory cells from the bit line bus in the read mode ([0026] of BIJIVEMULA, “…If the compare tag CT matches one of the binary tags BT stored in the CAM array 200, data corresponding to the binary tag BT can be accessed in the CAM array 200…”, BIJIVEMULA teaches memory cells storing binary data which may be accessed during operation, stored data is read for comparison operations), write data to be written from the bit line bus to the memory cells in the write mode (CAM memory cells inherently support write operations for storing tags), and compare data to be compared inputted from the bit line bus with data already stored in the memory cells and output a compare result in the compare mode ([0029] of BIJIVEMULA, “…column compare circuit 232 generates the compare true data 216T and compare complement data 216C...”, abstract of BIJIVEMULA, “…A row match circuit generates, for each row, in response to the set match signal, a row match signal indicating the compare tag matches the binary tag stored in the row…”, thus BIJIVEMULA teaches generating a matching signal based on comparison results).
Claims 14-20 are rejected under 35 U.S.C. 103 as being unpatentable over BIJIVEMULA PG PUB 20220284945 (hereinafter BIJIVEMULA), in view of Jiang US Patent 5351208 (hereinafter Jiang), further in view of Hu US Patent 7307860 (hereinafter Hu), for the reasons discussed above with respect to claims 4-10.
Claim 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over BIJIVEMULA PG PUB 20220284945 (hereinafter BIJIVEMULA), in view of Jiang US Patent 5351208 (hereinafter Jiang), CAM circuitry compares further in view of Hu US Patent 7307860 (hereinafter Hu), further in view of Bettman US Patent 7307861 (hereinafter Bettman).
Regarding claim 7, the combination of BIJIVEMULA, Jiang and Hu teaches the content addressable memory according to claim 6, but does not teach implementing the comparison circuitry such as XOR comparison circuits. In particular, BIJIVEMULA does not teach the first processing circuit (comparison circuitry responsible for comparison operation, [0022] of BIJIVEMULA, “…true compare circuit 104T and the complement compare circuit 104C are employed for comparing the true data 108T in the true data node 110T and complement data 108C in the complement data node 110C…”) comprises: a plurality of memory cell XOR circuits each coupled with the bit line bus, wherein each memory cell XOR circuit is coupled with one of the memory cells and configured to perform XOR processing on data inputted from the bit line bus with the data stored in the memory cells, and output an XOR result ; and a first logic operation circuit coupled with the plurality of memory cell XOR circuits and configured to receive the XOR result outputted by each memory cell XOR circuit corresponding to the memory cells coupled with an (n+2)-th word line to an (n+3)-th word line, and performing a first logic operation on each XOR result to generate the matching signal.
However, Bettman teaches a memory cell comparison transistor network, which can evaluate stored data against input bit line values and signals mismatch on a match line. Bettman teaches a bitwise comparison circuitry in CAM cells that compare stored data against input bit line values and generate mismatch signals, which corresponds to XOR-type comparison operations. It would have been obvious to incorporate the comparison circuitry of Bettman into the CAM architecture of BIJIVEMULA to perform efficient bitwise comparison between stored data and input data, such that the first processing circuit (comparison circuitry responsible for comparison operation, [0022] of BIJIVEMULA, “…true compare circuit 104T and the complement compare circuit 104C are employed for comparing the true data 108T in the true data node 110T and complement data 108C in the complement data node 110C…”) comprises: a plurality of memory cell XOR circuits each coupled with the bit line bus, wherein each memory cell XOR circuit is coupled with one of the memory cells and configured to perform XOR processing on data inputted from the bit line bus with the data stored in the memory cells, and output an XOR result (para(9) of Bettman, “…An XOR type comparison stack 704 can generate a compare result for the conventional TCAM cell 700. In particular, data values (shown as X and Y) stored in SRAM cells (702-0 and 702-1) can be compared against complementary compare data values (CD and CDB) provided by differential compare data lines (not shown). In the particular arrangement of FIG. 7, in the event of a match compare result, a match line 708 can remain essentially isolated from a low power supply voltage VSS. In the event of a mis-match compare result, an XOR type comparison stack 704 can provide a discharge path to a low power supply voltage VSS…”); and a first logic operation circuit (BIJIVEMULA teaches a row match circuit coupled witht eh comparison circuitry of memory cells) coupled with the plurality of memory cell XOR circuits and configured to receive the XOR result outputted by each memory cell XOR circuit corresponding to the memory cells coupled with an (n+2)-th word line to an (n+3)-th word line, and performing a first logic operation on each XOR result to generate the matching signal (BIJIVEMULA teaches combining comparison results from multiple cells to generate a match signal).
Response to Arguments
Applicant's arguments have been fully considered but they are not persuasive.
Applicant has amended the independent claims 1, 11, 13 with additional limitation(s): "an address line control circuit…perform a conversion of a number of data bits according to the control signal for the corresponding operation mode," the Applicant argues that the prior arts of record do not specifically teach this limitation. However, the limitation does not specify any particular conversion algorithm, XOR operation, bit rearrangement operation, or data-width transformation. The term “conversion” is broadly recited. The specification of applicant describes the data conversion circuit as performing read-mode, write-mode, and compare mode processing (see [0067]/[0072]-[0074] of specification of instance case), including generation of inverted data and compare data, without requiring a change in bit count. Accordingly, the broadest reasonable interpretation of “conversion of a number of data bits” encompasses operation-mode-dependent transformation or processing of multiple data bits. Hu teaches in column 3 that “command data received at the I/O buffer is provided on a command bus 112 to control logic 114. The command data received by the control logic 114 is then translated into internal timing and data signals that control the functionality of the CAM 100”. Hu further teaches write operation (para(15) of Hu, “…To write data to the CAM memory cell 200, the word line…”), read operation (para(16) of Hu, “…To read data from the CAM memory cell 200, the word line…”) and compare operation (para(17) of Hu, “…the match circuit 250 compares the data stored at the data node 212 to a compare data value provided by the data line 270…”). During a compare mode, stored data at nodes 212/214 are transformed into complementary compare representation on lines 270/271 and evaluated by match circuitry 250 according to the selected operation mode. Hu teaches operation-mode dependent processing of data through complementary data nodes 212/214, complementary data lines 270/271, read operations, write operation, and compare operations controlled by control logic 114. Such processing converts stored data representations and compare data representations dependent upon the selected operation mode. Complementary representation of stored data constitutes a transformation of plural data bits from one representation to another representation used by the selected mode. Therefore, Hu teaches or at least suggests performing a conversion of data according to a control signal corresponding to an operation mode.
Accordingly, the Examiner maintains the position previously set forth.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/XIAOCHUN L CHEN/Primary Examiner, Art Unit 2824
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