Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 8/3/2026 has been entered.
Claim Rejections - 35 USC § 112
Claims 1-4, 9-17 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claims 1, 11, 13 have been amended to recite an address line control circuit configured to “perform a conversion from p bits to q bits according to the control signal for the corresponding operation mode, wherein p and q are integers and q is different from p”.
The original filed specification does not reasonably convey to one of ordinary skill in the art that applicant was in possession of the full scope of the presently claimed conversion from p bits to q bits, wherein q may be any integer different from p.
Specifically, paragraph [0009] of the originally filed specification describes a particular data conversion in which the number of data bits before processing is m bits and then the number of data bits after processing is 2m bits. Paragraph [0026] further describes the particular conversion in connection with a write operation involving data written into memory cells associated with multiple word lines. Paragraph [0138] likewise describes the particular relationship between the number of data bits before and after conversion, m bits to 2m bits.
Furthermore, original claims 5, 18 recite the particular m-bits to 2m bit conversion.
Thus originally filed disclosure expressly describes a conversion having an output bit count twice the input bit count.
However, amended claims 1, 11, 13 are not limited to such a relationship.
Rather, the amended claims broadly encompass any conversion from p bits to q bits where p differs from p, including, for example, 9 bits to 12 bits.
The originally filed specification does not identify representative implementations of such alternative unequal-width conversions, nor does it describe common technical characteristics or conversion circuitry that would reasonably convey possession of the full claimed class of conversion.
The additional limitations of claims 2-4, 9-10, 12, 14 do not appear to restrict the inherited p-to-q conversions to the particular m-to-2m relationship or otherwise identify conversion structures demonstrating possession of the full claimed scope. Thus dependent Claims 2-4, 9-10, 12, 14 retain the written-description deficiency identified in their respective independent claims and fail to comply with the written description requirement of 35 U.S.C. 112(a).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1-4, 9-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over BIJIVEMULA PG PUB 20220284945 (hereinafter BIJIVEMULA), in view of Jiang US Patent 5351208 (hereinafter Jiang), in view of Hu US Patent 7307860 (hereinafter Hu), further in view of Sohn PG PUB 20050071582 (hereinafter Sohn).
Regarding independent claim 1, BIJIVEMULA teaches a content addressable memory ([0005] of BIJIVEMULA, “…a CAM array…”) comprising:
a plurality of word lines (202 in figure 2 of BIJIVEMULA, [0025] of BIJIVEMULA, “…CAM array 200 including a row 202 of compare memory cell circuits 204…”);
a bit line bus ([0029] of BIJIVEMULA, “…A column compare circuit 232 receives a compare true bit 234T and a compare complement bit 234C…”, the compare true and complement lines function as bit lines used to communicate data to memory cells);
a plurality of memory cells (204 in figure 2 of BIJIVEMULA, [0025] of BIJIVEMULA, “…CAM array 200 including a row 202 of compare memory cell circuits 204…”) coupled with each of the word lines and the bit line bus;
a timing control circuit (“set clock circuit 530” indicated in [0042] of BIJIVEMULA, “…dynamic comparator circuit 524 includes a set clock circuit 530 that generates, to each decode column 502, a set clock signal 532…”, set clock circuit controls timing of comparison operations in the CAM array);
an address line control circuit (“set address circuit 236” in figure 2 and [0030] of BIJIVEMULA, “…set clock signal 222 is generated by a set address circuit 236 and is activated by the clock signal CLK…”) coupled with the timing control circuit (“set clock circuit 530 “ indicated in [0042] of BIJIVEMULA), the word lines (202 in figure 2 of BIJIVEMULA) and the bit line bus and configured to activate a corresponding word line and the bit line bus based on the control signal ([0005] of BIJIVEMULA, “…a CAM array includes at least one decode column…”); and
a processing and output circuit coupled with the bit line bus ([0029] of BIJIVEMULA, “…column compare circuit 232 generates the compare true data 216T and compare complement data 216C...”) and configured to read out data stored in the memory cells from the bit line bus in the read mode ([0026] of BIJIVEMULA, “…If the compare tag CT matches one of the binary tags BT stored in the CAM array 200, data corresponding to the binary tag BT can be accessed in the CAM array 200…”, BIJIVEMULA teaches memory cells storing binary data which may be accessed during operation, stored data is read for comparison operations), write data to be written from the bit line bus to the memory cells in the write mode (CAM memory cells inherently support write operations for storing tags), and compare data to be compared inputted from the bit line bus with data already stored in the memory cells and output a compare result in the compare mode ([0029] of BIJIVEMULA, “…column compare circuit 232 generates the compare true data 216T and compare complement data 216C...”, abstract of BIJIVEMULA, “…A row match circuit generates, for each row, in response to the set match signal, a row match signal indicating the compare tag matches the binary tag stored in the row…”, thus BIJIVEMULA teaches generating a matching signal based on comparison results).
But BIJIVEMULA does not teach the timing control circuit is configured to determine an operation mode according to a received bus command and generate a control signal for a corresponding operation mode, the operation mode comprising one of a read mode, a write mode, or a compare mode, and an address line control circuit to perform a conversion of a number of data bits according to the control signal for the corresponding operation mode.
However, Jiang teaches control circuitry determining operation modes based on received command (abstract of Jiang, “…first and second plurality of lines each perform different functions during read, write, and comparison modes...”, thus Jiang provides explicit mode selection logic determining memory operations). Hu teaches in column 3 that “command data received at the I/O buffer is provided on a command bus 112 to control logic 114. The command data received by the control logic 114 is then translated into internal timing and data signals that control the functionality of the CAM 100”. Hu further teaches write operation (para(15) of Hu, “…To write data to the CAM memory cell 200, the word line…”), read operation (para(16) of Hu, “…To read data from the CAM memory cell 200, the word line…”) and compare operation (para(17) of Hu, “…the match circuit 250 compares the data stored at the data node 212 to a compare data value provided by the data line 270…”). Hu teaches operation-mode dependent processing of data through complementary data nodes 212/214, complementary data lines 270/271, read operations, write operation, and compare operations controlled by control logic 114. During a compare mode, stored data at nodes 212/214 are transformed into complementary compare representation on lines 270/271 and evaluated by match circuitry 250 according to the selected operation mode. Such processing transforms stored data into complementary representations used during the selected read, write, or compare operations. Complementary representation of stored data constitutes a transformation of plural data bits from one representation to another representation used by the selected mode. Therefore, Hu teaches or at least suggests performing a conversion of data according to a control signal corresponding to an operation mode.
BIJIVEMULA, Jiang and Hu are analogous art because all three related to memory device performing comparison operation between stored data and input data. At the time of the effective filing, it would have been obvious to one of ordinary skill in the art, having the teachings of BIJIVEMULA, Jiang and Hu before him, to modify the CAM architecture of BIJIVEMULA to include the control circuit of Jiang, to incorporate command-bus-controlled control logic and data conversion scheme of Hu, such that the timing control circuit is configured to determine an operation mode according to a received bus command and generate a control signal for a corresponding operation mode, the operation mode comprising one of a read mode, a write mode, or a compare mode, these read/write/compare are standard functions in CAM system, in order to enable the CAM device to receive commands from a system bus and control read, write and compare functions accordingly, further, Jiang’s comparison circuitry provides well-known techniques for implementing data comparison logic in memory devices, improving matching accuracy and reliability.
But the combination of BIJIVEMULA, Jiang and Hu does not teach the required conversion between unequal data widths, specifically, the combination does not teach an address line control circuit configured to “perform a conversion from p bits to q bits according to the control signal for the corresponding operation mode, wherein p and q are integers and q is different from p”.
However, Sohn teaches circuitry for controlling the input/output width of data transferred during memory operation. Particularly, Sohn teaches in figures 4, 7-9 a decoder 100, which responds to read or write commands and generates an internal I/O width control signal WCON, data output buffer controller 200, which receives WCON and generates COUT. Data input buffer controller 300, which receives WCON and generates CIN. Data output buffer 800 and data input buffer 900, whose effective data widths are controlled by the respective signals.
Sohn expressly teaches an example in which an 8-bit data word is converted to a 6-bit output word by masking two bits, and another example in which an 9-bit word is converted to a 2-bit output word by masking 6 bits (figure 5).
Thus Sohn teaches p=8, q=6, or alternatively, p=8, q=2, wherein p and q are integers and q differs from p.
Further Sogn teaches that decoder 100 is activated in response to read or write commands and generate WCON based on address-derived width control bits AD<9:10> (figure 7). Accordingly, Sohn teaches controlling data-width conversion with a corresponding memory operation.
It would have been to one of ordinary skill in the art before the effective filing data to modify the address and data control circuitry of the CAM system of BIJIVEMULA, as modified by Jiang and Hu, to incorporate the selectable data-width control circuitry taught by Sohn. Such modification would allow the memory system to support different effective data widths during read and write operations, thereby providing greater flexibility in transferring data and reducing unnecessary data-bit activity.
Therefore, the combination would have suggested performing a conversion from p bits to q bits in response to control signals associated with memory operation modes.
Regarding claim 2, the combination of BIJIVEMULA, Jiang, Hu and Sohn teaches the content addressable memory according to claim 1, wherein the timing control circuit (Hu teaches timing/control circuitry and address decoding circuitry) comprises:
a timing generation circuit configured to determine the operation mode according to the received bus command and generate the control signal and a reset signal for the corresponding mode according to the determined operation mode (para(9) of Hu, “…command data received at the I/O buffer is provided on a command bus 112 to control logic 114. The command data received by the control logic 114 is then translated into internal timing and data signals that control the functionality of the CAM 100…”);
an address counting circuit coupled with the timing generation circuit and configured to receive a clock signal and the reset signal, and based on the reset signal, output a row address signal of a next row of a current processed row according to an edge change of the clock signal (Para(9) of Hu, “…Address data provided to the I/0 buffer is provided to an address decoder 120 from the control logic 114 on an address bus 124. The address data is decoded and the appropriate rows of memory cells of the CAM array 104 are activated for accessing…”); and
a word line decoding circuit coupled with the address counting circuit and configured to receive the row address signal outputted by the address counting circuit, decode a row address in the row address signal, and output the decoded signal (Para(9) of Hu, “…Address data provided to the I/0 buffer is provided to an address decoder 120 from the control logic 114 on an address bus 124. The address data is decoded and the appropriate rows of memory cells of the CAM array 104 are activated for accessing…”)
Regarding claim 3, the combination of BIJIVEMULA, Jiang, Hu and Sohn teaches the content addressable memory according to claim 2, wherein the address line control circuit comprises:
a word line control circuit coupled with the word line decoding circuit and configured to receive the decoded signal and generate a word line drive signal according to the decoded signal to activate the corresponding word line (para(15) of Hu, “… To write data to the CAM memory cell 200, the word line 272 is…activated…”); and
a data conversion circuit configured to receive the control signal for the corresponding mode, and according to the control signal for the corresponding mode, perform a conversion of data bit on read data in the read mode, perform a conversion of data bit and differential processing on data to be written in the write mode, and perform differential processing on data to be compared in the compare mode (Sohn teaches in figures 4, 7-9 width control circuitry operating according to READ or WRITE commands. Hu teaches complementary data lines and differential data storage, (16) of Hu, “…couple the data nodes 212 and 214 to the respective data line 270 and 271…”, Hu’s complementary data node 212/214 and complementary data line 270/271 perform differential processing during read, write and compare operations under the control of operation-mode control logic 114).
Regarding claim 4, the combination of BIJIVEMULA, Jiang, Hu and Sohn teaches the content addressable memory according to claim 1, wherein the processing and output circuit comprises: a processing circuit coupled with the bit line bus and the memory cells and configured to compare a first data to be compared inputted from the bit line bus with a second data already stored in the memory cells and output a data matching signal according to the compare result in the compare mode (BIJIVEMULA teaches comparing stored data with input data, [0041] of BIJIVEMULA, “…Comparison of the compare tag CT to the binary tag BT in the row 510 and generation of an indication that the compare tag CT matches the binary tag BT are performed by a dynamic comparator circuit 524…”, Abstract of BIJIVEMULA, “…A row match circuit generates, for each row, in response to the set match signal, a row match signal indicating the compare tag matches the binary tag stored in the row…”, [0041] of BIJIVEMULA, “…Comparison of the compare tag CT to the binary tag BT in the row 510 and generation of an indication…”), wherein according to the first data being the same as the second data, the data matching signal outputted is a third data already stored in the memory cells ([0024] of BIJIVEMULA, “…match line 106 will remain charged to indicate that all bits of the binary tag stored in the CAM array match the corresponding bits of the compare tag…”, BIJIVEMULA teaches that a match condition produces a specific signal state), and according to the first data being different from the second data, the data matching signal outputted is a fourth data ([0022]-[0024] of BIJIVEMULA, “…if there is a mismatch between the true data 108T and the compare true data 112T, such that the true data 108T and the compare complement data 112C are both a binary “1”, both of the transistors 114A and 114B will be turned on and the match line 106 will be discharged to the ground voltage V.sub.SS, indicating the mismatch…”, thus BIJIVEMULA teaches compare operation, match/mismatch signals and match line logic states), and each bit of data of the fourth data is in a preset logical state (BIJIVEMULA inherently teaches logical states representing mismatch, e.g., ground state represents a preset logical state); and
a decision circuit coupled with the processing circuit and configured to receive the data matching signal and output the compare result according to the data matching signal (BIJIVEMULA teaches circuitry that produces match results based on the match line), wherein according to the data matching signal being the third data, the compare result outputted is in a first logical state which represents a successful comparison, and according to the data matching signal being the fourth data, the compare result outputted is in a second logical state which represents a failed comparison ([0042] of BIJIVEMULA, “…row match circuit 534 generates, for each row 510, in response to the set match signal 508 in the row 510, a row match signal 536 indicating that the compare tag CT matches the binary tag BT stored in the row 510...”, thus the row match circuit functions as the decision circuit).
Regarding claim 9, the combination of BIJIVEMULA, Jiang, Hu and Sohn teaches the content addressable memory according to claim 4, wherein the third data is storage address data corresponding to the second data (Jiang teaches identifying and outputting the address of a matching CAM entry, para(8) of Jiang, “…Match detector 5 detects a "no match" or "match" condition. Priority encoder 6 encodes the address of the location in CAM cell array 11 when a "match" condition occurs…”, it would have been obvious to incorporate the address encoding mechanism of Jiang into the CAM architecture of BIJIVEMULA in order to identify the storage location of matching data, since CAM systems commonly output the address of a matching entry for subsequent processing).
Regarding claim 10, the combination of BIJIVEMULA, Jiang, Hu and Sohn teaches the content addressable memory according to claim 1, wherein the bit line bus comprises a first bit line bus and a first complementary bit line bus ([0029] of BIJIVEMULA, “…A column compare circuit 232 receives a compare true bit 234T and a compare complement bit 234C…”, the compare true and complement lines function as bit lines used to communicate data to memory cells), and the memory cell (figure 1 of BIJIVEMULA) comprises: a first transistor (access transistor in figure 1), a second transistor (second access transistor in figure 1), a first inverter, and a second inverter, wherein: a control end of the first transistor is connected with the word line, a first controlled end of the first transistor is connected with the first bit line bus, and a second controlled end of the first transistor is connected with both of an input end of the first inverter and an output end of the second inverter; and a control end of the second transistor is connected with the word line, a first controlled end of the second transistor is connected with the first complementary bit line bus, and a second controlled end of the second transistor is connected with both of an output end of the first inverter and an input end of the second inverter (BIJIVEMULA teaches the CAM cell include SRAM storage structure, [0022] of BIJIVEMULA, “…compare memory cell circuit 100 includes a six (6) transistor (6T) static random-access memory cell circuit 102...”)
Regarding independent claim 11, the combination of BIJIVEMULA, Jiang, Hu and Sohn teaches a processor comprising one or more content addressable memories ([0005] of BIJIVEMULA, “…a CAM array…”, Hu teaches integrating memory devices into a processor system, para(9) of Hu, “…command data received at the I/O buffer is provided on a command bus 112 to control logic 114. The command data received by the control logic 114 is then translated into internal timing and data signals that control the functionality of the CAM 100…”), wherein the one or more content addressable memory comprises:
a plurality of word lines (202 in figure 2 of BIJIVEMULA, [0025] of BIJIVEMULA, “…CAM array 200 including a row 202 of compare memory cell circuits 204…”);
a bit line bus ([0029] of BIJIVEMULA, “…A column compare circuit 232 receives a compare true bit 234T and a compare complement bit 234C…”, the compare true and complement lines function as bit lines used to communicate data to memory cells);
a plurality of memory cells (204 in figure 2 of BIJIVEMULA, [0025] of BIJIVEMULA, “…CAM array 200 including a row 202 of compare memory cell circuits 204…”) coupled with each of the word lines and the bit line bus;
a timing control circuit (“set clock circuit 530” indicated in [0042] of BIJIVEMULA, “…dynamic comparator circuit 524 includes a set clock circuit 530 that generates, to each decode column 502, a set clock signal 532…”, set clock circuit controls timing of comparison operations in the CAM array) configured to determine an operation mode according to a received bus command and generate a control signal for a corresponding operation mode, the operation mode comprising one of a read mode, a write mode, or a compare mode (Jiang teaches control circuitry determining operation modes based on received command, abstract of Jiang, “…first and second plurality of lines each perform different functions during read, write, and comparison modes...”, thus Jiang provides explicit mode selection logic determining memory operations, Hu teaches in col 3 that “command data received at the I/O buffer is provided on a command bus 112 to control logic 114. The command data received by the control logic 114 is then translated into internal timing and data signals that control the functionality of the CAM 100”. Hu further teaches write operation (para(15) of Hu), read operation (para(16) of Hu), and compare operation (para(17) of Hu);
an address line control circuit (“set address circuit 236” in figure 2 and [0030] of BIJIVEMULA, “…set clock signal 222 is generated by a set address circuit 236 and is activated by the clock signal CLK…”) coupled with the timing control circuit (“set clock circuit 530 “ indicated in [0042] of BIJIVEMULA), the word lines (202 in figure 2 of BIJIVEMULA) and the bit line bus and configured to activate a corresponding word line and the bit line bus based on the control signal ([0005] of BIJIVEMULA, “…a CAM array includes at least one decode column…”) and to perform a conversion of data bits from p bits to q bits according to the control signal for the corresponding operation mode; wherein p and q are integers and q is different from p (Sohn teaches circuitry for controlling the input/output width of data transferred during memory operation. Particularly, Sohn teaches in figures 4, 7-9 a decoder 100, which responds to read or write commands and generates an internal I/O width control signal WCON, data output buffer controller 200, which receives WCON and generates COUT. Data input buffer controller 300, which receives WCON and generates CIN. Data output buffer 800 and data input buffer 900, whose effective data widths are controlled by the respective signals); and
a processing and output circuit coupled with the bit line bus ([0029] of BIJIVEMULA, “…column compare circuit 232 generates the compare true data 216T and compare complement data 216C...”) and configured to read out data stored in the memory cells from the bit line bus in the read mode ([0026] of BIJIVEMULA, “…If the compare tag CT matches one of the binary tags BT stored in the CAM array 200, data corresponding to the binary tag BT can be accessed in the CAM array 200…”, BIJIVEMULA teaches memory cells storing binary data which may be accessed during operation, stored data is read for comparison operations), write data to be written from the bit line bus to the memory cells in the write mode (CAM memory cells inherently support write operations for storing tags), and compare data to be compared inputted from the bit line bus with data already stored in the memory cells and output a compare result in the compare mode ([0029] of BIJIVEMULA, “…column compare circuit 232 generates the compare true data 216T and compare complement data 216C...”, abstract of BIJIVEMULA, “…A row match circuit generates, for each row, in response to the set match signal, a row match signal indicating the compare tag matches the binary tag stored in the row…”, thus BIJIVEMULA teaches generating a matching signal based on comparison results).
Regarding claim 12, the combination of BIJIVEMULA, Jiang, Hu and Sohn teaches the processor according to claim 11, wherein the processor comprises a microprocessor unit (MCU) (Hu teaches processor-controlled CAM operations. It would have been obvious to implement the process as a microprocessor unit, sinch MCUs are conventional processors used to control memory system).
Regarding independent claim 13, the combination of BIJIVEMULA, Jiang, Hu and Sohn teaches a memory system comprising:
at least one memory device and a memory controller coupled with and controlling the memory device (Hu teaches memory controllers communicating with memory arrays), wherein: the memory device comprises:
a memory cell array and a peripheral circuit coupled with and controlling the memory cell array; at least one of the peripheral circuit or the memory controller comprises one or more processors, the one or more processors comprising one or more content addressable memories, wherein the content addressable memory comprises:
a plurality of word lines (202 in figure 2 of BIJIVEMULA, [0025] of BIJIVEMULA, “…CAM array 200 including a row 202 of compare memory cell circuits 204…”);
a bit line bus ([0029] of BIJIVEMULA, “…A column compare circuit 232 receives a compare true bit 234T and a compare complement bit 234C…”, the compare true and complement lines function as bit lines used to communicate data to memory cells);
a plurality of memory cells (204 in figure 2 of BIJIVEMULA, [0025] of BIJIVEMULA, “…CAM array 200 including a row 202 of compare memory cell circuits 204…”) coupled with each of the word lines and the bit line bus;
a timing control circuit (“set clock circuit 530” indicated in [0042] of BIJIVEMULA, “…dynamic comparator circuit 524 includes a set clock circuit 530 that generates, to each decode column 502, a set clock signal 532…”, set clock circuit controls timing of comparison operations in the CAM array) configured to determine an operation mode according to a received bus command and generate a control signal for a corresponding operation mode, the operation mode comprising one of a read mode, a write mode, or a compare mode (Jiang teaches control circuitry determining operation modes based on received command, abstract of Jiang, “…first and second plurality of lines each perform different functions during read, write, and comparison modes...”, thus Jiang provides explicit mode selection logic determining memory operations, Hu teaches in col 3 that “command data received at the I/O buffer is provided on a command bus 112 to control logic 114. The command data received by the control logic 114 is then translated into internal timing and data signals that control the functionality of the CAM 100”. Hu further teaches write operation (para(15) of Hu), read operation (para(16) of Hu), and compare operation (para(17) of Hu);
an address line control circuit (“set address circuit 236” in figure 2 and [0030] of BIJIVEMULA, “…set clock signal 222 is generated by a set address circuit 236 and is activated by the clock signal CLK…”) coupled with the timing control circuit (“set clock circuit 530 “ indicated in [0042] of BIJIVEMULA), the word lines (202 in figure 2 of BIJIVEMULA) and the bit line bus and configured to activate a corresponding word line and the bit line bus based on the control signal ([0005] of BIJIVEMULA, “…a CAM array includes at least one decode column…”) and to perform a conversion of data bits from p bits to q bits according to the control signal for the corresponding operation mode, wherein p and q are integers and q is different from p (Sohn teaches circuitry for controlling the input/output width of data transferred during memory operation. Particularly, Sohn teaches in figures 4, 7-9 a decoder 100, which responds to read or write commands and generates an internal I/O width control signal WCON, data output buffer controller 200, which receives WCON and generates COUT. Data input buffer controller 300, which receives WCON and generates CIN. Data output buffer 800 and data input buffer 900, whose effective data widths are controlled by the respective signals); and
a processing and output circuit coupled with the bit line bus ([0029] of BIJIVEMULA, “…column compare circuit 232 generates the compare true data 216T and compare complement data 216C...”) and configured to read out data stored in the memory cells from the bit line bus in the read mode ([0026] of BIJIVEMULA, “…If the compare tag CT matches one of the binary tags BT stored in the CAM array 200, data corresponding to the binary tag BT can be accessed in the CAM array 200…”, BIJIVEMULA teaches memory cells storing binary data which may be accessed during operation, stored data is read for comparison operations), write data to be written from the bit line bus to the memory cells in the write mode (CAM memory cells inherently support write operations for storing tags), and compare data to be compared inputted from the bit line bus with data already stored in the memory cells and output a compare result in the compare mode ([0029] of BIJIVEMULA, “…column compare circuit 232 generates the compare true data 216T and compare complement data 216C...”, abstract of BIJIVEMULA, “…A row match circuit generates, for each row, in response to the set match signal, a row match signal indicating the compare tag matches the binary tag stored in the row…”, thus BIJIVEMULA teaches generating a matching signal based on comparison results).
Claims 14-17 are rejected under 35 U.S.C. 103 as being unpatentable over BIJIVEMULA PG PUB 20220284945 (hereinafter BIJIVEMULA), in view of Jiang US Patent 5351208 (hereinafter Jiang), and Hu US Patent 7307860 (hereinafter Hu), further in view of Sohn PG PUB 20050071582 (hereinafter Sohn), for the reasons discussed above with respect to claims 4-7.
Allowable Subject Matter
Claims 5-8, 18-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The closest prior art to the present invention is BIJIVEMULA PG PUB 20220284945.
BIJIVEMULA discloses a CAM array of compare memory cell circuits includes a decode column corresponding to each set, and each set includes at least one row of the compare memory cell circuits. Each decode column receives a set clock signal addressing the corresponding set and generates a set match signal in each row of the corresponding set. A column compare circuit generates compare data indicating a bit of a compare tag. A row match circuit generates, for each row, in response to the set match signal, a row match signal indicating the compare tag matches the binary tag stored in the row. Circuits and loads in a decode column employed to generate the set clock signal correspond to circuits generating the row match signal in each column of the CAM array to reduce a timing margin of the match indication and decrease the access time for the CAM array.
Regarding claim 5 (and the respective dependent claims), the prior arts of record do not disclose or suggest the combination of all the limitations in the claim and the base claim, including: wherein data bits of the data to be written are m bits, data bits of the data to be written after being processed by the data conversion circuit are 2m bits.
Regarding claim 18 (and the respective dependent claims), the prior arts of record do not disclose or suggest the combination of all the limitations in the claim and the base claim, including: wherein data bits of the data to be written are m bits, data bits of the data to be written after being processed by the data conversion circuit are 2m bits.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled "Comments on Statement of Reasons for Allowance”.
Conclusion
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/XIAOCHUN L CHEN/Examiner, Art Unit 2824
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