DETAILED ACTION
This Office action responds to Applicant’s invention filed on 09/27/2024.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Amendment Status
The present Office action is made with all previously suggested amendments being fully considered. Accordingly, pending in this Office action are claims 1-20.
Information Disclosure Statement (IDS)
Acknowledgement is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. The IDS has been considered.
Specification Objection
The specification has been checked to the extend necessary to determine the presence of possible minor errors. However, the Applicant’s cooperation is requested in correcting any errors of which Applicant may become aware in the specification.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims.
Therefore, the vertical direction on which the first channel is stacked onto the second channel recited in claim 4 must be shown in the drawings or the feature(s) canceled from the claim(s). It is not clear from the drawings about the directionality of the channel stack.
Therefore, the first channel between n-doped regions and second channel between p-doped recited in claim 20 must be shown in the drawings or the feature(s) canceled from the claim(s).
No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim 2 is rejected under 35 U.S.C. 112(b) as being indefinite.
The claims are indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint regard as the invention.
Claim 2 recites the limitation "… the work-function metal layer is uniform thickness”. This limitation should be "… the work-function metal layer has uniform thickness”.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-8, and 10-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cheng (US 2023/0343847).
Regarding claim 1, Cheng shows (see, e.g., Cheng: figs. 15A-15B, 16A-16B, and 17A-17B, and annotated figs. 15A-15B) all aspects of a method of forming two or more gates in a gate-all-around (GAA) semiconductor device 10 (20N/20P) (see, e.g., Cheng: fig. 1 and par. [0015]) comprising:
Forming a first dielectric layer 221 (see, e.g., Cheng: fig. 15B, and formation of an N-type low threshold voltage (N-LVT) gate structure)
wherein:
A first portion of the first dielectric layer 221 overlays a first channel 22A (see, e.g., Cheng: fig. 15B)
wherein:
A second portion of the first dielectric layer overlays 221 (a part of the layer 222) a second channel 22A (see, e.g., Cheng: fig. 15A, and formation of an N-type ultra low threshold voltage (N-uLVT) gate structure)
Forming a doped dielectric portion of the first dielectric layer 221 (see, e.g., Cheng: fig. 15B) by doping the first portion of the first dielectric layer with a dopant (see, e.g., Cheng: fig. 15B, by using layer 400 and process 500; see also par. [0072])
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Forming a second dielectric layer 230 overlaying the first dielectric layer 221 (see, e.g., Cheng: fig. 15B)
Forming a work-function metal layer 700 overlaying the second dielectric layer 230 (see, e.g., Cheng: fig. 17B)
Regarding claim 2, Cheng shows (see, e.g., Cheng: figs. 15A-15B, 16A-16B, and 17A-17B, and annotated figs. 15A-15B) that the work-function metal layer has uniform thickness
Regarding claim 3, Cheng shows (see, e.g., Cheng: figs. 15A-15B, 16A-16B, and 17A-17B, and annotated figs. 15A-15B) that a first gate 200B formed with the first channel 22A has a first threshold voltage and a second gate 200A formed with the second channel 22A has a second threshold voltage different than the first threshold voltage (see, e.g., Cheng: par. [0072]).
Regarding claim 4, Cheng shows (see, e.g., Cheng: figs. 15A-15B, 16A-16B, and 17A-17B, and annotated figs. 15A-15B) that the first channel is vertically stacked onto the second channel (see, e.g., Cheng: fig. 23).
Regarding claim 5, Cheng shows (see, e.g., Cheng: figs. 15A-15B, 16A-16B, and 17A-17B, and annotated figs. 15A-15B) that:
Forming a second doped dielectric portion of the second dielectric layer 222 by doping a second portion of the second dielectric layer 222
wherein:
The second portion of the second dielectric layer 222 overlays the second portion of the first dielectric layer 221
Forming a third dielectric layer 230 overlaying the second dielectric layer 222 and under the work-function metal layer 700
Regarding claim 6, Cheng shows (see, e.g., Cheng: figs. 15A-15B, 16A-16B, and 17A-17B, and annotated figs. 15A-15B) that a third portion of the first dielectric layer 220 overlay a third channel 22A (see, e.g., Cheng: fig. 15C)
Regarding claim 7, Cheng shows (see, e.g., Cheng: figs. 15A-15B, 16A-16B, and 17A-17B, and annotated figs. 15A-15B) that:
A first portion of the work-function metal layer 700 has a first thickness
A second portion of the work-function metal layer 700 has a second thickness
wherein:
The first portion of the work-function metal layer 700 overlays a first portion of the second dielectric layer 230 corresponding to the first channel 22A
The second portion of the work-function metal layer 700 overlays a second portion of the second dielectric layer 222 corresponding to the second channel 22A
Regarding claim 8, Cheng shows (see, e.g., Cheng: figs. 15A-15B, 16A-16B, and 17A-17B, and annotated figs. 15A-15B) all aspects of a method of forming two or more gates in a gate-all-around (GAA) semiconductor device 10 (20N/20P) (see, e.g., Cheng: fig. 1 and par. [0015]) comprising:
Forming a first dielectric layer 221 over a channel 22A (see, e.g., Cheng: fig. 15B, and formation of an N-type low threshold voltage (N-LVT) gate structure)
Forming a doped dielectric layer 221 (see, e.g., Cheng: fig. 15B) by doping the first dielectric layer with a dopant (see, e.g., Cheng: fig. 15B, by using layer 400 and process 500; see also par. [0072])
Forming a second dielectric layer 230 overlaying the first dielectric layer 221 (see, e.g., Cheng: fig. 15B)
Forming a work-function metal layer 700 overlaying the second dielectric layer 230 (see, e.g., Cheng: fig. 17B)
Regarding claim 10, Cheng shows (see, e.g., Cheng: figs. 15A-15B, 16A-16B, and 17A-17B, and annotated figs. 15A-15B) that:
Forming a second doped dielectric layer 222 by doping the second dielectric layer with a second dopant (because there are two tuning dielectric layers 300 and 400 with different compositions, thus, they will produce different dopants) (see, e.g., Cheng: par. [0068])
Forming a third dielectric layer 230 overlaying the second dielectric layer 222 and under the work-function metal layer 700
Regarding claim 11, Cheng shows (see, e.g., Cheng: figs. 15A-15B, 16A-16B, and 17A-17B, and annotated figs. 15A-15B) that forming the first dielectric layer 221 includes forming the first dielectric layer 221 around all sides of the channel 22A (see, e.g., Cheng: fig. 23)
Regarding claim 12, Cheng shows (see, e.g., Cheng: figs. 15A-15B, 16A-16B, and 17A-17B, and annotated figs. 15A-15B) that the work-function metal layer 700 is a single metal alloy (see, e.g., Cheng: par. [0079]).
Regarding claim 13, Cheng shows (see, e.g., Cheng: figs. 15A-15B, 16A-16B, and 17A-17B, and annotated figs. 15A-15B) that the work-function metal layer 700 has a thickness of about 1.0 nm (see thickness 255) (see, e.g., Cheng: par. [0079]).
Regarding claim 14, Cheng shows (see, e.g., Cheng: figs. 15A-15B, 16A-16B, and 17A-17B, and annotated figs. 15A-15B) that the first dielectric layer 221has a thickness of about 5.0 angstroms (see thickness 225) (see, e.g., Cheng: par. [0064]).
Regarding claim 15, Cheng shows (see, e.g., Cheng: figs. 15A-15B, 16A-16B, and 17A-17B, and annotated figs. 15A-15B) all aspects of a gate-all-around (GAA) semiconductor device 10 (20N/20P) (see, e.g., Cheng: fig. 1 and par. [0015]) comprising:
A first channel 22A (see, e.g., Cheng: fig. 15B, and formation of an N-type low threshold voltage (N-LVT) gate structure)
wherein:
The first channel 22A is overlaid by a first dielectric layer 221
The first dielectric layer 221 overlaid by a second dielectric layer 230
A second channel 22A (see, e.g., Cheng: fig. 15A, and formation of an N-type ultra low threshold voltage (N-uLVT) gate structure)
wherein:
The second channel 22A is overlaid by a third dielectric layer 230
The first dielectric layer 221 is a doped dielectric layer 221
The third dielectric layer 230 is overlaid by a fourth dielectric layer 240 (see, e.g., Cheng: par. [0077])
A work-function metal layer 700 overlaying the second dielectric layer 230 and the fourth dielectric layer 240
The work-function metal layer 700 has a uniform thickness
Regarding claim 16, Cheng shows (see, e.g., Cheng: figs. 15A-15B, 16A-16B, and 17A-17B, and annotated figs. 15A-15B) that the first channel 22A and the second channel 22A are comprised of one or more nanotubes Cheng shows (see, e.g., Cheng: par. [0018]).
Regarding claim 17, Cheng shows (see, e.g., Cheng: figs. 15A-15B, 16A-16B, and 17A-17B, and annotated figs. 15A-15B) that a first gate 200B formed with the first channel 22A has a first threshold voltage and a second gate 200A formed with the second channel 22A has a second threshold voltage different than the first threshold voltage (see, e.g., Cheng: par. [0072]).
Regarding claim 18, Cheng shows (see, e.g., Cheng: figs. 15A-15B, 16A-16B, and 17A-17B, and annotated figs. 15A-15B) that the work-function metal layer 700 is a single metal alloy (see, e.g., Cheng: par. [0079]).
Regarding claim 19, Cheng shows (see, e.g., Cheng: figs. 15A-15B, 16A-16B, and 17A-17B, and annotated figs. 15A-15B) that the work-function metal layer 700 has a thickness of about 1.0 nm (see thickness 255) (see, e.g., Cheng: par. [0079]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Cheng in view of Huang (US 2024/0204073).
Regarding claim 9, Cheng shows (see, e.g., Cheng: figs. 15A-15B, 16A-16B, and 17A-17B, and annotated figs. 15A-15B) most aspects of a method of forming two or more gates in a gate-all-around (GAA) semiconductor device 10 (20N/20P) (see, e.g., Cheng: fig. 1 and par. [0015]) comprising the method step of forming the doped dielectric layer that includes:
Forming a dipole material layer 300 over the first dielectric layer 221 (see, e.g., Cheng: par. [0066])
Forming a cap layer 400 over the dipole material layer 300
Annealing 500 the semiconductor device 10
Removing the dipole material layer 300 and the cap layer 400
However, Cheng fails (see, e.g., Cheng: figs. 15A-15B, 16A-16B, and 17A-17B, and annotated figs. 15A-15B) to show that the cap layer 400 comprises metal. Cheng shows (see, e.g., Cheng: figs. 15A-15B, 16A-16B, and 17A-17B, and annotated figs. 15A-15B) that the cap layer 400 comprises a magnesium oxide (see, e.g., Cheng: par. [0068]).
Huang, in a similar device to Cheng, also teaches (see, e.g., Huang: fig. 2J-2) that the cap layer 184 comprises metal (see, e.g., Huang: par. [0072]).
Therefore, it would have been obvious at the time of the invention to one of ordinary skill in the art to use either the magnesium oxide cap layer of Cheng or the metal cap layer of Huang because these were recognized in the semiconductor art for their use as cap layers in doping dielectric layers in semiconductor devices, as taught by Cheng and by Huang, and selecting between known equivalents would be within the level of ordinary skill in the art. KSR International Co. v. Teleflex Inc., 550 U.S.--,82 USPQ2d 1385 (2007).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Cheng.
Regarding claim 20, Cheng shows (see, e.g., Cheng: figs. 15A-15B, 16A-16B, and 17A-17B, and annotated figs. 15A-15B) all aspects of a gate-all-around (GAA) semiconductor device 10 (20N/20P) (see, e.g., Cheng: fig. 1 and par. [0015]) comprising:
A first channel 22A that is between n-doped regions (see, e.g., Cheng: fig. 15B, and formation of an N-type low threshold voltage (N-LVT) gate structure)
A second channel 22A (see, e.g., Cheng: fig. 15A, and formation of an N-type ultra low threshold voltage (N-uLVT) gate structure)
However, Cheng fails (see, e.g., Cheng: figs. 15A-15B, 16A-16B, and 17A-17B, and annotated figs. 15A-15B) to show that the second channel 22A is between p-doped channels. Cheng shows (see, e.g., Cheng: figs. 15A-15B, 16A-16B, and 17A-17B, and annotated figs. 15A-15B) that the second channel 22A is between n-doped regions.
Cheng, in a similar device to Cheng, also teaches (see, e.g., Cheng: figs. 15F) that the second channel is between p-regions.
Therefore, it would have been obvious at the time of the invention to one of ordinary skill in the art to use either the second channel between n-regions of Cheng or the second channel between p-regions of Cheng because these were recognized in the semiconductor art for their use as channels of transistors in semiconductor devices, as taught by Cheng and by Cheng, and selecting between known equivalents would be within the level of ordinary skill in the art. KSR International Co. v. Teleflex Inc., 550 U.S.--,82 USPQ2d 1385 (2007).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TIBERIU DAN ONUTA whose telephone number is (571) 270-0074 and between the hours of 9:00 AM to 5:00 PM (Eastern Standard Time) Monday through Friday or by e-mail via Tiberiu.Onuta@uspto.gov. If attempts to reach the examiner by telephone or email are unsuccessful, the examiner's supervisor, Wael Fahmy, can be reached on (571) 272-1705.
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/TIBERIU DAN ONUTA/Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814
