DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1-7 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-7 of U.S. Patent No. US 11, 942, 493. Although the claims at issue are not identical, they are not patentably distinct from each other because Claim 1-7 of the instant applciaiton are a broader recitations of Claims 1-7 of U.S. Patent No. US 11, 942, 493.
Instant Application
US 11, 942, 493
Claim 1: A light detecting device, comprising: a light receiving element; and a read circuit configured to read an electrical signal photoelectrically converted by the light receiving element, wherein a field effect transistor included in the read circuit includes: a semiconductor layer in which a channel is formed; a gate electrode configured to cover the semiconductor layer; and a gate insulating film disposed between the semiconductor layer and the gate electrode, wherein the semiconductor layer includes a first side surface, and wherein a crystal plane of the first side surface is a (100) plane or a plane equivalent to the (100) plane.
Claim 1: An imaging device, comprising: a light receiving element; and a read circuit configured to read an electrical signal photoelectrically converted by the light receiving element, wherein a field effect transistor included in the read circuit includes a semiconductor layer in which a channel is formed, a gate electrode configured to cover the semiconductor layer, and a gate insulating film disposed between the semiconductor layer and the gate electrode, the semiconductor layer includes a main surface, and a first side surface located on one end side of the main surface in a gate width direction of the field effect transistor, the gate electrode includes a first portion configured to face the main surface via the gate insulating film, and a second portion configured to face the first side surface via the gate insulating film, and a crystal plane of the first side surface is a (100) plane or a plane equivalent to the (100) plane.
Claim 2: The light detecting device according to claim 1, wherein the semiconductor layer further includes a second side surface opposite to the first side surface, and wherein a crystal plane of the second side surface is a (100) plane or a plane equivalent to the (100) plane.
Claim 2: The imaging device according to claim 1, wherein the semiconductor layer further includes a second side surface located on the other end side of the main surface in the gate width direction, the gate electrode further includes a third portion configured to face the second side surface via the gate insulating film, and a crystal plane of the second side surface is a (100) plane or a plane equivalent to the (100) plane.
3. The light detecting device according to claim 1, wherein the semiconductor layer further includes a main surface, and wherein a crystal plane of the main surface is a (100) plane or a plane equivalent to the (100) plane.
3. The imaging device according to claim 1, wherein a crystal plane of the main surface is a (100) plane or a plane equivalent to the (100) plane.
4. The light detecting device according to claim 1, wherein the read circuit includes, as the field effect transistor, an amplification transistor configured to amplify the electrical signal.
4. The imaging device according to claim 1, wherein the read circuit includes, as the field effect transistor, an amplification transistor configured to amplify the electrical signal.
5. The light detecting device according to claim 4, wherein the read circuit further includes, as the field effect transistor, a selection transistor configured to switch a connection between the amplification transistor and a signal line on or off.
6: The imaging device according to claim 4, wherein the read circuit further includes, as the field effect transistor, a selection transistor configured to switch connection between the amplification transistor and a signal line on or off.
6. The light detecting device according to claim 4, wherein the read circuit further includes, as the field effect transistor, a reset transistor configured to switch a connection between a floating diffusion for temporarily holding an electrical signal output from the light receiving element and a power supply line on or off.
6. The light detecting device according to claim 4, wherein the read circuit further includes, as the field effect transistor, a reset transistor configured to switch a connection between a floating diffusion for temporarily holding an electrical signal output from the light receiving element and a power supply line on or off.
7. The light detecting device according to claim 1, wherein the field effect transistor includes a plurality of the semiconductor layers, and wherein the plurality of the semiconductor layers are disposed side by side at intervals in a gate width direction of the field effect transistor
7. The imaging device according to claim 1, wherein the field effect transistor includes a plurality of the semiconductor layers, and the plurality of the semiconductor layers are disposed side by side at intervals in the gate width direction of the field effect transistor.
Drawings
The drawing filed on 09/27/2024 is in compliance with MPEP 608.03 and therefore is accepted.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-8 are rejected under 35 U.S.C. 103 as being unpatentable over Adachi (US 20070290238 A1) in view of Huang et al. (US 20210098450 A1; hereafter Huang).
As of claim 1: Adachi teaches a light detecting device (¶¶0034 and note that a CMOS image sensor. FIG. 1. Each pixel is a so-called 5-transistor type CMOS image sensor comprised of a photodiode PD that receives light to generate and store photocharge), comprising: a light receiving element (PD); and a read circuit configured to read an electrical signal photoelectrically converted by the light receiving element, wherein a field effect transistor included in the read circuit includes: a semiconductor layer in which a channel is formed (¶¶0040,0045 and note that gate electrode 60 made of polysilicon is formed via gate insulating film 50 made of silicon oxide on the top of p-well (first semiconductor layer) 11 formed in an n-type semiconductor substrate. A pair of n+-type semiconductor regions (second semiconductor layer) (40, 41) is formed on the surface layer of p-well 11 on both sides of gate electrode 60. n+-type semiconductor regions (40, 41) are used as source/drain); a gate electrode configured to cover the semiconductor layer; and a gate insulating film disposed between the semiconductor layer and the gate electrode, wherein the semiconductor layer includes a first side surface (¶¶0045-0047 and note that gate electrode 60 made of polysilicon is formed via gate insulating film 50 made of silicon oxide on the top of p-well (first semiconductor layer) 11 formed in an n-type semiconductor substrate. A pair of n+-type semiconductor regions (second semiconductor layer) (40, 41) is formed on the surface layer of p-well 11 on both sides of gate electrode 60. n+-type semiconductor regions (40, 41) are used as source/drain. In this way, source follower Tr4 is formed as an n-channel type field effect transistor having a channel forming region on the surface layer of p-well 11.).
Huang is a similar or analogous system to the claimed invention as evidenced Huang teaches scale down the dimensions of semiconductor devices, such as metal oxide semiconductor field effect transistors (MOSFETs), including planar MOSFETs, fin field effect transistors (finFETs), and nano-sheet FETs. Such scaling down has increased the complexity of semiconductor manufacturing processes that would have prompted a predictable variation of Adachi by applying Huang’s known principal of wherein a crystal plane of the first side surface is a (100) plane or a plane equivalent to the (100) plane (¶¶0025,0027,0050 and note that Substrate 102 can be a bulk semiconductor wafer or the top semiconductor layer of a semiconductor-on-insulator (SOI) wafer (not shown), such as silicon-on-insulator. In some embodiments, substrate 102 can include a crystalline semiconductor layer with its top surface 102.sub.t parallel to (100), (110), (111), or c-(0001) crystal plane.).
In view of the motivations such as finding the optimal electron mobility in the transistor thereby providing a robust platform and flexible design window for the implementing integrated circuits with multiple functionalities (e.g., system on chip) as disclosed in ¶0091 and one of ordinary skill in the art would have implemented the claimed variation of the prior art system of Adachi.
Therefore, the claimed invention would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention.
As of claim 2: Adachi in view of Huang further teaches the semiconductor layer further includes a second side surface opposite to the first side surface, and wherein a crystal plane of the second side surface is a (100) plane or a plane equivalent to the (100) plane (Huang ¶¶0025,0057,0060 substrate 102 can include a crystalline semiconductor layer with its top surface 102.sub.t parallel to (100), (110), (111), or c-(0001) crystal plane,).
As of claim 3: Adachi in view of Huang further teaches the semiconductor layer further includes a main surface, and wherein a crystal plane of the main surface is a (100) plane or a plane equivalent to the (100) plane(Huang ¶¶0057,0060 and noteFIG. 4, in operation 330, a channel layer is formed over each of the first recess. For example, as shown in FIGS. 6B and 7B, channel layer 716 can be selectively grown over recess 601's bottom surface 603 to form vertical structure 706B for finFET 100B. The top surface 701 of channel layer 716 can include one or more (111) crystal facets.).
As of claim 4: Adachi in view of Huang further teaches the read circuit includes, as the field effect transistor, an amplification transistor configured to amplify the electrical signal (Adachi ¶¶0031, 0034, 0077).
As of claim 5: Adachi in view of Huang further teaches the read circuit further includes, as the field effect transistor, a selection transistor configured to switch a connection between the amplification transistor and a signal line on or off (Adachi ¶¶0031, 0035, 0045,0048).
As of claim 6: Adachi in view of Huang further teaches the read circuit further includes, as the field effect transistor, a reset transistor configured to switch a connection between a floating diffusion for temporarily holding an electrical signal output from the light receiving element and a power supply line on or off (Adachi ¶¶0035, 0061, 0095, 0098).
As of claim 7: Adachi in view of Huang further teaches the field effect transistor includes a plurality of the semiconductor layers, and wherein the plurality of the semiconductor layers are disposed side by side at intervals in a gate width direction of the field effect transistor (Adachi ¶0037 and Huang ¶0091).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Adachi (US 20070290238 A1) in view of Huang et al. (US 20210098450 A1; hereafter Huang), and further in view of Ohnuma (US 20090057726 A1; hereafter Ohnuma).
As of claim 8: Adachi teaches a signal processing circuit configured to process a signal output from the light detecting device, wherein the light detecting device comprises: a light detecting device (¶¶0034 and note that a CMOS image sensor. FIG. 1. Each pixel is a so-called 5-transistor type CMOS image sensor comprised of a photodiode PD that receives light to generate and store photocharge), comprising: a light receiving element (PD); and a read circuit configured to read an electrical signal photoelectrically converted by the light receiving element, wherein a field effect transistor included in the read circuit includes: a semiconductor layer in which a channel is formed (¶¶0040,0045 and note that gate electrode 60 made of polysilicon is formed via gate insulating film 50 made of silicon oxide on the top of p-well (first semiconductor layer) 11 formed in an n-type semiconductor substrate. A pair of n+-type semiconductor regions (second semiconductor layer) (40, 41) is formed on the surface layer of p-well 11 on both sides of gate electrode 60. n+-type semiconductor regions (40, 41) are used as source/drain); a gate electrode configured to cover the semiconductor layer; and a gate insulating film disposed between the semiconductor layer and the gate electrode, wherein the semiconductor layer includes a first side surface (¶¶0045-0047 and note that gate electrode 60 made of polysilicon is formed via gate insulating film 50 made of silicon oxide on the top of p-well (first semiconductor layer) 11 formed in an n-type semiconductor substrate. A pair of n+-type semiconductor regions (second semiconductor layer) (40, 41) is formed on the surface layer of p-well 11 on both sides of gate electrode 60. n+-type semiconductor regions (40, 41) are used as source/drain. In this way, source follower Tr4 is formed as an n-channel type field effect transistor having a channel forming region on the surface layer of p-well 11.).
Huang is a similar or analogous system to the claimed invention as evidenced Huang teaches scale down the dimensions of semiconductor devices, such as metal oxide semiconductor field effect transistors (MOSFETs), including planar MOSFETs, fin field effect transistors (finFETs), and nano-sheet FETs. Such scaling down has increased the complexity of semiconductor manufacturing processes that would have prompted a predictable variation of Adachi by applying Huang’s known principal of wherein a crystal plane of the first side surface is a (100) plane or a plane equivalent to the (100) plane (¶¶0025,0027,0050 and note that Substrate 102 can be a bulk semiconductor wafer or the top semiconductor layer of a semiconductor-on-insulator (SOI) wafer (not shown), such as silicon-on-insulator. In some embodiments, substrate 102 can include a crystalline semiconductor layer with its top surface 102.sub.t parallel to (100), (110), (111), or c-(0001) crystal plane.).
In view of the motivations such as finding the optimal electron mobility in the transistor thereby providing a robust platform and flexible design window for the implementing integrated circuits with multiple functionalities (e.g., system on chip) as disclosed in ¶0091 and one of ordinary skill in the art would have implemented the claimed variation of the prior art system of Adachi.
Therefore, the claimed invention would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention.
Ohnuma is a similar or analogous system to the claimed invention as evidenced Ohnuma teaches scale down the dimensions of semiconductor devices, such as metal oxide semiconductor field effect transistors (MOSFETs), including planar MOSFETs, fin field effect transistors (finFETs), and nano-sheet FETs. Such scaling down has increased the complexity of semiconductor manufacturing processes that would have prompted a predictable variation of Adachi by applying Ohnuma’s known principal of an electronic device, comprising: an optical component; a light detecting device on which light transmitted through the optical component is incident (¶¶0234-0236 and note that he electronic device manufactured using the semiconductor device of the present invention include a camera such as a video camera or a digital camera).
In view of the motivations such as capturing images using efficient transitors thereby providing a high-performance semiconductor device is successfully provided as disclosed in ¶0007 and one of ordinary skill in the art would have implemented the claimed variation of the prior art system of Adachi.
Therefore, the claimed invention would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
KUROKAWA (US 2017/0025415 A1) teaches the gate of the transistor 704 is electrically connected to the node 707. One of a source and a drain of the transistor 704 is electrically connected to a wiring 709. The other of the source and the drain of the transistor 704 is electrically connected to one of a source and a drain of the transistor 705. The other of the source and the drain of the transistor 705 is electrically connected to the wiring 708. One electrode of the capacitor 706 is electrically connected to the node 707. The other electrode of the capacitor 706 is electrically connected to the wiring 711 (See ¶0232).
KUDOH (US 2019/0123079) teaches a region on a semiconductor substrate 41, sandwiched between the fin portions 47-1 and 47-2 of the gate electrode 44 includes an N-type channel portion 49 formed across the source and the drain, so as to be in contact with side surfaces of the fin portions 47-1 and 47-2 via the insulating film 48. For example, the region where the N-type channel portion 49 is formed, that is, a region sandwiched between the two fin portions 47-1 and 47-2 has a width S set to be narrower than a depth D of the fin portions 47-1 and 47-2. For example, using a configuration having a large width S of this region would lower the modulation depth due to a back bias effect from the P-type semiconductor substrate 41. Accordingly, the channel portion 49 is formed to have the width S and the depth D that would not lower the modulation depth. Furthermore, the channel portion 49 is sandwiched between the fin portions 47-1 and 47-2 so as to allow a bottom surface side alone of the channel portion 49 to be in contact with the semiconductor substrate 41 (well), making it possible to suppress the back bias effect (See ¶0038).
Okamato (US 2014/0374571) teaches in [0051] In FIG. 7, wells EA and EB are formed in a semiconductor substrate SB. Electrodes GA1 and GA2 are formed over the well EA via gate insulation films ZA1 and ZA2, respectively. Electrodes GB1 and GB2 are formed over the well EB via gate insulation films ZB1 and ZB2, respectively. Note that the electrodes GA1 and GA2 can constitute a positive electrode of the nonlinear capacitance CA1, and the well EA can constitute a negative electrode of the nonlinear capacitance CA1. The electrodes GB1 and GB2 can constitute a positive electrode of the nonlinear capacitance CB1, and the well EB can constitute a negative electrode of the nonlinear capacitance CB1.
SUYAMA et al. (US 2013/0107097) teaches in [0050] at the one end 12a of the imaging plane 12, N first signal readout circuits 20 are arranged for each of the columns. Each of these first signal readout circuits 20 has a transistor (a FET in the present embodiment) 21 and a signal output bonding pad 22. A control terminal (gate) of the transistor 21 is electrically connected with a terminal end of the one end 12a side of a corresponding pixel column in the imaging plane 12. The potential of this control terminal becomes larger as the amount of a charge taken out of said pixel column increases. One current terminal (drain) of the transistor 21 is electrically connected to a bonding pad 24 via a wiring 23 commonly provided over the N columns. To this bonding pad 24, a voltage of a predetermined magnitude is always applied. The other current terminal (source) of the transistor 21 is electrically connected to the signal output bonding pad 22. In the case of the first operation mode, when a charge is transferred up to the one end 12a in a certain pixel column, a voltage according to the amount of that charge is applied to the control terminal of the transistor 21 of said column. Accordingly, a current of a magnitude according to said amount of charge is output from the other current terminal of said transistor 21 and taken out via the signal output bonding pad 22.
Ohsawa (US 2007/0189094 A1) teaches in [0006] If the FBC memory cell is an n-type FET, parts of electrons in an inversion layer are trapped by an interface state on an interface between a gate oxide film and the body region when the FBC memory cell is turned on. The holes accumulated in the body region are recombined with the electrons and disappear. If a word line is activated between a refresh operation and a next refresh operation, data is not written back to an unselected FBC memory cell. Due to this, if the unselected memory cell is repeatedly turned on and off during reading or writing of the data from or to a selected memory cell, the number of holes accumulated in the body region of the unselected memory cell that stores the data "1" therein gradually decreases. As a result, the data "1" in the unselected memory cell is changed to data "0".
Muralidhar et al. (US 2011/0053361) teaches in the abstract fabrication of a semiconductor structure comprises providing a substrate structure (15) comprising a pair of single crystal semiconductor layers; patterning and etching the second single crystal semiconductor layer to form a single crystal patterned structure having vertical sidewalls; oxidizing to grow oxide spacers on the sidewalls; selectively removing a remaining portion of the patterned structure while retaining the spacers; and selectively etching the first single crystal semiconductor layer to leave fin-shaped field effect transistor (FinFET) (12) channel regions patterned.
Contacts
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MEKONNEN D DAGNEW whose telephone number is (571)270-5092. The examiner can normally be reached on 8:00AM-5:00PM M-Th.
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/MEKONNEN D DAGNEW/Primary Examiner, Art Unit 2638