DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d).
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 09/27/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner and made of record.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-8 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over YOSHIMATSU; Naoki (US 20160099224 A1) “YOSHIMATSU et al.” in view of ASAI; Tatsuhiko (US 20180076149 A1) “ASAI” further in view of SAEGUSA; Naoki (US 11145584 B2) “SAEGUSA”
Regarding Independent Claim 1, YOSHIMATSU et al. Figs. 1-5 discloses, a semiconductor device (“semiconductor device” ¶ [0032]), comprising:
a semiconductor chip (“the semiconductor elements 5 and 6” ¶ [0034]) including a main electrode (“an electrode formed on an upper surface of each of the semiconductor element 5 and the semiconductor element 6” ¶ [0034]) on a front surface thereof (“an upper surface of each of the semiconductor element 5 and the semiconductor element 6” ¶ [0034]);
a first conductive plate 3 (“circuit pattern 3 (first circuit pattern)” ¶ [0034]) having a first main surface (upper surface of pattern 3) with a chip area (region of pattern 3 under element 5 and 6) defined thereon, a rear surface of the semiconductor chip (lower surface of 5 and 6) being bonded to the chip area (“A semiconductor element 5 and a semiconductor element 6 are bonded on the circuit pattern 3 through a brazing material 13.” ¶ [0025]);
a second conductive plate 4 (“circuit pattern 4 (second circuit pattern)” ¶ [0033]) provided adjacent to the first conductive plate 3 in a plan view of the semiconductor device (“the circuit pattern 4 is provided on the insulating layer 2, and separated (insulated) from the circuit pattern 3.” ¶ [0035]; Fig. 1 is a plan view);
a supporting part provided adjacent to the first conductive plate in the plan view, and being insulated from the first conductive plate, the supporting part and the second conductive plate being on two opposite sides of the chip area (“the wiring terminal 8 is partially in contact with the insulating substrate 1 through the circuit pattern 4, and is in contact with the insulating substrate 1 at several positions on opposite sides of the semiconductor elements 5 and 6 in a planar view. Furthermore, the circuit pattern 4 is provided on the insulating layer 2, and separated (insulated) from the circuit pattern 3.” ¶ [0035]; Fig. 1 is a plan view); and
a lead frame (“A wiring terminal 8” ¶ [0026]), including
a first bonding part bonded to the supporting part, a second bonding part bonded to the second conductive plate (“the wiring terminal 8 is bonded with the brazing material 14 (second brazing material) on an electrode formed on an upper surface of each of the semiconductor element 5 and the semiconductor element 6 (this electrode is provided on each of the semiconductor elements 5 and 6 on an opposite side of the circuit pattern 3 (first circuit pattern)). The semiconductor elements 5 and 6 are bonded on the circuit pattern 3 with the brazing material 13 (first brazing material). Furthermore, the wiring terminal 8 is formed so as to partially protrude (at two sections).” ¶ [0034]), and
an electrode bonding part bonded to the main electrode of the semiconductor chip via a bonding member (“the wiring terminal 8 is bonded to the electrode formed on the upper surface of each of the semiconductor elements 5 and 6 through the brazing material 14” ¶ [0037]).
However, YOSHIMATSU et al. does not explicitly disclose a supporting part provided adjacent to the first conductive plate in the plan view, and being insulated from the first conductive plate, the supporting part and the second conductive plate being on two opposite sides of the chip area and a first bonding part bonded to the supporting part.
In the similar field of endeavor of semiconductor devices, ASAI Figs. 1-4B discloses a supporting part provided adjacent to the first conductive plate in the plan view, and a first bonding part bonded to the supporting part (“a first bonding portion in contact with the semiconductor element, a second bonding portion in contact with the electrode pattern, and an interconnect portion connecting the first and the second bonding portions. The first and the second bonding portions have a width that is wider than a width of the interconnect portion.” ¶ [0016]; “bonding portion 6a (a first bonding portion) bonded to the power semiconductor chip 1 by the bonding member 3a, the bonding portion 6b (a second bonding portion) bonded to the electrode pattern 4 on the front surface by the bonding member 3b, and an interconnect portion 6c connecting the bonding portion 6a and the bonding portion 6b. In the interconnect portion 6c, a portion orthogonal to the bonding portions 6a, 6b may be called a raised portion 6d.” ¶ [0034]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify bonding structure of YOSHIMATSU et al. with the bonding structure of ASAI in order to reduce the stress applied to the upper surface of the power semiconductor chip (ASAI, ¶ [0036]).
However, ASAI does not disclose, a supporting part being insulated from the first conductive plate and the supporting part and the second conductive plate being on two opposite sides of the chip area.
In the similar field of endeavor or semiconductor device SAEGUSA Figs. 1-5 and 15-19 discloses, a supporting part being insulated from the first conductive plate and the supporting part and the second conductive plate being on two opposite sides of the chip area (“a pressing portion mechanically and directly contacted with an upper surface of the circuit board at a location spaced apart from the semiconductor element in a width direction of the circuit board, the upper surface of the circuit board being located below a bottom surface of the semiconductor element.” Claim 1; The contact portion of the first pressing portion 51a is directly contacted with a contact region defined on an upper surface of the first contact pattern layer 17a. For example, in a planar pattern as seen from above, the first contact pattern layer 17a is formed into a rectangular shape larger than the contact portion of the first pressing portion 51a” Column 15, Lines 25-31)
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify bonding structure of YOSHIMATSU et al. with the bonding structure of ASAI and further using the arrangement of SAEGUSA in order to improve yield and non-defective rate, enhance reliability, and extend life expectancy of product (Column 15, Lines 59-61).
Regarding Claim 2, YOSHIMATSU et al. as modified by ASAI and SAEGUSA discloses the limitations of claim 1. YOSHIMATSU et al. Figs. 1-5 further show gap between pattern 3 and pattern 4 that defines an opening region in the plan view (Fig. 1 is a planar view),
However, YOSHIMATSU et al. does not explicitly disclose wherein the first conductive plate has a recess and does not disclose the supporting part is disposed in the opening region, and the supporting part is spaced apart from the first conductive plate.
In the similar field of endeavor of semiconductor devices, SAEGUSA Figs. 15-16 discloses the first conductive plate has a recess (“a part of which is cut out to avoid the first contact pattern layer 17a” Column 15, Lines 34-35), the supporting part is disposed in the opening region (17a is in the cut out region), and the supporting part is spaced apart from the first conductive plate (“The first contact pattern layer 17a is separated from the first circuit pattern layer 12a,” Column 15, Lines 31-32).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify bonding structure of YOSHIMATSU et al. with the bonding structure of ASAI and further using the arrangement of SAEGUSA in order to improve yield and non-defective rate, enhance reliability, and extend life expectancy of product (Column 15, Lines 59-61).
Regarding Claim 3, YOSHIMATSU et al. as modified by ASAI and SAEGUSA discloses the limitations of claim 2. However, YOSHIMATSU et al. does not disclose wherein the supporting part is made of a same material as the first conductive plate.
In the similar field of endeavor or semiconductor device SAEGUSA Figs. 1-5 and 15-19 discloses, wherein the supporting part is made of a same material as the first conductive plate (“metal pattern layers formed to have the same thickness from the same material as those of the circuit pattern layer group” Column 15, Lines 22-24).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify bonding structure of YOSHIMATSU et al. with the bonding structure of ASAI and further using the arrangement of SAEGUSA in order to improve yield and non-defective rate, enhance reliability, and extend life expectancy of product (Column 15, Lines 59-61).
Regarding Claim 4, YOSHIMATSU et al. as modified by ASAI and SAEGUSA discloses the limitations of claim 1. YOSHIMATSU et al. Figs. 1-5 further disclose wherein, in the lead frame, a first length spanning from the electrode bonding part to the first bonding part is equal to a second length spanning from the electrode bonding part to the second bonding part (“the wiring terminal 8 is partially in contact with the insulating substrate 1 through the circuit pattern 4, and is in contact with the insulating substrate 1 at several positions on opposite sides of the semiconductor elements 5 and 6 in a planar view.” ¶ [0035]; Figs 3 and 5 show same height for the vertical part of 8 in two sides).
However, YOSHIMATSU et al. does not explicitly state a first length spanning from the electrode bonding part to the first bonding part is equal to a second length spanning from the electrode bonding part to the second bonding part.
In the similar field of endeavor of semiconductor devices, ASAI Figs. 1-4B discloses a first length spanning from the electrode bonding part to the first bonding part is equal to a second length spanning from the electrode bonding part to the second bonding part (“both ends of the interconnect portion 6c are shortened by the same amount, having a shape connecting a central portion of the side p1 of the bonding portion 6a and a central portion of the side p2 of the bonding portion 6b” ¶ [0035]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify bonding structure of YOSHIMATSU et al. with the bonding structure of ASAI in order to reduce the stress applied to the upper surface of the power semiconductor chip (ASAI, ¶ [0036]).
In the similar field of endeavor or semiconductor device SAEGUSA Figs. 1-5 and 15-19 discloses, a first length spanning from the electrode bonding part to the first bonding part is equal to a second length spanning from the electrode bonding part to the second bonding part (“Respective contact portions of the first pressing portion 51a and the second pressing portion 51d and the bonding portions 31a to 31d are preferably arranged to have a mirror image symmetry.” Column 10, Lines 15-18).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify bonding structure of YOSHIMATSU et al. with the bonding structure of ASAI and further using the teaching of SAEGUSA in order to improve yield and non-defective rate, enhance reliability, and extend life expectancy of product (Column 15, Lines 59-61).
Regarding Claim 5, YOSHIMATSU et al. as modified by ASAI and SAEGUSA discloses the limitations of claim 1. YOSHIMATSU et al. Figs. 1-5 further discloses the wiring terminal 8 is partially bent toward the insulating substrate 1 and The protruding sections of the wiring terminal 8 extend toward the insulating substrate 1.
However, YOSHIMATSU et al. does not explicitly state a first linking part of a plate shape, connecting between the electrode bonding part and the first bonding part, and a second linking part of the plate shape, connecting between the electrode bonding part and the second bonding part, and
a first height spanning from the first bonding part to the first linking part and a second height spanning from the second bonding part to the second linking part are greater than a third height spanning from the electrode bonding part to the first linking part and a fourth height spanning from the electrode bonding part to the second linking part, respectively.
In the similar field of endeavor of semiconductor devices, ASAI Figs. 1-4B discloses a first linking part of a plate shape, connecting between the electrode bonding part and the first bonding part, and a second linking part of the plate shape, connecting between the electrode bonding part and the second bonding part (“In the interconnect portion 6c, a portion orthogonal to the bonding portions 6a, 6b may be called a raised portion 6d.” ¶ [0034]; “In the interconnect portion 6c, a portion orthogonal to the bonding portions 6a, 6b may be called a raised portion 6d.” ¶ [0044]), and
a first height spanning from the first bonding part to the first linking part and a second height spanning from the second bonding part to the second linking part are greater than a third height spanning from the electrode bonding part to the first linking part and a fourth height spanning from the electrode bonding part to the second linking part, respectively (bonding portion 6a on the chip’s upper surface vs 6b on the electrode pattern shows the height difference for the second and fourth heights).
Furthermore 2144.04(VI) states “Duplication of Parts: In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960) (Claims at issue were directed to a water-tight masonry structure wherein a water seal of flexible material fills the joints which form between adjacent pours of concrete. The claimed water seal has a "web" which lies in the joint, and a plurality of "ribs" projecting outwardly from each side of the web into one of the adjacent concrete slabs. The prior art disclosed a flexible water stop for preventing passage of water between masses of concrete in the shape of a plus sign (+). Although the reference did not disclose a plurality of ribs, the court held that mere duplication of parts has no patentable significance unless a new and unexpected result is produced.”. Therefore, the first and third height can be achieved by duplication of the bonding portions of ASAI into the YOSHIMATSU et al. structure.
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify bonding structure of YOSHIMATSU et al. with the bonding structure of ASAI in order to reduce the stress applied to the upper surface of the power semiconductor chip (ASAI, ¶ [0037]).
Regarding Claim 6, YOSHIMATSU et al. as modified by ASAI and SAEGUSA discloses the limitations of claim 1. However, YOSHIMATSU et al. does not disclose wherein the lead frame extends linearly from the electrode bonding part to the first bonding part in the plan view.
In the similar field of endeavor of semiconductor devices, ASAI Figs. 1-4B discloses wherein the lead frame extends linearly from the electrode bonding part to the first bonding part in the plan view (“the interconnect portion 6c are shortened by the same amount, having a shape connecting a central portion of the side p1 of the bonding portion 6a and a central portion of the side p2 of the bonding portion 6b. In particular, the interconnect portion 6c has a shape connecting the interconnect portion 6c and the bonding portions 6a, 6b at the central portions thereof with respect to width. When the lead frame interconnection is created from a rectangular plate” ¶ [0035])
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify bonding structure of YOSHIMATSU et al. with the bonding structure of ASAI in order to reduce the stress applied to the upper surface of the power semiconductor chip (ASAI, ¶ [0037]).
Regarding Claim 7, YOSHIMATSU et al. as modified by ASAI and SAEGUSA discloses the limitations of claim 6. However, YOSHIMATSU et al. does not disclose wherein the lead frame extends linearly from the electrode bonding part to the second bonding part in the plan view.
In the similar field of endeavor of semiconductor devices, ASAI Figs. 1-4B discloses wherein the lead frame extends linearly from the electrode bonding part to the second bonding part in the plan view (“the interconnect portion 6c are shortened by the same amount, having a shape connecting a central portion of the side p1 of the bonding portion 6a and a central portion of the side p2 of the bonding portion 6b. In particular, the interconnect portion 6c has a shape connecting the interconnect portion 6c and the bonding portions 6a, 6b at the central portions thereof with respect to width. When the lead frame interconnection is created from a rectangular plate” ¶ [0035])
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify bonding structure of YOSHIMATSU et al. with the bonding structure of ASAI in order to reduce the stress applied to the upper surface of the power semiconductor chip (ASAI, ¶ [0037]).
Regarding Claim 8, YOSHIMATSU et al. as modified by ASAI and SAEGUSA discloses the limitations of claim 6. However, YOSHIMATSU et al. does not disclose wherein the lead frame extends linearly from the first bonding part to the second bonding part in the plan view.
In the similar field of endeavor of semiconductor devices, ASAI Figs. 1-4B discloses wherein the lead frame extends linearly from the first bonding part to the second bonding part in the plan view (“created from a rectangular plate” ¶ [0035])
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify bonding structure of YOSHIMATSU et al. with the bonding structure of ASAI in order to reduce the stress applied to the upper surface of the power semiconductor chip (ASAI, ¶ [0037]).
Regarding Claim 11, YOSHIMATSU et al. as modified by ASAI and SAEGUSA discloses the limitations of claim 1. However, YOSHIMATSU et al. does not disclose wherein the lead frame further includes a first elastic portion between the electrode bonding part and the first bonding part and a second elastic portion between the electrode bonding part and the second bonding part.
In the similar field of endeavor of semiconductor devices, ASAI Figs. 1-4B discloses wherein the lead frame further includes a first elastic portion between the electrode bonding part and the first bonding part and a second elastic portion between the electrode bonding part and the second bonding part (“as depicted in FIG. 4B, the end portions of the bonding portions 6a, 6b may be deformed downwardly, enabling a concentration of stress applied to the end portions of the bonding portions 6a, 6b consequent to thermal deformation to be mitigated.” ¶ [0038])
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify bonding structure of YOSHIMATSU et al. with the bonding structure of ASAI in order to reduce necessary stress to achieve reliability of the power semiconductor module (ASAI, ¶ [0039]).
Claims 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over YOSHIMATSU; Naoki (US 20160099224 A1) “YOSHIMATSU et al.” in view of ASAI; Tatsuhiko (US 20180076149 A1) “ASAI” further in view of SAEGUSA; Naoki (US 11145584 B2) “SAEGUSA” further in view of ARATA; Kazuki (US 20230378033 A1) “ARATA et al”.
Regarding Claim 9, YOSHIMATSU et al. as modified by ASAI and SAEGUSA discloses the limitations of claim 6. YOSHIMATSU et al. further discloses, the wiring terminal 8 is formed so as to partially protrude (at two sections) and the wiring terminal 8 is bonded to the circuit pattern 4 at the two positions.
However, YOSHIMATSU et al. does not disclose wherein the second bonding part includes a plurality of second bonding subparts, and
the lead frame extends linearly from the electrode bonding part to each of the plurality of second bonding subparts in the plan view.
In the similar field of endeavor semiconductor devices ARATA et al. Figs. 1-2 and 11 discloses wherein the second bonding part includes a plurality of second bonding subparts (“The fourth dummy terminal 322 extends from the second conductor 32 through between the second conductive plate 22 and the third conductive plate 23 toward the one side in the second direction, and is connected to the second AC terminal 622 connected to the second conductive plate 22.” ¶ [0043]; “The second conductor 32 is connected to the frame 1a at three locations of the first AC terminal 621, the first dummy terminal 321, and the second AC terminal 622 via the fourth dummy terminal 322” ¶ [0046]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify bonding structure of YOSHIMATSU et al. with the bonding structure of ARATA et al. in order to prevent droop toward the switching element side by self-weights during manufacturing in a state in which they are connected to the frame. Thus, position displacement of the second conductor, the third conductor, and the fourth conductor, which are terminals connected to the switching elements can be suppressed. (ARATA, ¶ [0015]).
However, ARATA et al. does not disclose the lead frame extends linearly from the electrode bonding part to each of the plurality of second bonding subparts in the plan view.
In the similar field of endeavor of semiconductor devices, ASAI Figs. 2A-2B discloses the lead frame extends linearly from the electrode bonding part to second bonding part in the plan view (“both ends of the interconnect portion 6c are shortened by the same amount, having a shape connecting a central portion of the side p1 of the bonding portion 6a and a central portion of the side p2 of the bonding portion 6b” ¶ [0035]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify bonding structure of YOSHIMATSU et al. with the bonding structure of ARATA et al. and using the teaching of ASAI in order to reduce the stress applied to the upper surface of the power semiconductor chip (ASAI, ¶ [0037]).
Regarding Claim 10, YOSHIMATSU et al. as modified by ASAI and SAEGUSA discloses the limitations of claim 9. YOSHIMATSU et al. does not disclose, wherein the electrode bonding part is located at a position corresponding to a center of gravity of the lead frame in the plan view.
In the similar field of endeavor or semiconductor device SAEGUSA Figs. 1-5 and 15-19 discloses, wherein the electrode bonding part is located at a position corresponding to a center of gravity of the lead frame in the plan view (“positioned at a center among the bonding portions” Column 13, Line 59).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify bonding structure of YOSHIMATSU et al. with the bonding structure of ASAI and further using the teaching of SAEGUSA in order to improve yield and non-defective rate, enhance reliability, and extend life expectancy of product (Column 15, Lines 59-61).
Claims 12 is rejected under 35 U.S.C. 103 as being unpatentable over YOSHIMATSU; Naoki (US 20160099224 A1) “YOSHIMATSU et al.” in view of ASAI; Tatsuhiko (US 20180076149 A1) “ASAI” further in view of SAEGUSA; Naoki (US 11145584 B2) “SAEGUSA” further in view of Asai; Tatsuhiko (US 10373919 B2) “Asai-1”.
Regarding Claim 12, YOSHIMATSU et al. as modified by ASAI and SAEGUSA discloses the limitations of claim 11. However, YOSHIMATSU et al. does not disclose wherein: the lead frame further includes
a first linking part of a plate shape, connecting between the electrode bonding part and the first bonding part, and
a second linking part of the plate shape, connecting between the electrode bonding part and the second bonding part,
the first and second elastic portions are respectively provided in the first linking part and the second linking part,
in the first elastic portion, the first linking part has a first bent portion that is of an entire width of the first linking part, and is bent in a thickness direction of the first linking part, and
in the second elastic portion, the second linking part has a second bent portion that is of an entire width of the second linking part, and is bent in a thickness direction of the second linking part.
In the similar field of endeavor of semiconductor devices, Asai-1 Figs. 1-4B discloses the lead frame further includes a first linking part of a plate shape, connecting between the electrode bonding part and the first bonding part, and a second linking part of the plate shape, connecting between the electrode bonding part and the second bonding part (“the interconnect portion being a bended rectangular plate, and having a first end extending from a side surface of the first plate, a second end extending from a side surface or a top surface of the second plate, and an n-shaped central portion that extends from, and connects, the first and second ends, wherein the first and second ends and the central portion of the interconnect portion are of a same width in a second direction perpendicular to the first direction” Claim 1), the first and second elastic portions are respectively provided in the first linking part and the second linking part, in the first elastic portion, the first linking part has a first bent portion that is of an entire width of the first linking part, and is bent in a thickness direction of the first linking part, and in the second elastic portion, the second linking part has a second bent portion that is of an entire width of the second linking part, and is bent in a thickness direction of the second linking part (“In the interconnect portion 6c, a portion orthogonal to the bonding portions 6a, 6b may be called a raised portion 6d.” ¶ [0034]; “In the interconnect portion 6c, a portion orthogonal to the bonding portions 6a, 6b may be called a raised portion 6d.” ¶ [0044]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify bonding structure of YOSHIMATSU et al. with the bonding structure of Asai-1 in order to reduce necessary stress to achieve reliability of the power semiconductor module (Asai-1, Column 6 Lines 5-6).
Conclusion
The prior art UMEDA; Soichiro (US 20210233885 A1) “UMEDA et al.” filing date 2019-04-10 made of record and not relied upon considered pertinent to applicant’s disclosure.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AKHEE SARKER-NAG whose telephone number is (703)756-4655. The examiner can normally be reached Monday - Friday 7:15 AM to 5:30 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, YARA J. GREEN can be reached at (571) 270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/AKHEE SARKER-NAG/Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893
Prosecution Insights