DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 2 and 9 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 12,107,037 in view of Jeng et al. (U.S. Patent No. 10,515,827). Claim 1 of U.S. Patent No. 12,107,037 does not disclose the first side of the first pattern base is coplanar with a first side of the first terminal. However, Jeng discloses a first side of the first pattern base is coplanar with a first side of a first terminal (Fig. 4). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified claim 1 in view of Jeng to configure the first side of the first pattern base to be coplanar with a first side of the first terminal in order to simplify the fabrication process.
18/900,411
U.S. Patent No. 12,107,037
2. A semiconductor device, comprising:
a substrate comprising a top side and a bottom side, a dielectric structure, and a conductive structure, wherein the conductive structure comprises a first terminal exposed from the dielectric structure;
an electronic component over the top side of the substrate; and
an encapsulant over the top side of the substrate and covering a lateral side of the electronic component;
wherein the dielectric structure comprises a first pattern base and first pattern wall that extends from a first side of the first pattern base;
wherein the first side of the first pattern base is coplanar with a first side of the first terminal; and
wherein the first pattern base extends laterally from the first pattern wall beyond a footprint of the first pattern wall.
9. A semiconductor device, comprising:
a substrate comprising a top side and a bottom side, a dielectric structure, and a conductive structure, wherein the conductive structure comprises a first terminal exposed from the dielectric structure;
an electronic component over the top side of the substrate; and
an encapsulant over the top side of the substrate and covering a lateral side of the electronic component;
wherein the dielectric structure comprises a first pattern base and first pattern wall that extends from a first side of the first pattern base; and
wherein the first side of the first pattern base is coplanar with a first side of the first terminal.
1. A semiconductor device, comprising:
a substrate comprising a top side and a bottom side, a dielectric structure, and a conductive structure, wherein the conductive structure comprises a first terminal exposed from the dielectric structure;
an electronic component over the top side of the substrate; and
an encapsulant over the top side of the substrate and covering a lateral side of the electronic component;
wherein the dielectric structure comprises a first pattern base and first pattern wall that extends from the first pattern base and is adjacent to the first terminal, and the first terminal is bounded by the first pattern wall;
wherein the first pattern wall is spaced apart from the first terminal; and
wherein the first pattern base extends laterally from the first pattern wall beyond a footprint of the first pattern wall.
1. A semiconductor device, comprising:
a substrate comprising a top side and a bottom side, a dielectric structure, and a conductive structure, wherein the conductive structure comprises a first terminal exposed from the dielectric structure;
an electronic component over the top side of the substrate; and
an encapsulant over the top side of the substrate and covering a lateral side of the electronic component;
wherein the dielectric structure comprises a first pattern base and first pattern wall that extends from the first pattern base and is adjacent to the first terminal, and the first terminal is bounded by the first pattern wall;
wherein the first pattern wall is spaced apart from the first terminal; and
wherein the first pattern base extends laterally from the first pattern wall beyond a footprint of the first pattern wall.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 2-21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jeng et al. (U.S. Patent No. 10,515,827).
Regarding to claim 2, Jeng teaches a semiconductor device (Fig. 4, please also see Fig. 1 for numerical labels), comprising:
a substrate comprising a top side and a bottom side (Fig. 4, Fig. 1A, element 120), a dielectric structure (Fig. 4, Fig. 1A, element 121/123/125/127), and a conductive structure (Fig. 4, Fig. 1A, element 122/124/126), wherein the conductive structure comprises a first terminal exposed from the dielectric structure (Fig. 4, Fig. 1A, element 122);
an electronic component over the top side of the substrate (Fig. 4, Fig. 1C, element 140); and
an encapsulant over the top side of the substrate and covering a lateral side of the electronic component (Fig. 4, Fig. 1F, element 210);
wherein the dielectric structure comprises a first pattern base and first pattern wall that extends from a first side of the first pattern base (Fig. 4, please also see the attached figure with annotations);
wherein the first side of the first pattern base is coplanar with a first side of the first terminal (Fig. 4, please also see the attached figure with annotations); and
wherein the first pattern base extends laterally from the first pattern wall beyond a footprint of the first pattern wall (Fig. 4, please also see the attached figure with annotations).
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Regarding to claim 3, Jeng teaches the first terminal is bounded by the first pattern wall (Fig. 4).
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Regarding to claim 4, Jeng teaches a second pattern wall extending from the first side of the first pattern base, wherein the first terminal is bounded by the first pattern wall and the second pattern wall (Fig. 4, please also see the attached figure with annotations).
Regarding to claim 5, Jeng teaches a second terminal exposed from the dielectric structure, wherein the first terminal and the second terminal are bounded by the first pattern wall (Fig. 4, please also see the attached figure with annotations).
Regarding to claim 6, Jeng teaches a second terminal exposed from the dielectric structure and a second pattern wall extending from the first side of the first pattern base, wherein the first terminal and the second terminal are bounded by the first pattern wall and the second pattern wall (Fig. 4, please also see the attached figure with annotations).
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Regarding to claim 7, Jeng teaches a second terminal exposed from the dielectric structure, wherein the first pattern wall is between the first terminal and the second terminal (Fig. 4, please also see the attached figure with annotations).
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Regarding to claim 8, Jeng teaches an exterior lateral side of the first pattern wall is coplanar with an exterior lateral side of the encapsulant (Fig. 4).
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Regarding to claim 9, Jeng teaches a semiconductor device, comprising:
a substrate comprising a top side and a bottom side (Fig. 4, Fig. 1A, element 120), a dielectric structure (Fig. 4, Fig. 1A, element 121/123/125/127), and a conductive structure (Fig. 4, Fig. 1A, element 122/124/126), wherein the conductive structure comprises a first terminal exposed from the dielectric structure (Fig. 4, Fig. 1A, element 122);
an electronic component over the top side of the substrate (Fig. 4, Fig. 1C, element 140); and
an encapsulant over the top side of the substrate and covering a lateral side of the electronic component (Fig. 4, Fig. 1F, element 210);
wherein the dielectric structure comprises a first pattern base and first pattern wall that extends from a first side of the first pattern base (Fig. 4, please also see the attached figure with annotations); and
wherein the first side of the first pattern base is coplanar with a first side of the first terminal (Fig. 4, please also see the attached figure with annotations).
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Regarding to claim 10, Jeng teaches the first terminal is bounded by the first pattern wall (Fig. 4, please also see the attached figure with annotations).
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Regarding to claim 11, Jeng teaches a second pattern wall extending from the first side of the first pattern base, wherein the first terminal is bounded by the first pattern wall and the second pattern wall (Fig. 4, please also see the attached figure with annotations).
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Regarding to claim 12, Jeng teaches a second terminal exposed from the dielectric structure, wherein the first terminal and the second terminal are bounded by the first pattern wall (Fig. 4, please also see the attached figure with annotations).
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Regarding to claim 13, Jeng teaches a second terminal exposed from the dielectric structure and a second pattern wall extending from the first side of the first pattern base, wherein the first terminal and the second terminal are bounded by the first pattern wall and the second pattern wall (Fig. 4, please also see the attached figure with annotations).
Regarding to claim 14, Jeng teaches a second terminal exposed from the dielectric structure, wherein the first pattern wall is between the first terminal and the second terminal (Fig. 4, please also see the attached figure with annotations).
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Regarding to claim 15, Jeng teaches an exterior lateral side of the first pattern wall is coplanar with an exterior lateral side of the encapsulant (Fig. 4).
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Regarding to claim 16, Jeng teaches a method to manufacture a semiconductor device, comprising:
providing a substrate comprising a top side and a bottom side (Fig. 4, Fig. 1A, element 120), a dielectric structure (Fig. 4, Fig. 1A, element 121/123/125/127), and a conductive structure (Fig. 4, Fig. 1A, element 122/124/126), wherein the conductive structure comprises a first terminal exposed from the dielectric structure (Fig. 4, Fig. 1A, element 122);
providing an electronic component over the top side of the substrate (Fig. 4, Fig. 1C, element 140); and
providing an encapsulant over the top side of the substrate and covering a lateral side of the electronic component (Fig. 4, Fig. 1F, element 210);
wherein the dielectric structure comprises a first pattern base and first pattern wall that extends from a first side of the first pattern base (Fig. 4, please also see the attached figure with annotations);
wherein the first side of the first pattern base is coplanar with a first side of the first terminal (Fig. 4, please also see the attached figure with annotations); and
wherein the first pattern base extends laterally from the first pattern wall beyond a footprint of the first pattern wall (Fig. 4, please also see the attached figure with annotations).
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Regarding to claim 17, Jeng teaches the first terminal is bounded by the first pattern wall (Fig. 4).
Regarding to claim 18, Jeng teaches a second pattern wall extending from the first side of the first pattern base, wherein the first terminal is bounded by the first pattern wall and the second pattern wall (Fig. 4, please also see the attached figure with annotations).
Regarding to claim 19, Jeng teaches a second terminal exposed from the dielectric structure, wherein the first terminal and the second terminal are bounded by the first pattern wall (Fig. 4, please also see the attached figure with annotations).
Regarding to claim 20, Jeng teaches a second terminal exposed from the dielectric structure and a second pattern wall extending from the first side of the first pattern base, wherein the first terminal and the second terminal are bounded by the first pattern wall and the second pattern wall (Fig. 4, please also see the attached figure with annotations).
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Regarding to claim 21, Jeng teaches a second terminal exposed from the dielectric structure, wherein the first pattern wall is between the first terminal and the second terminal (Fig. 4, please also see the attached figure with annotations).
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Pertinent Art
For the benefits of the Applicant, US-11387177-B2, US-20110186997-A1, US-8106495- B2, US-7288841-B2, US-8502370-B2, US-9859201-B2, US-10217702-B2, US-8941230-B2, US-7173828-B2, and US-7485951-B2, are cited on the record as being pertinent to significant disclosure through some but not all claimed features of the defined invention. The references fail to disclose “the first side of the first pattern base is coplanar with a first side of the first terminal and the first pattern base extends laterally from the first pattern wall beyond a footprint of the first pattern wall.”
Conclusion
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/VU A VU/Primary Examiner, Art Unit 2897
