DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 6-11, 14-17 and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen et al. 20230010353 herein Chen.
Per claim 1, Chen discloses: In an electronic system including an interconnect for a plurality of cores, a directory-based cache coherence method comprising: (fig. 1, ¶0039-40; FIG. 1. FIG. 1 indicates a configuration example of a 6-core processor (CPU chip) CPU0. Each of the core groups CMG0 and CMG1 includes a plurality of (3 in the example in FIG. 1) cores CORE, a level 1 cache L1$ belonging to each of the plurality of cores… The LL cache LL$ includes an LL tag LLTAG in which state information of the cache e.g., MESI is stored, an LL data RAM LLRAM in which data is stored, and an LL cache control unit (not illustrated).;the examiner notes that a directory cache coherence is merely storing the MESI tag in the cache) receiving a request transaction including a plurality of writes; (fig. 6, ¶0055; As the first operation steps, when an IO store request with order guarantee is received (S1), the store command queue STCQ enters the received IO store request to an entry queue register ENTRY_QUE_REG in order of reception (S2).) sending a request for ownership of a window of cache lines corresponding to the plurality of writes; (¶0055; When a notification, that data ownership of the address of the IO store request is acquired, is received from the LL cache control unit (S3), the store command queue changes a data ownership acquisition flag MIPTKN of the target IO store request to valid “1” (S4). In a case where there is an entry which is a top-of-queue (TOQ), that is the oldest in the entry queue register, and of which data ownership acquisition flag is valid (S5)) generating a cache maintenance operation that specifies a target address for each cache line, wherein the cache maintenance operation is entered in a directory transaction table when the directory transaction table does not have any outstanding transaction to the cache line; (fig. 8, ¶0084; Since both the LL tag LLTAG and the tag directory TAGD have no ownership (I: invalid), the home agent acquires the data ownership of the address A of the IO store request A. Then the home agent HA changes the tag directory TAGD to the ownership state (E: Exclusive) in the flow of READ_A, and replies with the data ownership acquisition notification MIPTKN_A to the LL cache control unit of BANK0 (SA5). The data ownership acquisition notification MIPTKN_A notifies that the processing of IO_FST or IO_PST, corresponding to the IO store request, is able to be started, and the processing will eventually complete; the examiner notes that the cache maintenance operation is merely the ownership request per the applicants specification ¶0032 and the negative limitation is interpreted as the cache line not having an owner) granting ownership window to the cache lines without regard for order; (¶0010; An IO store request that is requested from an IO device to a processor has either a strong ordering attribute which guarantees the order of store processing, or a relaxed ordering attribute which does not have to guarantee the order of store processing.; fig. 6, ¶0055; When a notification, that data ownership of the address of the IO store request is acquired, is received from the LL cache control unit (S3), the store command queue changes a data ownership acquisition flag MIPTKN of the target IO store request to valid “1” (S4). In a case where there is an entry which is a top-of-queue (TOQ), that is the oldest in the entry queue register, and of which data ownership acquisition flag is valid (S5) ; the examiner interprets the negative limitation as out of order) and committing a write that is oldest once ownership has been granted to its corresponding cache line (fig. 6; ¶0055; he store command queue sends a top-of-queue notification (TOQ notification, P_BK(0|1)_STCQ_TOQ_VAL) to the LL cache control unit, and deletes the entry of the top-of-queue (TOQ) from the queue (S6). At the same time, the store command queue sends to the router RT an IO store request entry release notification (P_IO_STCQ_RLS) addressed to the IO device).
Per claim 2, Chen discloses: wherein ownership is requested by a cache maintenance operation, and the write is a write-back (fig. 6 s1-s3; ¶0140; Responding to this entry, the LL-PIPE issues a write back request WRBK to HA to write the “data before storing” in the data RAM DATA-RAM back to the memory (S83), and writes the data stored in the store data queue STDQ to the data RAM DATA-RAM. Responding to the write back request WRBK, the home agent HA sets the tag directory TAGD to TAGD: I, and writes the “data before storing” back to the memory; the examiner notes that the cache maintenance operation is merely the ownership request per the applicants specification ¶0032).
Per claim 3, Chen discloses: wherein once the committed write has started, snoops to the corresponding cache line are blocked until the committed write has been completed (¶0110-0111; FIG. 13 indicates the dead lock state in Operation Example 5. As indicated in the entry queue register ENTRY_QUE_REG of the store command queue, for the IO store requests C and D in the entry, the data ownership has been already acquired (MIPTKN=1), hence the addresses C and D in the IO store request are currently locked…. In the above state, (1) addresses C and D are currently locked in the LL-PIPE, hence the snoop requests to acquire the data ownership at the addresses C and D are continuously aborted in the LL-PIPE.).
Per claim 6, Chen discloses: further comprising releasing ownership of the window of cache lines after write data becomes visible downstream (¶0090; Responding to the input of the MIPTKN notification B, the store command queue STCQ sets the data ownership acquisition flag MIPTKN of the entry B of the entry queue register ENTRY_QUE_REG to valid “1” (SB7). However, the top-of-queue TOQ is still the entry A, hence the entry B is not released first from the entry queue. Therefore, the entry B remains in the entry queue register until the entry A, of which IO store request was received first, is released.; the examiner interprets “visible downstream” as notification/indication of a write).
Per claim 7, Chen discloses: wherein the request transaction is received and the request for ownership is sent by an interface unit; and wherein ownership is granted and the oldest write is committed by a directory (fig. 6, ¶0055; When a notification, that data ownership of the address of the IO store request is acquired, is received from the LL cache control unit (S3), the store command queue changes a data ownership acquisition flag MIPTKN of the target IO store request to valid “1” (S4). In a case where there is an entry which is a top-of-queue (TOQ), that is the oldest in the entry queue register, and of which data ownership acquisition flag is valid (S5)).
Claims 8-11 and 14 are the system claims corresponding to the system claims 1-3 and 6 and are rejected under the same reasons set forth in connection with the rejection of claims 1-3 and 6. The rejection is silent to a plurality of initiators. However, Chen discloses a plurality of initiators in fig. 1 ¶0041 and ¶0042.
Claims 15-17 and 20 are the network on chip claims corresponding to the system claims 1-3 and 6 and are rejected under the same reasons set forth in connection with the rejection of claims 1-3 and 6. The rejection is silent to a plurality of initiators. However, Chen discloses a plurality of initiators in fig. 1 ¶0041 and ¶0042.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 4-5, 12-13 and 18-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. 20230010353 herein Chen in view of Hum et al. 20140181394 herein Hum.
Per claim 4, Chen does not specifically disclose: wherein when a snoop is received and when the cache line of a given write is waiting for ownership, the ownership of all cache lines of writes after the given write is revoked.
However, Hum discloses: wherein when a snoop is received and when the cache line of a given write is waiting for ownership, the ownership of all cache lines of writes after the given write is revoked (fig. 3B, claim 13; wherein responsive to the home agent receiving a new ownership request for the cache line from a second caching agent, the home agent is to send a snoop message to the remote caching agent to determine if the remote caching agent is in the process of writing to the cache line, and wherein the home agent is to revoke ownership of the cache line from the remote caching agent, remove the entry from the directory cache, and grant ownership of the cache line to the second caching agent if the remote caching agent is not writing to the cache line).
It would have been obvious to one having ordinary skill in the art at the effective filing date of the invention to combine the teachings of Chen and Hum to limit the amount of traffic to perform coherency. Hum reduces overhead (¶0016)
Per claim 5, Hum discloses: wherein ownership is once again requested for those cache lines that had their ownership revoked (fig. 3B, ¶0054; Accordingly, the method proceeds to block 365, and the home agent waits for the remote caching agent to complete writing to the cache line and for a writeback to complete. Alternatively, the second caching agent may have to issue a new ownership request for the cache line. If the remote caching agent is not in the process of writing to the cache line, the method continues to block 370).
Claims 12-13 are the system claims corresponding to the system claims 4-5 and are rejected under the same reasons set forth in connection with the rejection of claims 4-5. The rejection is silent to a plurality of initiators. However, Chen discloses a plurality of initiators in fig. 1 ¶0041 and ¶0042.
Claims 18-19 are the network on chip claims corresponding to the system claims 4-5 and are rejected under the same reasons set forth in connection with the rejection of claims4-5. The rejection is silent to a plurality of initiators. However, Chen discloses a plurality of initiators in fig. 1 ¶0041 and ¶0042.
Response to Arguments
Applicant's arguments filed 5/14/26 have been fully considered but they are not persuasive.
The applicant argues: Applicant respectfully asserts that the feature of "a cache maintenance operation that specifies a target address for each cache line in the window of cache lines and . . . is entered in a directory transaction table when the directory transaction table does not have any outstanding transaction to a cache line in the window of cache lines," as now set forth in independent claim 1 (similar a feature in independent claims 8 and 15) is not taught or suggest by any of the references of record, alone or in combination. Applicant respectfully submits that the rejection of independent claims 1, 8, and 15 are now moot in light of the foregoing amendments and the telephone interview conducted. Accordingly, Applicant respectfully submits that independent claims 1, 8, and 15 are now in condition for allowance. Applicants respectfully request withdrawal of the rejections of independent claims 1, 8, and 15 under 35 USC 102 and 35 USC 103, as set forth in the NFOA, and allowance of same.
Applicant's arguments fail to comply with 37 CFR 1.111(b) because they amount to a general allegation that the claims define a patentable invention without specifically pointing out how the language of the claims patentably distinguishes them from the references.
Assuming arguendo, the examiner respectfully disagrees and asserts that Chen discloses a cache maintenance operation (ownership request) that specifies a target address in the range of cache lines and the operation updates an entry in the directory transaction table which was not in use by any transaction. As cited supra, Chen in ¶0084 discloses a maintenance operation wherein the maintenance operation merely requests and obtains ownership of the address range of cache lines. Further, an update is made to the tag directory to establish ownership when it is determined that the address is invalid or has no ownership. Therefore, Chen discloses a cache maintenance operation that specifies a target address for each cache line in the window of cache lines and . . . is entered in a directory transaction table when the directory transaction table does not have any outstanding transaction to a cache line in the window of cache lines.
Remark
Examiner respectfully requests, in response to this Office action, support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line number(s) in the specification and/or drawing figure(s). This will assist Examiner in prosecuting the application.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BABOUCARR FAAL whose telephone number is (571)270-5073. The examiner can normally be reached M-F 8:30-5:30 EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Tim VO can be reached at 5712723642. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
BABOUCARR . FAAL
Primary Examiner
Art Unit 2138
/BABOUCARR FAAL/Primary Examiner, Art Unit 2138
Prosecution Insights