Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
In response to the Communications dated September 30, 2024, claims 1-20 are active in
this application.
Specification
If there are cross-reference to related applications, please include the
respective patent numbers, if known.
Foreign Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)
(d), which papers have been placed of record in the file.
Information Disclosure Statement
The information disclosure statements filed September 30, 2024 have been considered.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 1-10 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-10 of U.S. Patent No. 12154616 [‘616]. Although the claims at issue are not identical, they are not patentably distinct from each other because of the following reason.
The subject matter claimed in the instant application is fully disclosed in the patent and is covered by the patent since the patent and the application are claiming common subject matter, as follows.
Present Application
Patent ‘616
1. A memory device comprising: a first input data receiver configured to receive a first data signal through a first data line and to determine a logic level of the first data signal; a second input data receiver configured to receive a second data signal through a second data line and to determine a logic level of the second data signal; a first mode register configured to store a first code and a second code, the first and second codes indicating a first reference voltage level and a second reference voltage level, respectively; and a second mode register configured to store a third code and a fourth code, the third and fourth codes indicating a first DFE value and a second DFE value, respectively, wherein the first input data receiver determines the logic level of the first data signal based on the first code and the third code, and the second input data receiver determines the logic level of the second data signal based on the second code and the fourth code.
1. A memory device comprising: a first input data receiver configured to receive a first data signal through a first data line and to determine logic level of the first data signal; a second input data receiver configured to receive a second data signal through a second data line and to determine a logic level of the second data signal; a first mode register configured to store a first code and a second code, the first and second codes indicating a first reference voltage level and a second reference voltage level, respectively; and a second mode register configured to store a third code and a fourth code, the third and fourth codes indicating a first DFE value and a second DFE value, respectively, wherein the first input data receiver determines the logic level of the first data signal based on the first code and the third code, and the second input data receiver determines the logic level of the second data signal based on the third code and the fourth code.
2. The memory device of claim 1, wherein the first and second reference voltage levels are different from each other and/or the first and second DFE values are different from each other.
2. The memory device of claim 1, wherein the first and second reference voltage levels are different from each other and/or the first and second DFE values are different from each other.
3. The memory device of claim 1, wherein the first and second reference voltage levels and the first and second DFE values are programmed during write training operation.
3. The memory device of claim 1, wherein the first and second reference voltage levels and the first and second DFE values are programmed during write training operation.
4. The memory device of claim 1, wherein the first input data receiver determines the logic level of the first data signal by comparing the first input data signal with a first internal reference voltage which is a sum of the first reference voltage level and the first DFE value, and the second input data receiver determines the logic level of the second data signal by comparing the second input data signal with a second internal reference voltage which is a sum of the second reference voltage level and the second DFE value.
4. The memory device of claim 1, wherein the first input data receiver determines the logic level of the first data signal by comparing the first input data signal with a first internal reference voltage which is a sum of the first reference voltage level and the first DFE value, and the second input data receiver determines the logic level of the second data signal by comparing the second input data signal with a second internal reference voltage which is a sum of the second reference voltage level and the second DFE value.
5. The memory device of claim 4, wherein the first input data receiver comprises a first sampler configured to sample the first input data and to compare with an internal first reference voltage and the second input data receiver comprises a second sampler configured to sample the second input data and to compare with an internal second reference voltage.
5. The memory device of claim 4, wherein the first input data receiver comprises a first sampler configured to sample the first input data and to compare with an internal first reference voltage and the second input data receiver comprises a second sampler configured to sample the second input data and to compare with an internal second reference voltage.
6. The memory device of claim 5, wherein the first and second DFE values are generated based on a first previous bit value of the first input data and a second previous bit value of the second input data respectively.
6. The memory device of claim 5, wherein the first and second DFE values are generated based on a first previous bit value of the first input data and a second previous bit value of the second input data respectively.
7. The memory device of claim 6, wherein the first input data receiver further includes a first adder circuit configured to add the first code and the third code to generate the internal first reference voltage, and the second input receiver further includes a second adder circuit configured to add the second code and the fourth code to generate the internal second reference voltage.
7. The memory device of claim 6, wherein the first input data receiver further includes a first adder circuit configured to add the first code and the second code to generate the internal first reference voltage, and the second input receiver further includes a second adder circuit configured to add the third code and the fourth code to generate the internal second reference voltage.
8. The memory device of claim 7, wherein the first input receiver further includes a first DFE generator configured to generate a first DFE positive voltage and a first DFE negative voltage based on the third code, and the second input receiver further includes a second DFE generator configured to generate a second DFE positive voltage and a second DFE negative voltage based on the fourth code.
8. The memory device of claim 7, wherein the first input receiver further includes a first DFE generator configured to generate a first DFE positive voltage and a first DFE negative voltage based on the second code, and the second input receiver further includes a second DFE generator configured to generate a second DFE positive voltage and a second DFE negative voltage based on the fourth code.
9. The memory device of claim 8, wherein the first input data receiver further includes a first sub-sampler configured to determine a first current bit value of the first input data using the first reference voltage and one of the first positive DFE voltage and the first negative DFE voltage, and the second input data receiver further includes a second sub-sampler configured to determine a second current bit value of the second input data using the second reference voltage and one of the second positive DFE voltage and the second negative DFE voltage.
9. The memory device of claim 8, wherein the first input data receiver further includes a first sub-sampler configured to determine a first current bit value of the first input data using the first reference voltage and one of the first positive DFE voltage and the first negative DFE voltage, and the second input data receiver further includes a second sub-sampler configured to determine a second current bit value of the second input data using the second reference voltage and one of the second positive DFE voltage and the second negative DFE voltage.
10. The memory device of claim 1, wherein the memory device is a graphic double data rate (GDDR) SDRAM.
10. The memory device of claim 1, wherein the memory device is a graphic double data rate (GDDR) SDRAM.
As can be seen from the above table, similar to claim 1 of the present application claim 1 of patent ‘616 recites a system, with the exact same structure, having all four codes (code 1, code 2, code 3 and code 4, and that, in both, the first receiver operates identically. Unlike the application, the coding system of the patent switches to the input of the third code, instead of the second code, as recited in the application. However, the change in input codes is a mere difference in language or slight modification that does not add any patentable feature. Therefore, the patent protections have been granted to the earlier filed patent application.
For similar reasons, claims 2-10 are rejected over claims 1-10 of patent ‘616.
Claims 11-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 11-20 of U.S. Patent No. 12154616 [‘616]. Although the claims at issue are not identical, they are not patentably distinct from each other because of the following reason.
The subject matter claimed in the instant application is fully disclosed in the patent and is covered by the patent since the patent and the application are claiming common subject matter, as follows.
Present Application
Patent ‘616
11. A memory device comprising: a plurality of input data receivers, each configured to receive a data signal and to determine a logic level of the data signal; a first mode register configured to store a plurality of first codes, each indicating a reference voltage and being inputted to a corresponding one of the plurality of input data receivers; and a second mode register configured to store a plurality of second codes, each indicating a DFE value and being inputted to corresponding one of the plurality of input data receivers, wherein each of the plurality of input data receivers determines the logic level of the data signal based on one of the first codes and one of the second codes.
11. A memory device comprising: a plurality of input data receivers, each of the plurality of input data receivers configured to receive a data signal and to determine logic level of the data signal; a first mode register configured to store a plurality of first codes, each of the plurality of first codes indicating a reference voltage and being inputted to a corresponding input data receiver; and a second mode register configured to store a plurality of second codes, each of the second codes indicating a DFE value and being inputted to corresponding input data receiver, wherein each of the plurality of input data receivers determines the logic level of the data signal based on the first code and the second code inputted to the corresponding input data receiver.
12. The memory device of claim 11, wherein the plurality of the first codes are different from each other and/or the plurality of second codes are different from each other.
12. The memory device of claim 11, wherein the plurality of the first codes are different from each other and/or the plurality of second codes are different from each other.
13. The memory device of claim 11, wherein the first and second codes are programmed during a write training operation.
13. The memory device of claim 11, wherein the first and second codes are programmed during write training operation.
14. The memory device of claim 11, wherein each of the plurality of input data receivers determines the logic level of the data signal by comparing the input data signal with an internal reference voltage which is a sum of the corresponding first code and the corresponding second code.
14. The memory device of claim 11, wherein each of the plurality of input data receivers determines the logic level of the data signal by comparing the input data signal with an internal reference voltage which is a sum of the corresponding first code and the corresponding second code.
15. The memory device of claim 14, wherein each of the plurality of input data receivers comprises a sampler configured to sample the input data signal and to compare the sampled input data signal with the internal reference voltage.
15. The memory device of claim 14, wherein each of the plurality of input data receivers comprises a sampler configured to sample the input data signal and to compare the sampled input data signal with the internal reference voltage.
16. The memory device of claim 15, wherein the DFE values are generated based on a first previous bit value of the input data signal.
16. The memory device of claim 15, wherein the DFE values are generated based on a first previous bit value of the input data signal.
17. The memory device of claim 16, wherein each of the plurality of input data receivers further includes an adder circuit configured to add the first code and the second code to generate the internal reference voltage.
17. The memory device of claim 16, wherein each of the plurality of input data receivers further includes an adder circuit configured to add the first code and the second code to generate the internal reference voltage.
18. The memory device of claim 17, wherein each of the plurality of input receivers further includes a DFE generator configured to generate a DFE positive voltage and a DFE negative voltage based on the second code.
18. The memory device of claim 17, wherein each of the plurality of input receivers further includes a DFE generator configured to generate a DFE positive voltage and a DFE negative voltage based on the second code.
19. The memory device of claim 18, wherein each of the plurality of input data receivers further includes a sub-sampler configured to determine a first current bit value of the input data signal using the reference voltage and one of the positive DFE voltage and the negative DFE voltage.
19. The memory device of claim 18, wherein each of the plurality of input data receivers further includes a sub-sampler configured to determine a first current bit value of the input data signal using the reference voltage and one of the positive DFE voltage and the negative DFE voltage.
20. The memory device of claim 19, wherein the memory device is a graphic double data rate (GDDR) SDRAM.
20. The memory device of claim 19, wherein the memory device is a graphic double data rate (GDDR) SDRAM.
As can be seen from the above table, similar to claim 11 of the present application claim 11 of patent ‘616 recites a memory device with: a plurality of input data receivers; a first mode register storing codes for reference voltages; and, a second mode register storing codes for DFE (Decision Feedback Equalization) values. Unlike the application, the coding system of the patent recites: each of the plurality... is inputted to a corresponding input data receiver; and is based on the first code and the second code... instead of each... being inputted to a corresponding one of the plurality... receivers; and based on one of the first codes and one of the second codes, as in the application. However, the changes intended to clarify the language (e.g., changing "corresponding input data receiver" to "corresponding one of the plurality..."), which does not create a new invention. Therefore, the patent protections have been granted to the earlier filed patent application.
For similar reasons, claims 12-20 are rejected over claims 11-20 of patent ‘616.
Conclusion
For applicant’s benefit portions of the cited reference(s) have been cited to aid in
the review of the rejection(s). While every attempt has been made to be thorough and consistent within the rejection it is noted that the PRIOR ART MUST BE CONSIDERED IN ITS ENTIRETY, INCLUDING DISCLOSURES THAT TEACH AWAY FROM THE CLAIMS. See MPEP 2141.02 VI.
When responding to the Office action, Applicants are advised to provide
the Examiner with line and page numbers of the application and/or references cited to assist the Examiner in the prosecution of this case.
Any inquiry concerning this communication or earlier communications
from the Examiner should be directed to Michael T. Tran whose telephone number is (571) 272-1795. Interview agendas may be emailed to Michael.tran@uspto.gov. The Examiner can normally be reached on Monday-Thursday from 6:00AM-4:30 P.M.
Any inquiry of a general nature or relating to the status of this application.
should be directed to the Group receptionist whose telephone number is (571) 272-1650.
/MICHAEL T TRAN/Primary Examiner, Art Unit 2827 March 17, 2026