Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 9/30/2024 was filed before the mailing date of the Non-final rejection on 9/23/2026. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The formal drawings filed on 9/30/2024 have been approved by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-9 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 12,136,588. Although the claims at issue are not identical, they are not patentably distinct from each other because both the application and the patent recite leads and a die attach pad (DAP). At least one semiconductor die having a top side including circuitry electrically connected to bond pads and a bottom side that is attached to a bottom side portion of the DAP. A mold compound encapsulating the semiconductor die; a heat slug having a top side and a bottom side completely positioned within a cavity defined by sidewalls of the mold compound. The heat slug having an area greater than an area of the DAP and attached by its bottom side with a thermally conductive adhesive material to a top side portion of the DAP. The leads electrically coupled to the bond pads. Exposed from the mold compound are bottom side surfaces of the leads and the top side of the heat slug.
Claims 10-24 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 12 of U.S. Patent No. 12,136,588. Although the claims at issue are not identical, they are not patentably distinct from each other because both the application and the patent recite molding around a partially completed semiconductor package to form a mold compound. The partially completed semiconductor package comprising: leads and a die attach pad (DAP) having a top side and a bottom side opposite the top. At least one semiconductor die having a top side including circuitry electrically connected to bond pads and a bottom side that is attached to the bottom side of the DAP. The leads electrically coupled to the bond pads. The mold compound provides sidewalls defining an open mold cavity that exposes a topside of the DAP. Attaching a bottom side of a heat slug having an area greater than the DAP to the top side of the DAP. The heat slug fitting completely within the open mold cavity.
Claim 25 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 25 of U.S. Patent No. 12,136,588. Although the claims at issue are not identical, they are not patentably distinct from each other because both the application and the patent recite leads and a die attach pad (DAP). At least one semiconductor die having a top side including circuitry electrically connected to bond pads and a bottom side that is attached to a bottom side portion of the DAP. A mold compound encapsulating the semiconductor die. A heat slug having a top side and a bottom side positioned within a cavity having an area greater than an area of the DAP. The cavity defined by sidewalls of the mold compound. The heat slug attached by its bottom side with a thermally conductive adhesive material to a top side portion of the DAP. The leads electrically coupled to the bond pads, wherein exposed from the mold compound are bottom side surfaces of the leads and the top side of the heat slug.
Claim 26 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 26 of U.S. Patent No. 12,136,588. Although the claims at issue are not identical, they are not patentably distinct from each other because both the application and the patent recite molding around a partially completed semiconductor package. The partially completed semiconductor package comprising leads and a die attach pad (DAP) having a top side and a bottom side opposite the top side. At least one semiconductor die having a top side including circuitry electrically connected to bond pads and a bottom side that is attached to the bottom side of the DAP. The leads electrically coupled to the bond pads. The mold compound provides sidewalls defines an open mold cavity having an area greater than the DAP that exposes a top side of the DAP. Attaching a bottom side of a heat slug to the top side of the DAP.
The prior art made of record and not relied upon is cited primarily to show the
product of the instant invention.
Conclusion
9. Any inquiry concerning the communication or earlier communications from the
examiner should be directed to Alonzo Chambliss whose telephone number is (571)
272-1927.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's
supervisor, Jacob Y. Choi can be reached on (469) 295-9060. The fax phone number
for the organization where this application or proceeding is assigned is (571) 273-8300.
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AC/September 23, 2026 /Alonzo Chambliss/
Primary Examiner, Art Unit 2897
Prosecution Insights