DETAILED ACTION
This action is responsive to the response filed 30 Sep 2024. Claims 1-20 are pending. Claims 1, 9 and 16 are independent.
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Allowable Subject Matter
Claim(s) 4-8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
AND
Claims 9-20 are allowed.
Claim Rejections – 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless —
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 1 – 3 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sethuraman, et al, U.S. Patent Application Publication 2022/0300197 (“Sethuraman”).
Regarding claim 1, Sethuraman teaches:
A device, comprising: a receiver configured to receive a signal and generate an output for the signal; and (Sethuraman, fig 1, “[0024] Memory controller 120 includes I/O interface logic 122 to couple to a memory bus, such as a memory channel as referred to above. I/O interface logic 122 (as well as I/O interface logic 142 of memory device 140) can include pins, pads, connectors, signal lines, traces, or wires, or other hardware to connect the devices, or a combination of these.”; a memory device with a host controller 120, interface circuits that perform Input/Output and generate signals between the controller 120 and memory device 140).
self-adaptation circuits configured to receive the signal and obtain an adaptive value for a parameter based on the signal and the output for the signal. (Sethuraman, fig 1, “[0015] The backside CS and CA signal lines are the CS and CA signal lines going from the RCD to the DRAM. The backside CS and CA are referred to herein as QCS and QCA, respectively. [0040] In one such example, the RCD 121 includes one or both of backside CS training logic 128 and backside CA training logic 129. … [0041] Thus, in one example, instead of the host controlling the backside CS and CA training, the RCD 121 is responsible for triggering the memory device’s entry into a training mode, generating patterns, sweeping one or more parameters for the signal lines, receiving training feedback from the memory devices, and adjusting the parameters based on the training feedback.”; a training module RDC 121 that receives signals from the backside CS/ CA circuits; enters a training mode for the memory devices; and adjusts the parameters to operate the memory devices based on the training).
Regarding claim 2, Sethuraman teaches The device of claim 1, wherein the receiver comprises a command/address receiver. (Sethuraman, fig 1, “[0015] The backside CS and CA signal lines are the CS and CA signal lines going from the RCD to the DRAM. The backside CS and CA are referred to herein as QCS and QCA, respectively.”; a training module RDC 121 that receives signals from the backside CS/ CA circuits; enters a training mode for the CS and/or CA modes of operating the memory devices; and adjusts the CS/ CA parameters to operate the memory devices based on the training).
Regarding claim 3, Sethuraman teaches The device of claim 1, wherein a selection signal is used to enable the self-adaption circuits to obtain the adaptive value for the parameter for a memory chip of a plurality memory chips of the device. (Sethuraman, fig 2, 3, 5, “[0043] FIG. 2 is a block diagram of a system 200 in which autonomous RCD-controlled backside CS and CA training can be implemented. The system 200 includes multiple dual inline memory modules (DIMMs) 202-1-202-N coupled with a host memory controller 120. [0044] Each of the DIMMs 202-1-202-N also includes an RCD 121. [0060] FIG. 5 is a flow diagram of an example of a method 500 of autonomously training backside signal lines by an RCD. In one example, the one or more signal lines to train include one or more chip select (CS) signal lines or one or more command/address (CA) signal lines. [0065] Referring again to FIG. 5, the RCD iteratively adjusts (i.e., sweeps) a timing parameter for the signal lines being trained, at block 506. A timing parameter can include a delay in the signal.”; a device with multiple RCD 121 modules to train multiple DIMMs; that each set of DIMMs has a dedicated RCD 121; that the RDC is selected via signal lines, and then proceeds to train one or more CS or CA signal lines to obtain a timing parameter).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DONALD H.B. BRASWELL whose telephone number is (469)295-9119. The examiner can normally be reached on 7-5 Central Time (Dallas).
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/Donald HB Braswell/ Primary Examiner, Art Unit 2825
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