Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-21 are presented for examination.
Claim Objections
Claim 3 is objected to because of the following informality: The claim ends in a semicolon rather than a period. Appropriate correction is required.
Claim 10 is objected to because of the following informality: The claim is missing a period. Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-14, 18 are rejected under 35 U.S.C. 103 as being unpatentable over Burger et al., US Patent Application Publication 2017/0083314 (hereinafter Burger) in view of Takahashi et al., US Patent 5,724,548 (hereinafter Takahashi), further in view of Hooker et al., US Patent Application Publication 2011/0040955 (hereinafter Hooker).
Regarding claim 1, Burger teaches:
A processor architecture implementing a vector-dataflow execution model comprising: a scalar processor core (see e.g. fig. 1, para. [0073], one of the cores executing scalar operations); a vector processor core (see e.g. fig. 1, para. [0073], [0088], another core executing vector/SIMD operations); issue logic (see e.g. para. [0065-7]); an instruction window buffer (see e.g. para. [0051]); and a forwarding buffer (see e.g. para. [0083]).
Burger fails to explicitly teach the vector processor core with a single execution unit, and an xdata buffer, wherein the xdata buffer stores additional information from a scalar register file needed by instructions executed by the vector processor core.
Takahashi teaches a vector processor core with one execution unit (see e.g. fig. 8, one vector unit), and a buffer that stores additional information from a scalar register file needed by instructions executed by a vector processor core (see e.g. col. 7 lines 14-40).
Before the effective filing date of the claimed invention it would have been obvious to one of ordinary skill in the art to combine the teachings of Burger and Takahashi to include the vector processor core with a single execution unit, and an xdata buffer, wherein the xdata buffer stores additional information from a scalar register file needed by instructions executed by the vector processor core. This would have provided an advantage such as discussed by Takahashi “to improve the efficiency of the system in which a processor is connected to the cache memory to gain access to particular data such as vector data by reducing the penalty at the time of a cache miss in effecting non-sequential data access and, hence, by realizing a high-speed operation” (see col. 2 lines 62-67).
Burger in view of Takahashi fails to explicitly teach a register renaming table.
Hooker teaches a register renaming table (see e.g. para. [0027-8], [0035-6], register alias table).
Before the effective filing date of the claimed invention it would have been obvious to one of ordinary skill in the art to combine the teachings of Burger, Takahashi, and Hooker to include a register renaming table. This would have provided advantages such as discussed by Hooker to more quickly and efficiently forward data between instructions (see e.g. para. [0089-90]).
Regarding claim 2, Burger in view of Takahashi and Hooker teaches or suggests:
The architecture of claim 1 wherein the issue logic identifies, prepares and issues for execution a window of dependent instructions over a vector of inputs (see e.g. Burger para. [0030-1], [0047]), implements forwarding by renaming register operands of the instructions to refer to a free location in the forwarding buffer instead of to a vector register file and records the renaming in the register renaming table (see e.g. Hooker para. [0035-40]).
Regarding claim 3, Burger in view of Takahashi and Hooker teaches or suggests:
The architecture of claim 2 wherein the instruction window buffer stores the window of instructions issued by the issue logic and determines the next operation to be executed by the vector processor (see e.g. Burger para. [0030-1], [0047], [0051]);
Regarding claim 4, Burger in view of Takahashi and Hooker teaches or suggests:
The architecture of claim 3 wherein the forwarding buffer stores intermediate values forwarded by the execution unit and forwards the intermediate values to dependent instructions in the instruction window buffer (see e.g. Burger para. [0083], Hooker para. [0035-40]).
Regarding claim 5, Burger in view of Takahashi and Hooker teaches or suggests:
The architecture of claim 1 further comprising: instruction buffer control logic; wherein the instruction buffer control logic determines an order of execution for the instructions in the instruction buffer and executes an operation represented by each instruction in the instruction buffer (see e.g. Hooker para. [0035-40]).
Regarding claim 6, Burger in view of Takahashi and Hooker teaches or suggests:
The architecture of claim 5 wherein: the xdata buffer contains information from a scalar register file necessary for performing vector loads and stores; and the instruction buffer control logic contains indices into the xdata buffer as needed when information from the scalar register file is needed to fetch or store operands (see e.g. Takahashi col. 7 lines 14-40).
Regarding claim 7, Burger in view of Takahashi and Hooker teaches or suggests:
The architecture of claim 1 wherein execution of the instructions proceeds across each element of a vector for a single vector instruction before executing the next vector instruction in the instruction buffer (see e.g. Burger para. [0031], [0073], [0088]).
Regarding claim 8, Burger in view of Takahashi and Hooker teaches or suggests:
The architecture of claim 2 further comprising: a renaming table; wherein the instruction buffer control logic fetches or stores renamed operands from the forwarding buffer; and wherein the renaming table stores operands that have been renamed (see e.g. Hooker para. [0027-8], [0035-40]).
Regarding claim 9, Burger in view of Takahashi and Hooker teaches or suggests:
The architecture of claim 8 wherein the renaming table is a fixed size, directly-indexable table having one entry for each renamed operand (see e.g. Hooker para. [0027-8], [0035-40]).
Regarding claim 10, Burger in view of Takahashi and Hooker teaches or suggests:
The architecture of claim 2 further comprising: wherein the additional information stored in the xdata buffer includes information from a scalar register file necessary for performing vector loads and stores (see e.g. Takahashi col. 7 lines 14-40)
Regarding claim 11, Burger in view of Takahashi and Hooker teaches or suggests:
The architecture of claim 10 herein the instruction buffer control logic contains indices into the xdata buffer as needed when information from the scalar register file is needed to fetch or store operands (see e.g. Takahashi col. 7 lines 14-40).
Regarding claim 12, Burger in view of Takahashi and Hooker teaches or suggests:
The architecture of claim 4 wherein the forwarding buffer is a directly-indexed buffer storing intermediate values of operands for forwarding to dependent instructions (see e.g. Hooker para. [0035-40]).
Regarding claim 13, Burger in view of Takahashi and Hooker teaches or suggests:
The architecture of claim 1 wherein the issue logic identifies instructions within the window of continuous vector instructions that have a dataflow dependency therebetween by comparing names of input and output operands for each vector instruction to determine if output operands of any instruction match input operands of any other vector instruction (see e.g. Hooker para. [0044-6]).
Regarding claim 14, Burger in view of Takahashi and Hooker teaches or suggests:
The architecture of claim 1 wherein the architecture is used in low-power embedded systems (see e.g. Burger para. [0003], [0106]).
Claim 18 is rejected for reasons corresponding to those given above for claim 1.
Claims 15-17, 19-21 are rejected under 35 U.S.C. 103 as being unpatentable over Burger in view of Takahashi and Hooker, further in view of Chan et al., US Patent Application Publication 2022/0066783 (hereinafter Chan).
Regarding claim 15, Burger in view of Takahashi and Hooker teaches or suggests:
The architecture of claim 1.
Burger in view of Takahashi and Hooker fails to explicitly teach wherein the architecture uses a custom compiler having a modified ISA to supporting code scheduling and vector register kill annotations.
Chan teaches using a compiler having a modified ISA to support code scheduling and vector/scalar register kill annotations (see e.g. para. [0005], [0007], [0031-2]).
Before the effective filing date of the claimed invention it would have been obvious to one of ordinary skill in the art to combine the teachings of Burger, Takahashi, Hooker, and Chan such that the architecture uses a custom compiler having a modified ISA to supporting code scheduling and vector register kill annotations. This would have provided an advantage such as discussed by Chan to produce code “that is better structured to take advantage of the SIMT execution model than it would be in the absence of IR modification process” (see para. [0035]).
Regarding claim 16, Burger in view of Takahashi, Hooker, and Chan teaches or suggests:
The architecture of claim 15 wherein the kill annotations denote the last use of a vector register (see e.g. Chan para. [0005], [0007], [0031-2]).
Regarding claim 17, Burger in view of Takahashi, Hooker, and Chan teaches or suggests:
The architecture of claim 16 wherein the kill annotation comprises a kill bit for each register indicating that the register is dead at that instruction (see e.g. Chan para. [0005], [0007], [0031-2]).
Claims 19-21 are rejected for reasons corresponding to those given above for claim 1, 15-17.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-21 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-21 of U.S. Patent No. 12,164,926. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims in the instant application are similar to and substantially generic to the claims in the ‘926 patent. Therefore, a patent to the genus would improperly extend the right to exclude granted by a patent to the species or sub-genus should the genus issue as a patent after the species or sub-genus (see MPEP 804(II)(B)(1)).
Conclusion
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/JOHN M LINDLOF/Primary Examiner, Art Unit 2183
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