Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 22 - 41 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 2-21 of U.S. PGPUB No. 2024/0036975 A1. Although the claims at issue are not identical, they are not patentably distinct from each other because they are claiming similar subject matter as showed, for example, in the Claims Comparison Tables below. It would have been obvious to a person of ordinary skill in the art at the time the intention was made to modify, add or omit the additional elements of claims to arrive at the claims 22 - 41 of the instant application because the skilled person in the art would have realized that the remaining element would perform the same functions as before. “Omission of element and its function in combination is obvious expedient if the remaining elements perform same functions as before.” See In re Karlson (CCPA) 136 USPQ 184, decide Jan 16 , 1963, Appl. No. 6857, U. S. Court of Customs and Patent Appeals.
Instant Application 18/902,067 (06/24/2025)
Application 18/230,403 (PGPUB US 20240036975 A1)
22. (New) A memory device, comprising: a first plurality of memory elements to store data bits and a second plurality of memory elements to store check bits associated with the data bits; a first interface to communicate groups of data bits; a second interface to, when the memory device is in a first mode, as part of write operations, receive groups of check bits to be stored in the second plurality of memory elements, and to, as part of read operations, transmit groups of check bits received from the second plurality of memory elements; and the memory device to, when the memory device is in a second mode, generate and store, in the second plurality of memory elements, check bits in response to write operations, and to use check bits received from the second plurality of memory elements to detect, in response to read operations, errors in data bits and associated check bits that are manifested when the data bits and associated check bits are retrieved from the first plurality of memory elements and the second plurality of memory elements, respectively.
2. A memory module, comprising: a plurality of memory devices each comprising a first plurality of memory elements to store data bits and a second plurality of memory elements to store check bits associated with the data bits; an external interface to, when the memory module is in a first mode, as part of write operations, receive the check bits, and to, as part of read operations, transmit the check bits; error correction logic to, when the memory module is in the first mode, receive the check bits and correct errors in a group of data bits received via the external interface; and the memory module to, when the memory module is in a second mode, generate and store, in the second plurality of memory elements, the check bits in response to write operations, and to use the check bits to detect, in response to read operations, errors in the data bits and the check bits that are manifested when the data bits and the check bits are retrieved from the first plurality of memory elements and the second plurality of memory elements, respectively.
23. (New) The memory device of claim 22, wherein, when the memory device is in the first mode, check bits are communicated via a data mask signal port of the second interface as part of read operations.
3. The memory module of claim 2, wherein, when the memory module is in the first mode, the memory module is to provide the check bits to a plurality of data mask signal ports of the external interface as part of read operations.
24. (New) The memory device of claim 22, wherein, when the memory device is in the first mode, check bits are communicated via a data mask signal port of the second interface as part of write operations.
4. The memory module of claim 2, wherein, when the memory module is in the first mode, a plurality of the check bits are to be received via a plurality of data mask signal ports of the external interface as part of write operations.
25. (New) The memory device of claim 22, further comprising: check bit deserialization circuitry to, when the memory device is in the first mode, deserialize subsets of check bits as part of write operations.
6. The memory module of claim 2, wherein the plurality of memory devices each further comprise check bit deserialization circuitry to, when the memory module is in the first mode, deserialize respective subsets of the check bits as part of write operations.
26. (New) The memory device of claim 22, further comprising: check bit serialization circuitry to, when the memory device is in the first mode, serialize subsets of check bits as part of read operations.
7. The memory module of claim 5, wherein the plurality of memory devices each further comprise data bit serialization circuitry to serialize respective subsets of the data bits as part of read operations.
27. (New) The memory device of claim 25, further comprising: data bit deserialization circuitry to deserialize subsets of data bits as part of write operations.
8. The memory module of claim 6, wherein the plurality of memory devices each further comprise data bit deserialization circuitry to deserialize respective subsets of the data bits as part of write operations.
28. (New) The memory device of claim 26, further comprising: data bit serialization circuitry to serialize subsets of data bits as part of read operations.
5. The memory module of claim 2, wherein the plurality of memory devices each further comprise check bit serialization circuitry to, when the memory module is in the first mode, serialize respective subsets of the check bits as part of read operations.
29. (New) A controller, comprising: a first interface to communicate groups of data bits with a memory device having a first plurality of memory elements to store data bits and a second plurality of memory elements to store check bits associated with the data bits; a second interface to, when the controller is in a first mode, as part of write operations, transmit groups of check bits to be stored by the second plurality of memory elements, and to, as part of read operations, receive groups of check bits stored by the second plurality of memory elements; and the controller to, when the controller is in a second mode, not transmit check bits in response to write operations, the memory device is to generate and store, in the second plurality of memory elements, check bits in response to write operations, and the memory device is to use check bits received from the second plurality of memory elements to detect, in response to read operations, errors in data bits and associated check bits that are manifested when the data bits and associated check bits are retrieved from the first plurality of memory elements and the second plurality of memory elements, respectively.
9. A memory component, comprising: a command/address interface; a plurality of memory devices each comprising: a memory array; a first interface to, in response to a write command received via the command/address interface, respectively receive a first plurality of groups of data bits to be stored in the memory array; a second interface to respectively receive a first plurality of data mask signals each coincident with a respective one of the first plurality of groups of data bits, and to respectively receive a second plurality of data mask signals, each of the first plurality of data mask signals indicating that the respective one of the first plurality of groups of data bits received coincident with the corresponding one of the first plurality of data mask signals is not to be masked;
2. A memory module, comprising: a plurality of memory devices each comprising a first plurality of memory elements to store data bits and a second plurality of memory elements to store check bits associated with the data bits; an external interface to, when the memory module is in a first mode, as part of write operations, receive the check bits, and to, as part of read operations, transmit the check bits; error correction logic to, when the memory module is in the first mode, receive the check bits and correct errors in a group of data bits received via the external interface; and the memory module to, when the memory module is in a second mode, generate and store, in the second plurality of memory elements, the check bits in response to write operations, and to use the check bits to detect, in response to read operations, errors in the data bits and the check bits that are manifested when the data bits and the check bits are retrieved from the first plurality of memory elements and the second plurality of memory elements, respectively.
30. (New) The controller of claim 29, wherein, when the memory device is in the first mode, check bits are communicated via a data mask signal port of the second interface as part of read operations.
17. The memory module of claim 16, wherein, when the memory module is in the first mode, each of the plurality of memory devices are to provide respective check bits to a respective data mask signal port of the external interface as part of read operations.
31. (New) The memory device of claim 29, wherein, when the memory device is in the first mode, check bits are communicated via a data mask signal port of the second interface as part of write operations.
18. The memory module of claim 16, wherein, when the memory module is in the first mode, each of the plurality of memory devices are to receive, via a respective data mask signal port of the external interface and as part of write operations, respective check bits.
32. (New) The controller of claim 29, further comprising: check bit deserialization circuitry to, when the controller is in the first mode, deserialize subsets of check bits as part of read operations.
19. The memory module of claim 16, wherein the plurality of memory devices each further comprise check bit serialization circuitry to, when the memory module is in the first mode, serialize respective subsets of the check bits as part of read operations.
33. (New) The controller of claim 29, further comprising: check bit serialization circuitry to, when the controller is in the first mode, serialize subsets of check bits as part of write operations.
20. The memory module of claim 16, wherein the plurality of memory devices each further comprise check bit deserialization circuitry to, when the memory module is in the first mode, deserialize respective subsets of the check bits as part of write operations.
34. (New) The controller of claim 32, further comprising: data bit deserialization circuitry to deserialize subsets of data bits as part of read operations.
21. The memory module of claim 19, wherein the plurality of memory devices each further comprise data bit serialization circuitry to serialize respective subsets of the data bits as part of read operations.
35. (New) The controller of claim 33, further comprising: data bit serialization circuitry to serialize subsets of data bits as part of write operations.
20. The memory module of claim 16, wherein the plurality of memory devices each further comprise check bit deserialization circuitry to, when the memory module is in the first mode, deserialize respective subsets of the check bits as part of write operations.
36. (New) A memory module, comprising: a plurality of memory devices each comprising a first plurality of memory elements to store data bits and a second plurality of memory elements to store check bits associated with the data bits; a first external interface to communicate groups of data bits; a second external interface to, when the memory module is in a first mode, as part of write operations, receive groups of check bits for the plurality of memory devices to respectively be stored in the second plurality of memory elements of the plurality of memory devices, and to, as part of read operations, transmit groups of check bits respectively received from the second plurality of memory elements of the plurality of memory devices; and the plurality of memory devices to, when the memory module is in a second mode, generate and store, in respective ones of the second plurality of memory elements of the plurality of memory devices, check bits in response to write operations, and to respectively use check bits received from the second plurality of memory elements of the plurality of memory device to detect, in response to read operations, errors in data bits and associated check bits that are manifested when the data bits and associated check bits are respectively retrieved, by the plurality of memory devices, from respective ones of the first plurality of memory elements and the second plurality of memory elements of the plurality of memory devices.
16. A memory module, comprising: a command/address interface; a plurality of memory devices coupled to the command/address interface, each of the plurality of memory devices comprising: a first plurality of memory elements to store data bits and a second plurality of memory elements to store check bits associated with the data bits; an external interface to, when the memory module is in a first mode, as part of write operations, receive the check bits, and to, as part of read operations, transmit the check bits; error correction logic to, when the memory module is in the first mode, receive the check bits and correct errors in a group of data bits received via the external interface; and each of the plurality of memory devices to, when the memory module is in a second mode, generate and store, in the second plurality of memory elements, the check bits in response to write operations, and to use the check bits to detect, in response to read operations, errors in the data bits and the check bits that are manifested when the data bits and the check bits are retrieved from the first plurality of memory elements and the second plurality of memory elements, respectively.
37. (New) The memory module of claim 36, wherein, when the memory module is in the first mode, check bits are communicated via a data mask signal port of the second external interface as part of read operations.
17. The memory module of claim 16, wherein, when the memory module is in the first mode, each of the plurality of memory devices are to provide respective check bits to a respective data mask signal port of the external interface as part of read operations.
38. (New) The memory module of claim 36, wherein, when the memory module is in the first mode, check bits are communicated via a data mask signal port of the second external interface as part of write operations.
18. The memory module of claim 16, wherein, when the memory module is in the first mode, each of the plurality of memory devices are to receive, via a respective data mask signal port of the external interface and as part of write operations, respective check bits.
39. (New) The memory module of claim 36, wherein the plurality of memory devices each further comprise: check bit deserialization circuitry to, when the memory module is in the first mode, deserialize subsets of check bits as part of write operations.
20. The memory module of claim 16, wherein the plurality of memory devices each further comprise check bit deserialization circuitry to, when the memory module is in the first mode, deserialize respective subsets of the check bits as part of write operations.
40. (New) The memory module of claim 36, wherein the plurality of memory devices each further comprise: check bit serialization circuitry to, when the memory device is in the first mode, serialize subsets of check bits as part of read operations.
21. The memory module of claim 19, wherein the plurality of memory devices each further comprise data bit serialization circuitry to serialize respective subsets of the data bits as part of read operations.
41. (New) The memory module of claim 39, wherein the plurality of memory devices each further comprise: data bit deserialization circuitry to deserialize subsets of data bits as part of write operations.
20. The memory module of claim 16, wherein the plurality of memory devices each further comprise check bit deserialization circuitry to, when the memory module is in the first mode, deserialize respective subsets of the check bits as part of write operations.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 22 - 41 are rejected under 35 U.S.C. 103 as being unpatentable over Alzheimer (US 2022/0149866 A1) in view of Ayyapureddi (US 2024/0071550 A1).
In regards to claim 22, Alzheimer teaches:
A memory device, comprising: a first plurality of memory elements to store data bits and a second plurality of memory elements to store check bits associated with the data bits (0015, Memory cells can include any one of a number of different memory media types, including capacitive, phase change, magneto resistive, ferroelectric, or the like. In some embodiments, a portion of the memory array 150 may be configured to store ECC parity bits); a first interface to communicate groups of data bits; a second interface to, when the memory device is in a first mode, as part of write operations, receive groups of check bits to be stored in the second plurality of memory elements, and to, as part of read operations, transmit groups of check bits received from the second plurality of memory elements; and the memory device to, when the memory device is in a second mode, generate and store, in the second plurality of memory elements, check bits in response to write operations (0053 & 0012, In other embodiments, the host device 308 and the control circuitry 306 can communicate over a serial interface, such as a serial attached SCSI (SAS), a serial AT attachment (SATA) interface, a peripheral component interconnect express (PCIe), or other suitable interface (e.g., a parallel interface). The host device 308 can send various requests (in the form of, e.g., a packet or stream of packets) to the control circuitry 306. the host device may access one or more mode registers of the memory device to indicate (program) which bit or bits to poison while executing an access command (e.g., a write command, a read command)), and to use check bits received from the second plurality of memory elements to detect, in response to read operations, errors in data bits and associated check bits that are manifested when the data bits and associated check bits are retrieved from the first plurality of memory elements and the second plurality of memory elements, respectively. (0010, the memory device may attempt to detect and/or correct at least one error before transmitting the data (e.g., 128 bits of data) to the memory controller. In some embodiments, the memory device reads the code word from the address, and compute another set of ECC check bits (e.g., 8 bits, a second group of check bits) using the data read from the address. Subsequently, the memory device may compare the first group of ECC check bits read from the address).
In regards to claim 23, Alzheimer teaches the memory device of claim 22 and teaches:
wherein, when the memory device is in the first mode, check bits are communicated via a data mask signal port of the second interface as part of read operations. (0034 & 0049, The data mask signal DM may indicate whether the main data MD is masked. based on the clock signal CLK, and/or may provide the main data MD from the ECC engine 400 to the memory controller 100 in a read operation of the semiconductor memory device 200).
In regards to claim 24, Alzheimer teaches the memory device of claim 22 and teaches:
wherein, when the memory device is in the first mode, check bits are communicated via a data mask signal port of the second interface as part of write operations. (0084, The flag generator 470 may receive the data mask signal DM, may output a flag signal FL with a first logic level (e.g., a high level) when the data mask signal DM designates a masked write operation).
In regards to claim 25, Alzheimer teaches the memory device of claim 22 but fails to teach:
further comprising: check bit deserialization circuitry to, when the memory device is in the first mode, deserialize subsets of check bits as part of write operations.
However, Ayyapureddi teaches:
further comprising: check bit deserialization circuitry to, when the memory device is in the first mode, deserialize subsets of check bits as part of write operations. (0079, the module logic must receive and deserialize the data and parity bits).
It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to modify the method of Alzheimer which teaches A memory device that generates and stores the check bits of error correcting code with the teaching of Ayyapureddi which teaches a memory module with an error correction code (ECC) circuit which pools information multiple memory devices on the module in order to correct data bit errors (Ayyapureddi: 0016, which may be used to correct up to a certain number of errors in the data bits).
In regards to claim 26, Alzheimer teaches the memory device of claim 22 but fails to teach:
further comprising: check bit serialization circuitry to, when the memory device is in the first mode, serialize subsets of check bits as part of read operations.
However, Ayyapureddi teaches:
further comprising: check bit serialization circuitry to, when the memory device is in the first mode, serialize subsets of check bits as part of read operations. (0052, The I/O buffer may receive the serial information so that the deserializer 264 can deserialize the N×M data bits and the K parity bits).
It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to modify the method of Alzheimer which teaches A memory device that generates and stores the check bits of error correcting code with the teaching of Ayyapureddi which teaches a memory module with an error correction code (ECC) circuit which pools information multiple memory devices on the module in order to correct data bit errors (Ayyapureddi: 0016, which may be used to correct up to a certain number of errors in the data bits).
In regards to claim 27, Alzheimer teaches the memory device of claim 25 but fails to teach:
further comprising: data bit deserialization circuitry to, when the memory device is in the first mode, deserialize subsets of data bits as part of write operations.
However, Ayyapureddi teaches:
further comprising: data bit deserialization circuitry to, when the memory device is in the first mode, deserialize subsets of data bits as part of write operations. (0079, the module logic must receive and deserialize the data and parity bits).
It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to modify the method of Alzheimer which teaches A memory device that generates and stores the check bits of error correcting code with the teaching of Ayyapureddi which teaches a memory module with an error correction code (ECC) circuit which pools information multiple memory devices on the module in order to correct data bit errors (Ayyapureddi: 0016, which may be used to correct up to a certain number of errors in the data bits).
In regards to claim 28, Alzheimer teaches the memory device of claim 26 but fails to teach:
further comprising: data bit serialization circuitry to, when the memory device is in the first mode, serialize subsets of data bits as part of read operations.
However, Ayyapureddi teaches:
further comprising: data bit serialization circuitry to, when the memory device is in the first mode, serialize subsets of data bits as part of read operations. (0052, The I/O buffer may receive the serial information so that the deserializer 264 can deserialize the N×M data bits and the K parity bits).
It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to modify the method of Alzheimer which teaches A memory device that generates and stores the check bits of error correcting code with the teaching of Ayyapureddi which teaches a memory module with an error correction code (ECC) circuit which pools information multiple memory devices on the module in order to correct data bit errors (Ayyapureddi: 0016, which may be used to correct up to a certain number of errors in the data bits).
In regards to claim 29, Alzheimer teaches the controller. The claim corresponds to claim 22 as analyzed accordingly.
In regards to claim 30, Alzheimer teaches the controller of claim 29. The claim corresponds to claim 23 as analyzed accordingly.
In regards to claim 31, Alzheimer teaches the controller of claim 29. The claim corresponds to claim 24 as analyzed accordingly.
In regards to claim 32, Alzheimer teaches the controller of claim 29 but fails to teach:
further comprising: check bit deserialization circuitry to, when the controller is in the first mode, deserialize subsets of check bits as part of read operations.
However, Ayyapureddi teaches:
further comprising: check bit deserialization circuitry to, when the controller is in the first mode, deserialize subsets of check bits as part of read operations. (0079, the module logic must receive and deserialize the data and parity bits).
It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to modify the method of Alzheimer which teaches A memory device that generates and stores the check bits of error correcting code with the teaching of Ayyapureddi which teaches a memory module with an error correction code (ECC) circuit which pools information multiple memory devices on the module in order to correct data bit errors (Ayyapureddi: 0016, which may be used to correct up to a certain number of errors in the data bits).
In regards to claim 33, Alzheimer teaches the controller of claim 29 but fails to teach:
further comprising: check bit serialization circuitry to, when the controller is in the first mode, serialize subsets of check bits as part of write operations.
However, Ayyapureddi teaches:
further comprising: check bit serialization circuitry to, when the controller is in the first mode, serialize subsets of check bits as part of write operations. (0052, The I/O buffer may receive the serial information so that the deserializer 264 can deserialize the N×M data bits and the K parity bits).
It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to modify the method of Alzheimer which teaches A memory device that generates and stores the check bits of error correcting code with the teaching of Ayyapureddi which teaches a memory module with an error correction code (ECC) circuit which pools information multiple memory devices on the module in order to correct data bit errors (Ayyapureddi: 0016, which may be used to correct up to a certain number of errors in the data bits).
In regards to claim 34, Alzheimer teaches the controller of claim 32 but fails to teach:
further comprising: data bit deserialization circuitry to, when the controller is in the first mode, deserialize subsets of data bits as part of read operations.
However, Ayyapureddi teaches:
further comprising: data bit deserialization circuitry to, when the controller is in the first mode, deserialize subsets of data bits as part of read operations. (0079, the module logic must receive and deserialize the data and parity bits).
It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to modify the method of Alzheimer which teaches A memory device that generates and stores the check bits of error correcting code with the teaching of Ayyapureddi which teaches a memory module with an error correction code (ECC) circuit which pools information multiple memory devices on the module in order to correct data bit errors (Ayyapureddi: 0016, which may be used to correct up to a certain number of errors in the data bits).
In regards to claim 35, Alzheimer teaches the controller of claim 33 but fails to teach:
further comprising: data bit serialization circuitry to, when the controller is in the first mode, serialize subsets of data bits as part of read operations.
However, Ayyapureddi teaches:
further comprising: data bit serialization circuitry to, when the controller is in the first mode, serialize subsets of data bits as part of read operations. (0052, The I/O buffer may receive the serial information so that the deserializer 264 can deserialize the N×M data bits and the K parity bits).
It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to modify the method of Alzheimer which teaches A memory device that generates and stores the check bits of error correcting code with the teaching of Ayyapureddi which teaches a memory module with an error correction code (ECC) circuit which pools information multiple memory devices on the module in order to correct data bit errors (Ayyapureddi: 0016, which may be used to correct up to a certain number of errors in the data bits).
In regards to claim 36, Alzheimer teaches the memory module. The claim corresponds to claim 22 as analyzed accordingly.
In regards to claim 37, Alzheimer teaches the memory module of claim 36. The claim corresponds to claim 23 as analyzed accordingly.
In regards to claim 38, Alzheimer teaches the memory module of claim 36. The claim corresponds to claim 24 as analyzed accordingly.
In regards to claim 39, Alzheimer teaches the memory module of claim 36. The claim corresponds to claim 25 as analyzed accordingly.
In regards to claim 40, Alzheimer teaches the memory module of claim 36. The claim corresponds to claim 26 as analyzed accordingly.
In regards to claim 41, Alzheimer teaches the memory module of claim 39. The claim corresponds to claim 27 as analyzed accordingly.
Conclusion
Claims 22 - 41 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 2-21 of U.S. Patent No. 2024/0036975 A1. Although the claims at issue are not identical, they are not patentably distinct from each other because they are claiming similar subject matter as shown.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Park (US 10997020 B2) A memory device, a memory system, and a method of operating the same. The memory device includes a memory cell array including a plurality of memory cells and a write command determination unit (WCDU) that determines whether a write command input to the memory device is (to be) accompanied a masking signal.
WARE (US 20230086896 A1) A memory component internally generates and stores the check bits of error detect and correct code (EDC). In a first mode, during a read transaction, the check bits are sent to the memory controller along with the data on the data mask (DM) signal lines. In a second mode, an unmasked write transaction is defined where the check bits are sent to the memory component on the data mask signal lines. In a third mode, a masked write transaction is defined where at least a portion of the check bits are sent from the memory controller on the data signal lines coincident with an asserted data mask signal line. By sending the check bits along with the data, the EDC code can be used to detect and correct errors that occur between the memory component and the memory controller.
Miller (US 2022/0327021 A1) The following disclosure relates to, among other things, memory components, memory controllers, and/or systems that have features and/or functionality for error detection and correction. A way of accessing data and error correction information involves accessing multiple data channels (e.g., 8) and one error detection and correction channel concurrently.
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/V.P./Examiner, Art Unit 2111
/MARK D FEATHERSTONE/Supervisory Patent Examiner, Art Unit 2111