DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102
and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same
under either status.
Response to Arguments
Applicant's arguments filed 04/08/2026 regarding the prior art rejections of Claims 1 - 30 have been fully considered, but they are not persuasive.
The Remarks argue that:
Applicant respectfully submits that "programming" which "bits to poison" are indications of "bit-flip" positions and are thus not ECC check bits.
Applicant submits that Alzheimer consistently describes a memory device in which ECC check bits are generated, stored, retrieved, and used entirely within the memory device and are thus the check bits of Alzheimer are never transmitted from, or received by, the memory device of Alzheimer.
Applicant respectfully submits that Alzheimer does not disclose, teach, or suggest a first
mode where the check bits are received (and transmitted) via a second interface separate from the data interface used in both the first and second modes.
Applicant respectfully submits that Alzheimer, either alone or in combination with Ayyapureddi, fails to disclose, teach, or suggest at least a memory device with a second interface to, when the memory device is in a first mode, as part of write operations, receive groups of check bits to be stored in the second plurality of memory elements, and to, as part of read operations, transmit groups of check bits received from the second plurality of memory elements (claim 22); a controller with a second interface to, when the controller is in a first mode, as part of write operations, transmit groups of check bits to be stored by the second plurality of memory elements, and to, as part of read operations, receive groups of check bits stored by the second plurality of memory elements (claim 29); nor a memory module with a second external interface to, when the memory module is in a first mode, as part of write operations, receive groups of check bits for the plurality of memory devices ... and to, as part of read operations, transmit groups of check bits respectively received from the second plurality of memory elements of the plurality of memory devices (claim 36).
The Examiner disagrees as these statements contradict each other. Alzheimer teaches ECC check bits to detect and correct errors as well as transmitting and receiving the check bits. (0029,0010, & 0038, ECC circuit may detect and/or correct one or more errors in the data read from the memory array 150.the memory device, may compute a set of ECC check bits (e.g., 8 bits, a first group of check bits) using the data (e.g., 128 bits of data) and then writes the code word (e.g., 136 bits including the data and the ECC check bits) to the address within the memory array. The peripheral circuitry 215 can transmit the external data back to the host device 270 through the I/O bus 245. In this manner, the host device 270 can confirm (validate, verify) the on-die ECC functionality)
In the presented disclosure, the interfaces refer to a data interface and a data mask interface. Alzheimer teaches multiple interface and data masking. (0053 & 0016, The control circuitry 306 communicates with the host device 308 over a host-device bus or interface 310. In some embodiments, the host device 308 and the control circuitry 306 can communicate over a dedicated memory bus (e.g., a DRAM bus). In other embodiments, the host device 308 and the control circuitry 306 can communicate over a serial interface, such as a serial attached SCSI (SAS), a serial AT attachment (SATA) interface, a peripheral component interconnect express (PCIe), or other suitable interface (e.g., a parallel interface). The host device 308 can send various requests (in the form of, e.g., a packet or stream of packets) to the control circuitry 306. A request can include a command to read, write, erase, return information, and/or to perform a particular operation (e.g., a refresh operation, a TRIM operation, a precharge operation, an activate operation, a wear-leveling operation, a garbage collection operation, etc.).The memory device 100 may employ a plurality of external terminals that include command and address terminals coupled to a command bus and an address bus to receive command signals CMD and address signals ADDR, respectively. The memory device may further include a chip select terminal to receive a chip select signal CS, clock terminals to receive clock signals CK and CKF, data clock terminals to receive data clock signals WCK and WCKF, data terminals DQ, RDQS, DBI (for data bus inversion function), and DMI (for data mask inversion function), power supply terminals VDD, VSS, and VDDQ.)
The Examiner disagrees Alzheimer in combination with Ayyapureddi discloses, teaches, and suggests the features recited in independent claims 22, 29, & 36. The previous prior art rejection is maintained.
Claims 23 – 28 which depend from claim 22, have been considered and rejected.
Claims 30 – 35 which depend from claim 29, have been considered and rejected.
Claims 37 – 41 which depend from claim 36, have been considered and rejected.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 22 - 41 are rejected under 35 U.S.C. 103 as being unpatentable over Alzheimer (US 2022/0149866 A1) in view of Ayyapureddi (US 2024/0071550 A1).
In regards to claim 22, Alzheimer teaches:
A memory device, comprising: a first plurality of memory elements to store data bits and a second plurality of memory elements to store check bits associated with the data bits (0015, Memory cells can include any one of a number of different memory media types, including capacitive, phase change, magneto resistive, ferroelectric, or the like. In some embodiments, a portion of the memory array 150 may be configured to store ECC parity bits); a first interface to communicate groups of data bits; a second interface to, when the memory device is in a first mode, as part of write operations, receive groups of check bits to be stored in the second plurality of memory elements, and to, as part of read operations, transmit groups of check bits received from the second plurality of memory elements; and the memory device to, when the memory device is in a second mode, generate and store, in the second plurality of memory elements, check bits in response to write operations (0053 & 0012, In other embodiments, the host device 308 and the control circuitry 306 can communicate over a serial interface, such as a serial attached SCSI (SAS), a serial AT attachment (SATA) interface, a peripheral component interconnect express (PCIe), or other suitable interface (e.g., a parallel interface). The host device 308 can send various requests (in the form of, e.g., a packet or stream of packets) to the control circuitry 306. the host device may access one or more mode registers of the memory device to indicate (program) which bit or bits to poison while executing an access command (e.g., a write command, a read command)), and to use check bits received from the second plurality of memory elements to detect, in response to read operations, errors in data bits and associated check bits that are manifested when the data bits and associated check bits are retrieved from the first plurality of memory elements and the second plurality of memory elements, respectively. (0010, the memory device may attempt to detect and/or correct at least one error before transmitting the data (e.g., 128 bits of data) to the memory controller. In some embodiments, the memory device reads the code word from the address, and compute another set of ECC check bits (e.g., 8 bits, a second group of check bits) using the data read from the address. Subsequently, the memory device may compare the first group of ECC check bits read from the address).
In regards to claim 23, Alzheimer teaches the memory device of claim 22 and teaches:
wherein, when the memory device is in the first mode, check bits are communicated via a data mask signal port of the second interface as part of read operations. (0034 & 0049, The data mask signal DM may indicate whether the main data MD is masked. based on the clock signal CLK, and/or may provide the main data MD from the ECC engine 400 to the memory controller 100 in a read operation of the semiconductor memory device 200).
In regards to claim 24, Alzheimer teaches the memory device of claim 22 and teaches:
wherein, when the memory device is in the first mode, check bits are communicated via a data mask signal port of the second interface as part of write operations. (0084, The flag generator 470 may receive the data mask signal DM, may output a flag signal FL with a first logic level (e.g., a high level) when the data mask signal DM designates a masked write operation).
In regards to claim 25, Alzheimer teaches the memory device of claim 22 but fails to teach:
further comprising: check bit deserialization circuitry to, when the memory device is in the first mode, deserialize subsets of check bits as part of write operations.
However, Ayyapureddi teaches:
further comprising: check bit deserialization circuitry to, when the memory device is in the first mode, deserialize subsets of check bits as part of write operations. (0079, the module logic must receive and deserialize the data and parity bits).
It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to modify the method of Alzheimer which teaches A memory device that generates and stores the check bits of error correcting code with the teaching of Ayyapureddi which teaches a memory module with an error correction code (ECC) circuit which pools information multiple memory devices on the module in order to correct data bit errors (Ayyapureddi: 0016, which may be used to correct up to a certain number of errors in the data bits).
In regards to claim 26, Alzheimer teaches the memory device of claim 22 but fails to teach:
further comprising: check bit serialization circuitry to, when the memory device is in the first mode, serialize subsets of check bits as part of read operations.
However, Ayyapureddi teaches:
further comprising: check bit serialization circuitry to, when the memory device is in the first mode, serialize subsets of check bits as part of read operations. (0052, The I/O buffer may receive the serial information so that the deserializer 264 can deserialize the N×M data bits and the K parity bits).
It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to modify the method of Alzheimer which teaches A memory device that generates and stores the check bits of error correcting code with the teaching of Ayyapureddi which teaches a memory module with an error correction code (ECC) circuit which pools information multiple memory devices on the module in order to correct data bit errors (Ayyapureddi: 0016, which may be used to correct up to a certain number of errors in the data bits).
In regards to claim 27, Alzheimer teaches the memory device of claim 25 but fails to teach:
further comprising: data bit deserialization circuitry to, when the memory device is in the first mode, deserialize subsets of data bits as part of write operations.
However, Ayyapureddi teaches:
further comprising: data bit deserialization circuitry to, when the memory device is in the first mode, deserialize subsets of data bits as part of write operations. (0079, the module logic must receive and deserialize the data and parity bits).
It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to modify the method of Alzheimer which teaches A memory device that generates and stores the check bits of error correcting code with the teaching of Ayyapureddi which teaches a memory module with an error correction code (ECC) circuit which pools information multiple memory devices on the module in order to correct data bit errors (Ayyapureddi: 0016, which may be used to correct up to a certain number of errors in the data bits).
In regards to claim 28, Alzheimer teaches the memory device of claim 26 but fails to teach:
further comprising: data bit serialization circuitry to, when the memory device is in the first mode, serialize subsets of data bits as part of read operations.
However, Ayyapureddi teaches:
further comprising: data bit serialization circuitry to, when the memory device is in the first mode, serialize subsets of data bits as part of read operations. (0052, The I/O buffer may receive the serial information so that the deserializer 264 can deserialize the N×M data bits and the K parity bits).
It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to modify the method of Alzheimer which teaches A memory device that generates and stores the check bits of error correcting code with the teaching of Ayyapureddi which teaches a memory module with an error correction code (ECC) circuit which pools information multiple memory devices on the module in order to correct data bit errors (Ayyapureddi: 0016, which may be used to correct up to a certain number of errors in the data bits).
In regards to claim 29, Alzheimer teaches the controller. The claim corresponds to claim 22 as analyzed accordingly.
In regards to claim 30, Alzheimer teaches the controller of claim 29. The claim corresponds to claim 23 as analyzed accordingly.
In regards to claim 31, Alzheimer teaches the controller of claim 29. The claim corresponds to claim 24 as analyzed accordingly.
In regards to claim 32, Alzheimer teaches the controller of claim 29 but fails to teach:
further comprising: check bit deserialization circuitry to, when the controller is in the first mode, deserialize subsets of check bits as part of read operations.
However, Ayyapureddi teaches:
further comprising: check bit deserialization circuitry to, when the controller is in the first mode, deserialize subsets of check bits as part of read operations. (0079, the module logic must receive and deserialize the data and parity bits).
It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to modify the method of Alzheimer which teaches A memory device that generates and stores the check bits of error correcting code with the teaching of Ayyapureddi which teaches a memory module with an error correction code (ECC) circuit which pools information multiple memory devices on the module in order to correct data bit errors (Ayyapureddi: 0016, which may be used to correct up to a certain number of errors in the data bits).
In regards to claim 33, Alzheimer teaches the controller of claim 29 but fails to teach:
further comprising: check bit serialization circuitry to, when the controller is in the first mode, serialize subsets of check bits as part of write operations.
However, Ayyapureddi teaches:
further comprising: check bit serialization circuitry to, when the controller is in the first mode, serialize subsets of check bits as part of write operations. (0052, The I/O buffer may receive the serial information so that the deserializer 264 can deserialize the N×M data bits and the K parity bits).
It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to modify the method of Alzheimer which teaches A memory device that generates and stores the check bits of error correcting code with the teaching of Ayyapureddi which teaches a memory module with an error correction code (ECC) circuit which pools information multiple memory devices on the module in order to correct data bit errors (Ayyapureddi: 0016, which may be used to correct up to a certain number of errors in the data bits).
In regards to claim 34, Alzheimer teaches the controller of claim 32 but fails to teach:
further comprising: data bit deserialization circuitry to, when the controller is in the first mode, deserialize subsets of data bits as part of read operations.
However, Ayyapureddi teaches:
further comprising: data bit deserialization circuitry to, when the controller is in the first mode, deserialize subsets of data bits as part of read operations. (0079, the module logic must receive and deserialize the data and parity bits).
It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to modify the method of Alzheimer which teaches A memory device that generates and stores the check bits of error correcting code with the teaching of Ayyapureddi which teaches a memory module with an error correction code (ECC) circuit which pools information multiple memory devices on the module in order to correct data bit errors (Ayyapureddi: 0016, which may be used to correct up to a certain number of errors in the data bits).
In regards to claim 35, Alzheimer teaches the controller of claim 33 but fails to teach:
further comprising: data bit serialization circuitry to, when the controller is in the first mode, serialize subsets of data bits as part of read operations.
However, Ayyapureddi teaches:
further comprising: data bit serialization circuitry to, when the controller is in the first mode, serialize subsets of data bits as part of read operations. (0052, The I/O buffer may receive the serial information so that the deserializer 264 can deserialize the N×M data bits and the K parity bits).
It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to modify the method of Alzheimer which teaches A memory device that generates and stores the check bits of error correcting code with the teaching of Ayyapureddi which teaches a memory module with an error correction code (ECC) circuit which pools information multiple memory devices on the module in order to correct data bit errors (Ayyapureddi: 0016, which may be used to correct up to a certain number of errors in the data bits).
In regards to claim 36, Alzheimer teaches the memory module. The claim corresponds to claim 22 as analyzed accordingly.
In regards to claim 37, Alzheimer teaches the memory module of claim 36. The claim corresponds to claim 23 as analyzed accordingly.
In regards to claim 38, Alzheimer teaches the memory module of claim 36. The claim corresponds to claim 24 as analyzed accordingly.
In regards to claim 39, Alzheimer teaches the memory module of claim 36. The claim corresponds to claim 25 as analyzed accordingly.
In regards to claim 40, Alzheimer teaches the memory module of claim 36. The claim corresponds to claim 26 as analyzed accordingly.
In regards to claim 41, Alzheimer teaches the memory module of claim 39. The claim corresponds to claim 27 as analyzed accordingly.
Prior Art Made of Record
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Park (US 10997020 B2) A memory device, a memory system, and a method of operating the same. The memory device includes a memory cell array including a plurality of memory cells and a write command determination unit (WCDU) that determines whether a write command input to the memory device is (to be) accompanied a masking signal.
WARE (US 2023/0086896 A1) A memory component internally generates and stores the check bits of error detect and correct code (EDC). In a first mode, during a read transaction, the check bits are sent to the memory controller along with the data on the data mask (DM) signal lines. In a second mode, an unmasked write transaction is defined where the check bits are sent to the memory component on the data mask signal lines. In a third mode, a masked write transaction is defined where at least a portion of the check bits are sent from the memory controller on the data signal lines coincident with an asserted data mask signal line. By sending the check bits along with the data, the EDC code can be used to detect and correct errors that occur between the memory component and the memory controller.
Miller (US 2022/0327021 A1) The following disclosure relates to, among other things, memory components, memory controllers, and/or systems that have features and/or functionality for error detection and correction. A way of accessing data and error correction information involves accessing multiple data channels (e.g., 8) and one error detection and correction channel concurrently.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office
action. Applicant's arguments filed 04/08/2026 regarding the prior art rejections of Claims 22 – 41 have
been fully considered and are persuasive.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/V.P./Examiner, Art Unit 2111
/GUERRIER MERANT/Primary Examiner, Art Unit 2111 6/11/2026
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