DETAILED ACTION
Response to Amendment
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-6, and 8-10 are rejected under 35 U.S.C. 103 as being unpatentable over Chialastri et al. (U.S. Patent Application Publication Number 2023/0109810) and Kuo et al. (U.S. Patent Application Publication Number 2025/0103334).
Regarding Claim 1, Chialastri discloses a performance control method, performed by a baseboard management controller (Figure 1, item 108, paragraphs 0021-0022), comprising:
obtaining a sensed temperature (Figure 1, item 112) of a processor (Figure 1, item 102, paragraph 0018) or a pulse-width modulation chip;
determining whether the sensed temperature is greater than a default temperature (paragraph 0020; i.e., the thermal operating limit that is specified by the manufacturer of the processor 102 is equivalent to the claimed “default temperature”);
lowering a underclocking standard for the processor and operating power of the processor when the sensed temperature is greater than the default temperature (paragraphs 0019-0020; i.e., the voltage and current that is provided to the processor 102 [the claimed “underclocking standard” and “operating power”] would be lowered such that the processor 102 cannot operate above that set point if the sensed temperature exceeds the thermal operating limit); and
increasing the underclocking standard for the processor and the operating power of the processor when the sensed temperature is not greater than the default temperature (paragraphs 0019-0020; i.e., the voltage and current that is provided to the processor 102 can be increased such that the processor 102 cannot operate above that higher set point if the sensed temperature is less than the thermal operating limit).
Chialastri does not expressly disclose wherein the lowering and increasing of the underclocking standard is of a pulse-width modulation chip;
wherein lowering the underclocking standard of the pulse-width modulation chip for the processor comprises lowering a current upper limit stored in the pulse-width modulation chip.
In the same field of endeavor (e.g., processor power controlling techniques), Kuo teaches wherein the lowering and increasing of the underclocking standard is of a pulse-width modulation chip (Figure 2, item 2, paragraphs 0023; i.e., electronic component 2 may include a PWM controller and is therefore equivalent to the claimed “pulse-width modulation chip”);
wherein lowering the underclocking standard of the pulse-width modulation chip for the processor comprises lowering a current upper limit (paragraph 0019; i.e., the PL2 power limit value) stored in the pulse-width modulation chip (Figure 2, item 22, paragraph 0024; i.e., it would have been obvious to one of ordinary skill in the art to have stored the PL2 power limit value in the pulse-width modulation chip 2 since it has been held that rearranging parts of an invention [e.g., moving the memory which contains the PL2 value from one component to another component] involves only routine skill in the art - In re Japikse, 181 F.2d 1019 (CCPA 1950)).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined Kuo’s teachings of processor power controlling techniques with the teachings of Chialastri, for the purpose of offering superior energy efficiency, minimal heat generation, and precise, rapid control over power delivery compared to analog methods. By switching between full-on and full-off states, PWM reduces energy loss in switching devices and allows for seamless integration with digital, high-frequency, low-voltage processors.
Regarding Claim 3, Kuo teaches wherein increasing the underclocking standard of the pulse-width modulation chip for the processor comprises increasing a current upper limit stored in the pulse-width modulation chip (paragraph 0033), and the pulse-width modulation chip outputs an underclocking signal to the processor when the pulse-width modulation chip determines that a working current of the processor is greater than the current upper limit (paragraphs 0028-0029; i.e., if the desired power level [which includes both voltage and current; P=IV] is reduced from, e.g., 135 W [PL2] to 65 W [PL1], then the processor would be sent a signal [the claimed “underclocking signal”] to reduce its power as long as its power consumption is still above 65 W; as discussed above, although the reference states that this signal is transmitted by the BIOS 7, it is the pulse-width modulation chip 2 that ultimately controls the power transmitted to the processor 1).
Regarding Claim 4, Kuo teaches wherein increasing the operating power of the processor comprises increasing a thermal design power value stored in the pulse-width modulation chip, wherein the thermal design power value is positively associated with a power consumption upper limit of the processor (paragraphs 0018-0020; i.e., the thermal design power [TDP] level may be modified to reflect the PL2 limit, e.g., 135 W).
Regarding Claim 5, Kuo teaches obtaining an optimization command (paragraph 0028; i.e., a Query event command),
wherein obtaining the sensed temperature is performed after obtaining the optimization command (paragraph 0028; i.e., the sensed temperature would once again be checked [paragraph 0033] after the power is reduced to ensure that it is still not above the threshold temperature).
Regarding Claim 6, Chialastri discloses a performance control system (Figure 1, item 100) comprising:
a temperature sensor (Figure 1, item 112) configured to perform sensing on a processor (Figure 1, item 102) or the pulse-width modulation chip to generate a sensed temperature (paragraph 0018); and
a baseboard management controller (Figure 1, item 108, paragraphs 0021-0022) connected to the temperature sensor, wherein the baseboard management controller is configured to determine whether the sensed temperature is greater than a default temperature (paragraph 0020; i.e., the thermal operating limit that is specified by the manufacturer of the processor 102 is equivalent to the claimed “default temperature”), lower a underclocking standard for the processor and operating power of the processor when the sensed temperature is greater than the default temperature (paragraphs 0019-0020; i.e., the voltage and current that is provided to the processor 102 [the claimed “underclocking standard” and “operating power”] would be lowered such that the processor 102 cannot operate above that set point if the sensed temperature exceeds the thermal operating limit), and increase the underclocking standard for the processor and the operating power of the processor when the sensed temperature is not greater than the default temperature (paragraphs 0019-0020; i.e., the voltage and current that is provided to the processor 102 can be increased such that the processor 102 cannot operate above that higher set point if the sensed temperature is less than the thermal operating limit).
Chialastri does not expressly disclose a pulse-width modulation chip;
wherein the baseboard management controller is connected to the pulse-width modulation chip;
wherein the lowering and increasing of the underclocking standard is of a pulse-width modulation chip;
wherein the baseboard management controller lowering the underclocking standard of the pulse-width modulation chip for the processor comprises lowering a current upper limit stored in the pulse-width modulation chip.
In the same field of endeavor, Kuo teaches a pulse-width modulation chip (Figure 2, item 2, paragraphs 0023; i.e., electronic component 2 may include a PWM controller and is therefore equivalent to the claimed “pulse-width modulation chip”);
wherein the baseboard management controller (Figure 2, item 3, paragraph 0025) is connected to the pulse-width modulation chip;
wherein the lowering and increasing of the underclocking standard is of a pulse-width modulation chip (paragraphs 0023-0025; i.e., although the reference states that the lowering and increasing of the power levels [the "underclocking standard"] to the processor 1 occurs via the BIOS 7, it is the pulse-width modulation chip 2 that actually supplies the operating voltage and clock to the processor 1; therefore, the lowering and increasing of the underclocking standard is of the pulse-width modulation chip 2);
wherein the baseboard management controller lowering the underclocking standard of the pulse-width modulation chip for the processor comprises lowering a current upper limit (paragraph 0019; i.e., the PL2 power limit value) stored in the pulse-width modulation chip (Figure 2, item 22, paragraph 0024; i.e., it would have been obvious to one of ordinary skill in the art to have stored the PL2 power limit value in the pulse-width modulation chip 2 since it has been held that rearranging parts of an invention [e.g., moving the memory which contains the PL2 value from one component to another component] involves only routine skill in the art - In re Japikse, 181 F.2d 1019 (CCPA 1950)).
The motivation discussed above with regards to Claim 1 applies equally as well to Claim 6.
Regarding Claim 8, Kuo teaches wherein the baseboard management controller increasing the underclocking standard of the pulse-width modulation chip for the processor comprises increasing a current upper limit stored in the pulse-width modulation chip (paragraph 0033), and the pulse-width modulation chip outputs a underclocking signal to the processor when the pulse-width modulation chip determines that a working current of the processor is greater than the current upper limit (paragraphs 0028-0029; i.e., if the desired power level [which includes both voltage and current; P=IV] is reduced from, e.g., 135 W [PL2] to 65 W [PL1], then the processor would be sent a signal [the claimed “underclocking signal”] to reduce its power as long as its power consumption is still above 65 W; as discussed above, although the reference states that this signal is transmitted by the BIOS 7, it is the pulse-width modulation chip 2 that ultimately controls the power transmitted to the processor 1).
Regarding Claim 9, Kuo teaches wherein the baseboard management controller increasing the operating power of the processor comprises increasing a thermal design power value stored in the pulse-width modulation chip, wherein the thermal design power value is positively associated with a power consumption upper limit of the processor (paragraphs 0018-0020; i.e., the thermal design power [TDP] level may be modified to reflect the PL2 limit, e.g., 135 W).
Regarding Claim 10, Kuo teaches wherein the baseboard management controller obtains the sensed temperature after obtaining an optimization command (paragraph 0028; i.e., the sensed temperature would once again be checked [paragraph 0033] after the power is reduced, which occurs after obtaining the Query event command [the “optimization command”] to ensure that it is still not above the threshold temperature).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure because each reference discloses a method for adjusting the underclocking standard of a processor based on a sensed temperature.
Response to Arguments
Applicant's arguments filed 4/13/26 have been fully considered but they are not persuasive.
Regarding Claim 1, Applicant argues “Kuo discloses lowering the power of CPU through BIOS, Kuo does not disclose lowering the current upper limit stored in the electronic component 2.” Response, page 5. While the examiner does not necessarily agree that the current upper limit is stored in the CPU of Kuo, it still would have been obvious to one of ordinary skill in the art to have stored the PL2 power limit value (the claimed “current upper limit”) in the pulse-width modulation chip 2 since it has been held that rearranging parts of an invention (e.g., moving the memory which contains the PL2 value from one component to another component) involves only routine skill in the art. See In re Japikse, 181 F.2d 1019 (CCPA 1950). Accordingly, Applicant’s argument is not persuasive.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FAISAL M ZAMAN whose telephone number is (571)272-6495. The examiner can normally be reached Monday - Friday, 8 am - 5 pm, alternate Fridays.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrew J. Jung can be reached at 571-270-3779. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/FAISAL M ZAMAN/ Primary Examiner, Art Unit 2175
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