Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is responsive to the Application filed August 14, 2026.
Status of claims to be treated in this office action:
a. Independent: 1, 6, 16, 18
b. Pending: 1, 3-20
Claims 1, 3-6, 9, 16 have been amended and claim 2 has been canceled.
Drawings
The objection to the drawings is withdrawn. Examiner acknowledges the information regarding the drawings with appreciation.
Specification
The new title has been reviewed and accepted by the Examiner.
Claim Objections
The claim objections are withdrawn pursuant to claim amendments.
Claim Rejections - 35 USC § 112
The 112(b) claim rejections are withdrawn pursuant to claim amendments.
Response to Arguments
Applicant’s arguments, see pages 8-19, filed August 14, 2026, with respect to claims 1, 3-15, and 18-20 have been fully considered and are persuasive. The rejection of claims 1, 3-15, and 18-20 has been withdrawn.
Applicant's arguments regarding claims 16-17, filed August 14, 2026, have been fully considered but they are not persuasive. Examiner used Lee et al. (US Pub. 20190244662 A1; “Lee”) to reject the following limitations of claim 16: “An analog filter with a tuneable filter property, the filter comprising: control a threshold voltage of that charge-trapping-transistors so as to tune said filter property.” The Applicant provided arguments against this rejection, but they are not persuasive for the following reasons:
Applicant argues, “the resistive potential divider 666 used in Lee to generate the measurement threshold is not formed from programmable CTT elements but is formed from fixed resistors”. However, Lee para. [0103] states “the array of programmable resistance cells can be configured into functional sets having one input and multiple members to implement a term Xi Wi of the sum-of-products operation in which the weight Wi can be values other than a one bit binary “0” or “1”, such as a multiple bit binary value, using a single bit value programmed in the programmable transistors in the cells”. This proves that the “array of programmable resistance cells”, or component 665, may be comprised of programmable transistors, not “fixed resistors”. Examiner has updated the rejection of claim 16 such that the whole circuit of Lee Fig. 14 is mapped to the “analog filter”. Thus, the “reference column or reference columns 665 in the array of programmable resistance cells” is included in the analog filter and the Applicant’s argument is unpersuasive.
Applicant also argues, “in this case the programming of the relevant reference column is fixed and is not varied in use. In this case, Lee programs the CTTs in the reference columns into defined fixed states to provide the relevant voltage Vmax and Vmin. There is only one programming state for the reference column that will generate the desired voltage Vmax, and likewise only one programming state for the reference column that will generate the desired voltage Vmin. One skilled in the art reading Lee would thus understand that these reference columns are operated with a fixed programming that is not varied in use.” Per item 1 above, since the updated rejection maps all of Lee Fig. 14 to the analog filter, the analog filter comprises the “programmable resistance cells”, which are programmable and therefore tunable.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Pan (US Pub. 20130069141 A1; “Pan”) in view of Lee (US Pub. 20190244662 A1).
Regarding independent claim 16, Pan discloses:
at least one charge-trapping-transistor (Fig. 4: memory module ST00; [0042]: Each memory module STxy comprises the following devices connected sequentially in series: one drain selection transistor (DST), z memory cell transistors, one bottom connecting line at a folding part, z SONOS memory cell transistors and one source selection transistor (SST). Examiner notes that SONOS is a type of charge-trapping transistor);
programming circuitry (Fig. 5: M120; [0047]: drain selection transistor 120) configured to selectively programme ([0053]: For a SONOS memory cell transistor A to be programmed…a positive programming voltage VP1 (e.g., 3V) is applied to a bit line connected to a drain of a drain selection transistor in the memory module comprising the memory cell transistor A, and the remaining bit lines are grounded) an amount of charge trapped by each of said at least one charge-trapping-transistor ([0002]: In the SONOS flash memory, a charge (an electron or a hole) is injected into a silicon nitride layer through a tunneling oxide layer by using a quantum is tunneling or hot carrier injection effect, and trapped by charge traps in the silicon nitride layer, thus changing a threshold voltage of a device cell and achieving data storage) so as to
Pan does not disclose:
An analog filter with a tuneable filter property, the filter comprising:
control a threshold voltage of the one or more charge-trapping-transistors so as to tune said filter property.
However, Lee teaches:
An analog filter (Fig. 14; [0028]: FIG. 14 is a simplified diagram of a reference voltage circuit that can be utilized with sensing circuitry like that of FIG. 13. Examiner notes that per p.51, lines 34-35 of the Specification of the present application, “Figure 37 illustrates one example of a basic tuneable voltage divider circuit 3700 using a CTT, which can be seen as a passive filter”. Thus, the resistive voltage divider 666 within the reference voltage circuit of Fig. 14 is analogous to a filter) with a tuneable filter property ([0089]: a reference column or reference columns 665 in the array of programmable resistance cells, or using cell structures like those used in the array, can be arranged to provide one or both of the voltages Vmax and Vmin), the filter comprising:
control a threshold voltage of the one or more charge-trapping-transistors so as to tune said filter property ([0044]: The programmable threshold transistor 35 can be implemented using a floating gate memory cell…such as a SONOS device or other types of dielectric charge trapping cells; [0103]: the array of programmable resistance cells can be configured into functional sets…in which the weight Wi can be values other than a one bit binary “0” or “1”, such as a multiple bit binary value, using a single bit value programmed in the programmable transistors in the cells. Examiner concludes that adjusting the threshold voltage of the programmable transistors within the reference columns 665 adjusts the voltage divider 666).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Lee to modified Pan wherein there is an analog filter with a tuneable filter property, and programming circuitry that controls a threshold voltage of the one or more charge-trapping-transistors so as to tune said filter property in order to reduce power consumption by using voltage sensing amplifiers that limit the magnitude of current needed to calculate the sum-of-products (Lee, [0008]).
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Pan (US Pub. 20130069141 A1) and Lee (US Pub. 20190244662 A1) as applied to claim 16 above, and further in view of Cao (CN 109217827 A).
Regarding claim 17, Pan and Lee together disclose all the limitations of claim 16. Neither Pan nor Lee discloses:
wherein the filter property comprises at least one of a cutoff frequency and a signal band gain.
However, Cao teaches:
wherein the filter property comprises at least one of a cutoff frequency and a signal band gain ([0004]: The design of the low-pass filter is related to factors such as speaker impedance, switching frequency and cutoff frequency of the Class D power amplifier).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Cao to modified Pan wherein the filter property comprises at least one of a cutoff frequency and a signal band gain in order to provide a signal processing device that compensates for gain attenuation and phase distortion cause by a filter (Cao, [0006]).
Allowable Subject Matter
Claims 1, 3-15, and 18-20 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Independent claims 1, 6, and 18 include allowable subject matter since the prior art made of record and considered pertinent to the applicant’s disclosure, taken individually or in combination, does not teach or suggest the claimed invention having:
Regarding both claims 1 and 6:
“wherein the first charge-trapping-transistor cell is configured as part of the analog signal processing circuit such that programmably varying the threshold voltage of the one or more charge-trapping-transistors varies a parameter of a transfer function of the analog signal processing circuit”
Further regarding claim 1:
“wherein the analog signal processing circuit comprises an amplification circuit and said parameter of the transfer function comprises an amplifier gain.”
Further regarding claim 6:
“wherein the analog signal processing circuit comprises a filter circuit and said parameter of the transfer function comprises a cutoff frequency of the filter circuit.”
Regarding claim 18:
“a second charge-trapping-transistor cell comprising a second set of one or more charge- trapping-transistors, the second charge-trapping-transistor cell being configured in a feedback path between an output node for outputting an output signal from the op-amp and said first node;
wherein a non-inverting input of the op-amp is connected to a defined reference voltage and the input signal can vary positively and negatively with respect to the defined reference voltage.”
The Examiner was not able to find additional references to logically combine with Pan, Wang, Lee, Yuasa, Cao, Gosson, and Wang-249 in order to reject the other above features of claims 1, 6, and 18. Claims 3-5, 7-15, and 19-20 are also allowed due to their dependency on claims 1, 6, and 18.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/E.R.A./Examiner, Art Unit 2824
/SULTANA BEGUM/Primary Examiner, Art Unit 2824
9/25/2026
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