Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
Claim 14 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Specifically, claim 14 discloses “wherein the metal posts include at least one of a plurality of different shapes and a plurality of different areas” (emphasis added), yet nowhere in the specification is this description mentioned; at best the specification describes two or more solder bumps having different shapes and/or sizes (see [0024]).
Claims 24 and 29 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 24 and 29 recite the limitation "the plurality of lead terminals". There is insufficient antecedent basis for this limitation in the claim. For the sake of further analysis, the term is interpreted as meaning the same as “a plurality of bondable features” (see claims 21 and 25 respectively) due to the similarity in wording.
Claim Rejections - 35 USC § 103
Claim(s) 10, 12-15, 18, 20-21, and 24 are rejected under 35 U.S.C. 103 as being unpatentable over Uzoh (PGPub No. 20150325507).
Regarding claim 10, Uzoh teaches an assembly method, comprising: printing a solder paste onto a plurality of bondable features of a package substrate (Fig. 23; 2310, 120A, 110A); reflowing the solder paste (Fig. 24; 210); flip chip die attaching at least one integrated circuit (IC) die comprising a substrate having circuitry configured for realizing at least one function including nodes (Fig. 29; 110B) coupled to bond pads (Fig. 14C; 120B) with metal posts on the bond pads to the bondable features (Figs. 14C and 29; 1240), and again reflowing the solder paste to form a solder joint between the metal posts and the bondable feature ([0039] points to the insertion of posts 1240 (metal posts) occurring before or during the solder reflow. It is thus considered obvious that insertion of the posts 1240 during the solder reflow would result in a three-step process comprising a first solder reflow step, an insertion step, and finally a second solder reflow step resulting in a final stack 210 (solder joint).).
Regarding claim 12, Uzoh teaches wherein the printing comprises screen printing using a screen-printing stencil ([0079] points to a solder locking layer 2210 that will provide a stencil if screen printing is used.).
Regarding claim 14, Uzoh teaches wherein the metal posts include at least one of a plurality of different shapes and a plurality of different areas (Figs. 14C and 29; 1240).
Regarding claim 15, Uzoh teaches wherein the reflowing the solder paste again and the reflowing the solder paste both comprise a vacuum reflow ([0082] points to performing reflow in vacuum.).
Regarding claim 18, Uzoh teaches wherein a bond line thickness (BLT) of the solder joint is at least 55 µm ([0007] points to the stack 210 (solder joint) comprising a stack of four solder balls 140.1 – 140.4. [0019] further points to the diameter of a single solder ball being for example from 25 μm to 500 μm, possibly not more than 250 μm, possibly not more than 175 μm; in other words, the connection stack 210 would have a minimum height of 100 µm. In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).).
Regarding claim 20, Uzoh teaches wherein the flip chip die attaching further comprises attaching a second IC die to the plurality of bondable features (Fig. 30; 110C).
Regarding claim 21, Uzoh teaches a method of making a semiconductor device assembly, comprising: providing a package substrate having a top side including a plurality of bondable features (Fig. 29; 110A, 120A); and providing at least one integrated circuit (IC) die comprising a substrate including at least a semiconductor surface having circuitry configured for realizing at least one function including nodes (Id.; 110B) coupled to bond pads (Fig. 14C; 120B) with metal posts on the bond pads (Figs. 14C and 29; 1240), the metal posts attached by solder joints to the plurality of bondable features (Id.; 210), wherein each of the solder joints comprise twice re-flown solder ([0039] points to the insertion of posts 1240 (metal posts) occurring before or during the solder reflow. It is thus considered obvious that insertion of the posts 1240 during the solder reflow would result in a three-step process comprising a first solder reflow step, an insertion step, and finally a second solder reflow step resulting in a final stack 210 (solder joint).).
Regarding claim 24, Uzoh teaches encapsulating the IC die with a mold compound except for at least an exposed bottom contact to the plurality of lead terminals ([0092] points to forming an encapsulant (molding compound) over the structures 110B/110C (IC die). It is considered obvious that the bottom contact of the IC die would remain exposed from the mold compound in order to avoid destroying the connections between the structures 110B/110C (IC die) and 110A (package substrate).).
Claim(s) 11 and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Uzoh in further view of Iijima (US Patent No. 12383987).
Regarding claim 11, Iijima teaches wherein the solder joint has a void density of less than or equal to (≤) 5% of a cross-sectional area of the solder joint (Claim 1 points to a solder alloy wherein an average value of an area ratio of void generated at a solder joint interface is 10% or less. In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).). Thus, it would have been obvious to a person of ordinary skill in the art (POSITA) prior to the filing date of the claimed invention to combine the teachings of Uzoh and Iijima, such that the solder joint has a void density of less than or equal to (≤) 5% of a cross-sectional area of the solder joint in order to create a solder joint/bonded interface that exhibits a high tensile strength.
Regarding claim 22, Iijima teaches wherein each solder joint has a void density of less than or equal to (≤) 5% of a cross-sectional area of the solder joint (Claim 1 points to a solder alloy wherein an average value of an area ratio of void generated at a solder joint interface is 10% or less. In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Uzoh and Iijima, such that the solder joint has a void density of less than or equal to (≤) 5% of a cross-sectional area of the solder joint in order to create a solder joint/bonded interface that exhibits a high tensile strength.
Claim(s) 13 is rejected under 35 U.S.C. 103 as being unpatentable over Uzoh in further view of Wu (PGPub No. 20190393186).
Regarding claim 13, Wu teaches flux dipping to add a flux dip over the metal posts before the flip chip die attaching (Fig. 5 and [0029] point to an application of flux over a copper post 12/12’ prior to a bonding operation.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Uzoh and Takahashi, such that a flux dipping is performed prior to flip chip die attaching in order to help mitigate oxidation of solders during the solder reflow process.
Claim(s) 16-17, 25-26, and 29 are rejected under 35 U.S.C. 103 as being unpatentable over Uzoh in further view of Takahashi (PGPub No. 20090291524).
Regarding claim 16, Takahashi teaches wherein the package substrate comprises a leadframe, and wherein the leadframe comprises a leadless leadframe (Fig. 5 and [0025] point to the package substrate 519 being a QFN (leadless leadframe).). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Uzoh and Takahashi, such that the package substrate comprises a leadless leadframe in order to create a package substrate with a lower profile, improved thermal performance, and/or shorter electrical pathways.
Regarding claim 17, Takahashi teaches wherein the package substrate comprises a multilayer organic substrate (Fig. 5 and [0025] point to the package substrate 519 being a polyimide substrate (multilayer organic substrate).). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Uzoh and Takahashi, such that the package substrate comprises a multilayer organic substrate in order to greatly increase I/O capability and/or routing density.
Regarding claim 25, Uzoh teaches a method of making a semiconductor device assembly, comprising: providing a package substrate having a top side including a plurality of bondable features (Fig. 29; 110A, 120A); and providing at least one integrated circuit (IC) die comprising a substrate including at least a semiconductor surface having circuitry configured for realizing at least one function including nodes (Id.; 110B) coupled to bond pads (Fig. 14C; 120B) with metal posts on the bond pads (Figs. 14C and 29; 1240), the metal posts attached by solder joints to the plurality of bondable features (Id.; 210), wherein the solder joints comprise twice re-flown solder ([0039] points to the insertion of posts 1240 (metal posts) occurring before or during the solder reflow. It is thus considered obvious that insertion of the posts 1240 during the solder reflow would result in a three-step process comprising a first solder reflow step, an insertion step, and finally a second solder reflow step resulting in a final stack 210 (solder joint).).
Uzoh fails to teach wherein the package substrate is a multilayer organic package substrate.
Takahashi teaches wherein the package substrate is a multilayer organic package substrate (Fig. 5 and [0025] point to the package substrate 519 being a polyimide substrate (multilayer organic substrate).). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Uzoh and Takahashi, such that the package substrate is a multilayer organic package substrate in order to greatly increase I/O capability and/or routing density.
Regarding claim 26, Uzoh teaches wherein the metal posts comprise copper pillars ([0039]; 1240).
Regarding claim 29, Uzoh teaches encapsulating the IC die with a mold compound except for at least an exposed bottom contact to the plurality of lead terminals ([0092] points to forming an encapsulant (molding compound) over the structures 110B/110C (IC die). It is considered obvious that the bottom contact of the IC die would remain exposed from the mold compound in order to avoid destroying the connections between the structures 110B/110C (IC die) and 110A (package substrate).).
Claim(s) 19 is rejected under 35 U.S.C. 103 as being unpatentable over Uzoh in further view of Yang (US Patent No. 10700011).
Regarding claim 19, Yang teaches wherein the flip chip die attaching further comprises attaching at least one passive device selected from a resistor, capacitor, and an inductor positioned lateral to the plurality of bondable features (Fig. 2C; 162). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Uzoh and Takahashi, such that at least one passive device is further formed in order to form a system-in-package module that offers higher density and enhanced electrical functionality relative to traditional semiconductor packaging.
Claim(s) 23 is rejected under 35 U.S.C. 103 as being unpatentable over Uzoh in further view of Shigeta (PGPub No. 20220087018).
Regarding claim 23, Shigeta teaches wherein each of the solder joints comprise a lead-free alloy that contains 96.5% tin, 3% silver, and 0.5% copper ([0057]). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Uzoh and Shigeta, such that each solder joint contains 96.5% tin, 3% silver, and 0.5% copper in order to create a solder alloy/solder joint exhibiting good melting behavior, mechanical reliability, and/or electrical conductivity.
Claim(s) 27 is rejected under 35 U.S.C. 103 as being unpatentable over Uzoh et al. in further view of Iijima (US Patent No. 12383987).
Regarding claim 27, Iijima teaches wherein each solder joint has a void density of less than or equal to (≤) 5% of a cross-sectional area of the solder joint (Claim 1 points to a solder alloy wherein an average value of an area ratio of void generated at a solder joint interface is 10% or less. In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Uzoh et al. and Iijima, such that the solder joint has a void density of less than or equal to (≤) 5% of a cross-sectional area of the solder joint in order to create a solder joint/bonded interface that exhibits a high tensile strength.
Claim(s) 28 is rejected under 35 U.S.C. 103 as being unpatentable over Uzoh et al. in further view of Shigeta (PGPub No. 20220087018).
Regarding claim 28, Shigeta teaches wherein each of the solder joints comprise a lead-free alloy that contains 96.5% tin, 3% silver, and 0.5% copper ([0057]). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Uzoh et al. and Shigeta, such that each solder joint contains 96.5% tin, 3% silver, and 0.5% copper in order to create a solder alloy/solder joint exhibiting good melting behavior, mechanical reliability, and/or electrical conductivity.
Conclusion
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/PATRICK CULLEN/ Assistant Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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