DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 12-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 7/2/26.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-4 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more. The claims recite a method of determining a number of timer entries in a group and then accessing multiple groups of timer entries to determine whether any timer entries in the groups have expired.
The limitations of determining a number of timer entries in a group and then accessing multiple groups of timer entries to determine whether any timer entries in the groups of entries have expired, as drafted, is a process that, under its broadest reasonable interpretation, covers performance of the limitation in the mind but for the recitation of generic computer components. That is, other than reciting “an application processor core” (Claims 3 and 4), nothing in the claim elements precludes the steps from practically being performed in the mind. For example, but for the “application processor core” language, “determining” and “accessing” in the context of these claims encompasses the user manually reading (“accessing”) and identifying (“determining”) which timer entries in the various groups have expired. If a claim limitation, under its broadest reasonable interpretation, covers performance of the limitation in the mind but for the recitation of generic computer components, then it falls within the “Mental Processes” grouping of abstract ideas. Accordingly, the claim recites an abstract idea.
This judicial exception is not integrated into a practical application. In particular, the claims only recite two additional elements – receiving an instruction from an application processor core that specifies the first number of timer entries and the second number of timer entries (Claim 3) and resetting the first number of timer entries and the second number of timer entries in response to an instruction from an application processor core (Claim 4). The application processor core in these steps is recited at a high-level of generality (i.e., as a generic application processor core performing a generic computer function of transmitting an instruction) such that it amounts no more than mere instructions to apply the exception using a generic computer component. Accordingly, these additional elements do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea. The claims are directed to an abstract idea.
The claims do not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements of using a processor to transmit the instruction that specifies the number of timer entries and resetting the numbers of timer entries steps amount to no more than mere instructions to apply the exception using a generic computer component. Mere instructions to apply an exception using a generic computer component cannot provide an inventive concept. The claims are not patent eligible.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Bar et al. (U.S. Patent Application Publication Number 2017/0017260).
Regarding Claim 1, Bar discloses a method comprising:
determining a number of timer entries in a first group of timer entries (Figure 6, items 601 and 602, paragraph 0039; i.e., by recording a list of timer IDs that have been allocated, the timer manager 106 would be able to determine the number of timer entries in each timer ring);
accessing a first subset of the first group of timer entries containing the number of timer entries (Figure 6, item 601, paragraph 0042);
determining whether any of the first subset of the first group of timer entries corresponds to a timer expiration (Figure 4, item 404, paragraph 0042); and
after the accessing of the first subset of the first group of timer entries:
accessing a timer entry of a second group of timer entries (Figure 6, items 603 and 604, paragraph 0053; i.e., the TEC component 214 cycles through each of the entries of each timer ring); and
determining whether the timer entry of the second group of timer entries corresponds to a timer expiration (Figure 4, item 404, paragraphs 0042-0043; i.e., the steps shown in Figure 4 are repeated for every group of timer entries 601-604); and
after the accessing of the timer entry of the second group of timer entries:
accessing a second subset of the first group of timer entries containing the number of timer entries (Figure 6, item 602, paragraphs 0053-0054); and
determining whether any of the second subset of the first group of timer entries corresponds to a timer expiration (Figure 4, item 404, paragraphs 0042 and 0053-0054).
Regarding Claim 2, Bar discloses wherein the number of timer entries is a first number of timer entries (Figure 6, item 601); and the method further comprises: determining a second number of timer entries in the second group of timer entries (Figure 6, items 603 and 604, paragraph 0039; i.e., by recording a list of timer IDs that have been allocated, the timer manager 106 would be able to determine the number of timer entries in each timer ring); and accessing a subset of the second group of timer entries that contains the second number of timer entries between each access of a third group of timer entries (Figure 1, paragraph 0051; i.e., there may any number of timer rings, and therefore, there may be a third group of timer entries shown in Figure 6).
Regarding Claim 3, Bar discloses receiving an instruction from an application processor core (Figure 1, item 110, paragraph 0026) that specifies the first number of timer entries and the second number of timer entries (paragraph 0030).
Regarding Claim 4, Bar discloses resetting the first number of timer entries and the second number of timer entries in response to an instruction from an application processor core (paragraph 0028).
Regarding Claim 5, Bar discloses storing the timer entries of the first group of timer entries to first respective address ranges within a memory (Figure 2, item 104) and storing the timer entries of the second group of timer entries to second respective address range within the memory (Figure 1, paragraph 0027; i.e., the groups of timer entries 131-133 are stored in different areas of the memory 104, which indicates that different memory address ranges are used for the different timer rings).
Regarding Claim 6, Bar discloses wherein determining whether a given timer entry of either the first group of timer entries or the second group of timer entries corresponds to a timer expiration comprises: comparing a first value, stored within the given timer entry, to a value of a counter (paragraph 0032); and determining whether the given timer entry corresponds to a timer expiration based upon the comparing (Figure 2, paragraph 0032; i.e., comparing the current timer value with the value of the corresponding master wall clock 231-233).
Regarding Claim 7, Bar discloses in response to determining that the given timer entry corresponds to a timer expiration, transmitting a function pointer to a processor scheduler (Figure 2, item 212) and transmitting a function argument to the processor scheduler (paragraph 0043; i.e., the “function pointer” being the ID of the timer owner and the “function argument” being that the particular timer [using an timer ID] has expired).
Regarding Claim 8, Bar discloses in response to determining that the given timer entry corresponds to a timer expiration, and in response to determining that the given timer entry is identified as a periodic timer entry (paragraph 0019), modifying the first value (paragraph 0032; i.e., the timer value [the “first value”] is reset [“modified”] upon the periodic timer expiring).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Bar as applied to Claim 6, and further in view of Aggarwal (U.S. Patent Application Publication Number 2023/0251900).
Regarding Claim 9, Bar discloses in response to determining that the given timer entry corresponds to a timer expiration, transmitting a function pointer to a processor scheduler and transmitting a function argument to the processor scheduler (paragraph 0043; i.e., the “function pointer” being the ID of the timer owner and the “function argument” being that the particular timer [using an timer ID] has expired).
Bar does not expressly disclose using either a first buffer or a second buffer based on whether the given timer entry is indicated as being a real time (RT) timer entry or a non-real time (non-RT) timer entry.
In the same field of endeavor (e.g., timer management techniques), Aggarwal teaches using either a first buffer or a second buffer based on whether the given timer entry (paragraph 0010) is indicated as being a real time (RT) timer entry (paragraph 0059) or a non-real time (non-RT) timer entry (paragraph 0111).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined Aggarwal’s teachings of timer management techniques with the teachings of Bar, for the purpose of ensuring that higher priority timer events are transmitted to the requestor faster than a lower priority timer event.
Claims 10 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Bar as applied to Claim 1, and further in view of Gately et al. (U.S. Patent 12,153,542).
Regarding Claim 10, Bar discloses receiving data from an application processor core (paragraph 0026), wherein the data indicates a plurality of values of a new timer entry (paragraphs 0028 and 0036; i.e., a timer ID and a requested timer duration); and storing the new timer entry to a memory (Figure 1, item 104), in a range of addresses associated with the first group of timer entries, wherein the new timer entry includes values based on the data (Figure 1, paragraph 0027; i.e., the groups of timer entries 131-133 are stored in different areas of the memory 104, which indicates that different memory address ranges are used for the different timer rings; each timer entry is stored based on a timer ID and the requested timer duration [e.g., hours, minutes, or seconds]).
Bar does not expressly disclose a memory managed register (MMR).
In the same field of endeavor (e.g., timer management techniques), Gately teaches a memory managed register (MMR) (Column 23, lines 12-18).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined Gately’s teachings of timer management techniques with the teachings of Bar, for the purpose of providing software simplicity: the CPU uses standard memory operations (e.g., standard C pointers or LOAD/STORE instructions) to control both RAM and peripherals, entirely bypassing the need for specialized I/O instructions.
Regarding Claim 11, Bar discloses receiving data from an application processor core (paragraph 0026), wherein the data indicates an index (i.e., a timer ID) of an existing timer entry, of the first group of timer entries, to be deleted (paragraph 0028; i.e., a requestor can cause early termination of a timer); storing a second value in the existing timer entry, wherein the second value indicates that the existing timer entry is free (paragraphs 0028 and 0046; i.e., the particular timer ID can be indicated as a free timer ID and thus may be reallocated).
Bar does not expressly disclose a memory managed register (MMR).
In the same field of endeavor, Gately teaches a memory managed register (MMR) (Column 23, lines 12-18).
The motivation discussed above with regards to Claim 10 applies equally as well to Claim 11.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure because each reference discloses a method for identifying expired timer entries by a timer manager.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FAISAL M ZAMAN whose telephone number is (571)272-6495. The examiner can normally be reached Monday - Friday, 8 am - 5 pm, alternate Fridays.
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/FAISAL M ZAMAN/ Primary Examiner, Art Unit 2175
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