DETAILED ACTION
This Office Action is in response to the application 18/902,704 filed on September 30th, 2024.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 1-20 are pending and herein considered.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS), submitted on 11/22/2024, is in compliance with the provisions of 37 CRR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-20 are rejected under 35 U.S.C. 101 as being directed to non-statutory subject matter.
Regarding claims 1, 11 and 20; claims 1, 11 and 20 are/is rejected under 35 USC 101 because the claims are/is directed to an abstract idea without being integrated into a practical application nor being significantly more.
The claims reciting the limitations “stor[ing] a first representation of an input data” and “perform[ing] a non-linear mapping of the first representation of the input data to a second representation of the input data” are directed to an abstract idea as the claims recite mental processes. Accordingly, the claims recite an abstract idea. This judicial exception is not integrated into a practical application. It’s noted that the claims recite additional element(s) (i.e, one or more first circuits, plurality of registers). However, said additional element is recited at a high-level of generality (i.e., as a generic processor performing a generic computer function of storing/performing) such that it amounts no more than mere instructions to apply the exception using a generic computer component. Accordingly, this additional element does not integrate the abstract idea into a practical application because it does not impose any meaningful limits on practicing the abstract idea. Therefore, the claims are not integrated into a practical application.
The claims do not include additional elements that are sufficient to amount to significantly more than the judicial exception because the additional elements when considered both individually and as an ordered combination do not amount to significantly more than the abstract idea. As mentioned above, although the claims recite additional element, said element taken individually or as a combination, do not result in the claim amounting to significantly more than the abstract idea because as the additional elements perform generic computer content distributing functions routinely used in information technology field. Performing a non-linear mapping of the first representation of the input data to a second representation of the input data is conventional, well know routing in view of Berkeeimer memo here. Generic computer components recited as performing generic computer functions that are well understood, routine and conventional activities amount to no more than implementing the abstract idea with a computerized system. Therefore, the claim is directed to non-statutory subject matter.
Regarding claims 2-10 & 12-19; claims 2-10 & 12-19 are also rejected under 35 U.S.C 101 as being directed to non-statutory subject matter for the same reasons addressed above as the claims are directed to abstract idea without being integrated into a practical application nor being significantly more.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shu et al. (Shu), U.S. Pub. Number 2012/0144205.
Regarding claim 1; Shu discloses a processing device comprising:
a plurality of registers (par. 0039; a plurality of registers.);
one or more first circuits (par. 0128; the circuit is independent of the data value content of the ALU register bit.) to store, in the plurality of registers:
a first representation of an input data into a cryptographic operation (par. 0129; an on-chip bus or chip architecture of a microprocessor that is used to perform cryptographic operations.), and
a dummy data (par. 0117; a dummy register in that it receives and stores data.),
wherein the first representation of the input data and the dummy data are stored in an order that is determined responsive to an input selector having at least a first value or a second value (par. 0127; the CPU Read and CPU Write lines are used to control the data flow direction; the bi-directional bus drivers 315, 317 are inverting or non-inverting tri-state buffers determined by the value of the associated random bit 3140 – 314N if the random number generated by random generator 313; For instance, when the random bit 3140 is “0” for bi-directional bus driver 315 during a CPU Write operation, the signal at 3050 will be inverted on the data bus 316; at the other end, bi-directional bus driver 317 will pick up the inverted signal from the data bus 316 for bit 3050 and invert the bit again to ensure the integrity of the original data signal.); and
one or more second circuits to perform a non-linear mapping of the first representation of the input data to a second representation of the input data (par. 0129; enable securing existing cryptographic algorithms including RSA, DES, AES and non-linear algorithms.).
Regarding claim 2; Shu discloses the processing device of claim 1, wherein the input data into the cryptographic operation comprises a plaintext message and a cryptographic key associated with the cryptographic operation, and wherein the first representation of the input data comprises a first share of the plaintext message and a second share of the plain text message, wherein the first share of the plaintext message comprises a random number (par. 0126; the N-bit random number generator controls the N-bit bi-directional drivers; the random number generator has N outputs, wherein each output comprises of one bit; each bit controls one bus driver; the random number generator generates a new set of N-bit random numbers whenever an activate signal is received from the CPU through the enable line; the required polarity changes are infrequent enough to thwart the statistical analysis by a reverse engineer; the polarity can be changed at the beginning of each DES round, or at the beginning of fetching each new plaintext for encryption.).
Regarding claim 3; Shu discloses the processing device of claim 1, wherein responsive to the input selector having the first value, the one or more first circuits are to: at a first clock cycle: store a first set of dummy data in data registers of the plurality of registers, and at a second clock cycle: overwrite the first set of dummy data in the data registers with the first representation of the input data (par. 0072; an encryption algorithm is a series of instructions executed by a processor; while the inputs and outputs of these instructions will vary, the amount of time required to complete each instruction is determined by the clock speed of the processor or a bus over which the data is transmitted to and from the processor; different instructions take more clock cycles than other instructions; the knowledge of the encryption algorithm used to encrypt/decrypt the data provides hackers with knowledge about the timing of the algorithm, knowledge about which instruction are used and how long each instruction should take.).
Regarding claim 4; Shu discloses the processing device of claim 3, wherein responsive to the input selector having the first value, the one or more first circuits are further to: at the first clock cycle: store a second set of dummy data in key registers of the plurality of registers, and at the second clock cycle: overwrite the second set of dummy data in the key registers with a representation of a key associated with the cryptographic operation (par. 0087; the random number generator may provide an output every clock cycle, or may be gated to ensure that an output is provided to the RIM Control Flag Register after a random number of X cycles, where X is any number such as 5; for a one-bit Random Number Generator, the RIM Control Flag Register is programmed to reset when either a zero or one is received from the one-bit Random Number Generator depending upon the logic used.).
Regarding claim 5; Shu discloses the processing device of claim 4, wherein the one or more first circuits are further to: at a third clock cycle: combine the first representation of the input data with the representation of the key associated with the cryptographic operation (par. 0087; the random number generator may provide an output every clock cycle, or may be gated to ensure that an output is provided to the RIM Control Flag Register after a random number of X cycles, where X is any number such as 5; for a one-bit Random Number Generator, the RIM Control Flag Register is programmed to reset when either a zero or one is received from the one-bit Random Number Generator depending upon the logic used.).
Regarding claim 6; Shu discloses the processing device of claim 1, wherein responsive to the input selector having the second value, the one or more first circuits are to: at a first clock cycle: store the first representation of the input data in data registers of the plurality of registers, and at a second clock cycle: store the dummy data in stage status registers of the plurality of registers (par. 0121; a processor may have additional status flag registers that should not be updated when running in RIM mode; the control such registers may be modified in the same way as the registers (by providing dummy flag registers – analogous to extra register – for writing results to when in RIM mode) resulting in a duplicated power signature component for updating these flags registers without really updating them; these flag registers are not depicted for purpose of simplicity.).
Regarding claim 7; Shu discloses the processing device of claim 6, wherein responsive to the input selector having the second value, the one or more first circuits are further to: at the first clock cycle: store a representation of a key associated with the cryptographic operation in key registers of the plurality of registers (par. 0124; the result is that within each group of messages having the same target bit values computed from the selection function with correctly guessed key KS, the corresponding power traces will not be always “0” or “1”; the chance of having “0” or “1” at the target bit will be appropriately at 0.5 due to the randomization of polarity; the section function D is effectively uncorrelated to the actual power trace measurement.).
Regarding claim 8; Shu discloses the processing device of claim 1, wherein the one or more first circuits comprise: an XOR circuit to receive the input data and a random value to generate a portion of the first representation of the input data (par. 0023; the eight SP boxes each take, as input, a scrambled 6-bit key (here, scrambled means that the key has been XOR-ed and shifted) and produce a 4-bit output target to be accessed by the CPU for OR-ing operations; each such 6-bit scrambled is an SP box’s entry address.); and a multiplexer to receive: a first signal representative of the dummy data, a second signal representative of the portion of the first representation of the input data, and a control signal representative of the input selector, wherein the multiplexer is configured to output at least one of: the first signal, responsive to the input selector having the first value, or the second signal, responsive to the input selector having the second value (par. 0042; a dummy register for receiving output of the arithmetic logic unit, in lieu of one of the plurality of registers in response to an instruction and in response to a second state of said control flag register.).
Regarding claim 9; Shu discloses the processing device of claim 1, wherein the non-linear mapping of the first representation of the input data to the second representation of the input data comprises a substitution box of the cryptographic operation (par. 0010; substitution box (S-Box) functions are non-linear and can be implemented by using table lookups, Boolean logic or appropriately programmed computers.).
Regarding claim 10; Shu discloses the processing device of claim 1, wherein the one or more second circuits are further to perform multiple iterations of a substitution box (S-Box) of the cryptographic operation (par. 0010; substitution box (S-Box) functions are non-linear and can be implemented by using table lookups, Boolean logic or appropriately programmed computers.), wherein each iteration comprises a plurality of parallel stages of the S-Box, at least one of the plurality of parallel stages of the S-Box computing inconsequential data (par. 0120; a pipelined ALU has four stages: prefetch, instruction decode, execute, and writeback; the RIM control signal from the RIM flags may be synchronized with the pipeline through a delay circuit.).
Regarding claim 11; Claim 11 is directed to a method which has similar scope as claim 1. Therefore, claim 11 remains un-patentable for the same reasons.
Regarding claims 12-19; Claims 12-19 are directed to the method of claim 11 which have similar scope as claims 2-10. Therefore, claims 12-19 remain un-patentable for the same reasons.
Regarding claim 20; Claim 20 is directed to a system which has similar scope as claim 1. Therefore, claim 20 remains un-patentable for the same reasons.
Conclusion
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/KHOI V LE/
Primary Examiner, Art Unit 2436