CTNF 18/903,010 CTNF 81768 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Objections 07-29-01 AIA Claim 11 is objected to because of the following informalities: in the last line replace the semicolon with a period to signify the end of the claim . Appropriate correction is required. Double Patenting 08-33 AIA The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg , 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman , 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi , 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum , 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel , 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington , 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA/25, or PTO/AIA/26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer . Applicant is advised that this Double Patenting rejection will not be held in abeyance. See MPEP § 804(I)(B)(1); 37 CFR § 1.111(b). 08-34 AIA Claim s 1-17 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim s 1-13 of U.S. Patent No. 12,135,676 . Although the claims at issue are not identical, they are not patentably distinct from each other because all of the features of the instant claims can be found in the conflicting claims, and thus are anticipated by those claims . Instant Claims Claims of U.S. Patent Number 12,135,676 1. A serial bus repeater, comprising: a port circuit configured to communicate via a serial bus; and a low power state detection circuit, comprising: a power state transaction identification circuit; and a bus state identification circuit; wherein the power state transaction identification circuit comprises a packet timer circuit; wherein the power state transaction identification circuit comprises a packet sequence identification circuit coupled to the packet timer circuit. 1. A serial bus repeater, comprising: a port circuit configured to receive and retransmit one or more packets for a downstream device coupled to a serial bus; and a power state identification circuit coupled to the port circuit, the power state identification circuit comprising: a power state transaction identification circuit configured to identify the one or more received and retransmitted packets as a potential power state transaction which requests the downstream device to transition to a reduced power state; and a bus state identification circuit configured to, responsive to the power state identification circuit identifying the received and retransmitted one or more packets as the potential power state transaction, measure a termination resistance on the serial bus to confirm the transition of the downstream device to the reduced power state; wherein the power state transaction identification circuit comprises a packet timer circuit configured to measure durations of packets on the serial bus; wherein the power state transaction identification circuit comprises a packet sequence identification circuit coupled to the packet timer circuit and configured to identify a series of sequential packets on the serial bus, wherein each of the sequential packets has a duration indicative of the power state transaction. 2. The serial bus repeater of claim 1, wherein the low power state detection circuit is configured to trigger the bus state identification circuit to measure the termination resistance on the serial bus responsive to the power state transaction identification circuit identifying the power state transaction on the serial bus. 11. A circuit comprising: a control circuit; a power state transaction identification circuit coupled to the control circuit, the power state transaction identification circuit configured to identify one or more received and retransmitted packets as a potential power state transaction which requests a downstream device coupled to a serial bus to transition to a reduced power state, and the power state transaction identification circuit is configured to notify the control circuit of the potential power state transaction; a bus state identification circuit coupled to the control circuit, wherein the control circuit is configured to, responsive to receiving the notification of the potential power state transaction, trigger the bus state identification circuit to measure a termination resistance on the serial bus to confirm the transition by the downstream device to the reduced power state; and a port circuit coupled to the power state transaction identification circuit and to the bus state identification circuit; wherein the port circuit comprises: a differential receiver having a first receiver input, a second receiver input, and a receiver output; a first resistor having a first resistor terminal and a second resistor terminal, the first resistor terminal coupled to the first receiver input; and a second resistor having a third resistor terminal and a fourth resistor terminal, the third resistor terminal coupled to the second receiver input and the fourth resistor terminal coupled to the second resistor terminal. 3. The serial bus repeater of claim 1, wherein the packet timer circuit is configured to measure a duration of each packet on the serial bus. 1. A serial bus repeater, comprising: a port circuit configured to receive and retransmit one or more packets for a downstream device coupled to a serial bus; and a power state identification circuit coupled to the port circuit, the power state identification circuit comprising: a power state transaction identification circuit configured to identify the one or more received and retransmitted packets as a potential power state transaction which requests the downstream device to transition to a reduced power state; and a bus state identification circuit configured to, responsive to the power state identification circuit identifying the received and retransmitted one or more packets as the potential power state transaction, measure a termination resistance on the serial bus to confirm the transition of the downstream device to the reduced power state; wherein the power state transaction identification circuit comprises a packet timer circuit configured to measure durations of packets on the serial bus; wherein the power state transaction identification circuit comprises a packet sequence identification circuit coupled to the packet timer circuit and configured to identify a series of sequential packets on the serial bus, wherein each of the sequential packets has a duration indicative of the power state transaction. 4. The serial bus repeater of claim 3, wherein the packet sequence identification circuit is configured to identify a series of sequential packets on the serial bus, wherein each of the sequential packets has a duration indicative of the power state transaction. 1. A serial bus repeater, comprising: a port circuit configured to receive and retransmit one or more packets for a downstream device coupled to a serial bus; and a power state identification circuit coupled to the port circuit, the power state identification circuit comprising: a power state transaction identification circuit configured to identify the one or more received and retransmitted packets as a potential power state transaction which requests the downstream device to transition to a reduced power state; and a bus state identification circuit configured to, responsive to the power state identification circuit identifying the received and retransmitted one or more packets as the potential power state transaction, measure a termination resistance on the serial bus to confirm the transition of the downstream device to the reduced power state; wherein the power state transaction identification circuit comprises a packet timer circuit configured to measure durations of packets on the serial bus; wherein the power state transaction identification circuit comprises a packet sequence identification circuit coupled to the packet timer circuit and configured to identify a series of sequential packets on the serial bus, wherein each of the sequential packets has a duration indicative of the power state transaction. 5. The serial bus repeater of claim 4, wherein the series of sequential packets comprises: a first packet having a first predetermined duration; a second packet, immediately subsequent to the first packet, having the first predetermined duration; and a third packet, immediately subsequent to the second packet, having a second predetermined duration. 2. The serial bus repeater of claim 1, wherein the series of sequential packets comprises: a first packet having a first duration; a second packet, immediately subsequent to the first packet, having the first duration; and a third packet, immediately subsequent to the second packet, having a second duration. 6. The serial bus repeater of claim 1, wherein the port circuit comprises: a differential receiver; a first termination resistor coupled to a first differential input terminal of the differential receiver; and a second termination resistor coupled to a second differential input terminal of the differential receiver. 3. A serial bus repeater comprising: a port circuit configured to receive and retransmit one or more packets for a downstream device coupled to a serial bus; and a power state identification circuit coupled to the port circuit, the power state identification circuit comprising: a power state transaction identification circuit configured to identify the one or more received and retransmitted packets as a potential power state transaction which requests the downstream device to transition to a reduced power state; and a bus state identification circuit configured to, responsive to the power state identification circuit identifying the received and retransmitted one or more packets as the potential power state transaction, measure a termination resistance on the serial bus to confirm the transition of the downstream device to the reduced power state; wherein the port circuit comprises: a differential receiver; a first termination resistor coupled to a first differential input terminal of the differential receiver; and a second termination resistor coupled to a second differential input terminal of the differential receiver. 7. The serial bus repeater of claim 6, wherein the bus state identification circuit comprises: a switch coupled to the first termination resistor and the second termination resistor, and configured to selectably connect the first termination resistor and the second termination resistor to ground; a current source coupled to the first termination resistor and the second termination resistor; and a comparator coupled to the current source. 4. The serial bus repeater of claim 3, wherein the bus state identification circuit comprises: a switch coupled to the first termination resistor and the second termination resistor, and configured to selectably connect the first termination resistor and the second termination resistor to ground; a current source coupled to the first termination resistor and the second termination resistor; and a comparator coupled to the current source. 8. The serial bus repeater of claim 7, wherein the current source is configured to provide a current of approximately 20 microamperes. 5. The serial bus repeater of claim 4, wherein the current source is configured to provide a current of approximately 20 microamperes. 9. The serial bus repeater of claim 7, wherein the bus state identification circuit is configured to: open the switch responsive to the power state transaction identification circuit identifying the power state transaction on the serial bus; activate the current source responsive to opening the switch; and compare a voltage at the first termination resistor and the second termination resistor to a predetermined threshold voltage. 6. The serial bus repeater of claim 4, wherein the bus state identification circuit is configured to: open the switch responsive to the power state transaction identification circuit identifying the potential power state transaction on the serial bus; activate the current source responsive to opening the switch; and compare a voltage at the first termination resistor and the second termination resistor to a threshold voltage. 10. The serial bus repeater of claim 9, wherein: the predetermined threshold voltage is approximately 100 millivolts; and the bus state identification circuit is configured to close the switch responsive to the voltage at the first termination resistor and the second termination resistor being less than the predetermined threshold voltage. 7. The serial bus repeater of claim 6, wherein: the threshold voltage is approximately 100 millivolts; and the bus state identification circuit is configured to close the switch responsive to the voltage at the first termination resistor and the second termination resistor being less than the threshold voltage. 11. A method for identifying a reduced power state on a serial bus, comprising: identifying a power state transaction on the serial bus, wherein the power state transaction is indicative of entering the reduced power state; and identifying a value of termination resistance on the serial bus responsive to identifying the power state transaction, wherein the value of termination resistance is indicative of entering the reduced power state; wherein identifying the power state transaction comprises: measuring a duration of each packet on the serial bus; an identifying a series of sequential packets on the serial bus. 8. A method comprising: receiving and retransmitting one or more packets for a downstream device coupled to a serial bus; identifying the received and retransmitted one or more packets as a potential power state transaction which requests the downstream device to transition to a reduced power state; and measuring a termination resistance on the serial bus responsive to identifying the received and retransmitted one or packets as the potential power state transaction, wherein the termination resistance confirms the transition of the downstream device to the reduced power state; wherein identifying the received and retransmitted one or packets as the potential power state transaction comprises: measuring a duration of each packet on the serial bus; and identifying a series of sequential packets on the serial bus; wherein the series of sequential packets comprises: a first packet having a first duration; a second packet, immediately subsequent to the first packet, having the first duration; and a third packet, immediately subsequent to the second packet, having a second duration. 12. The method of claim 11, wherein the series of sequential packets comprises: a first packet having a first predetermined duration; a second packet, immediately subsequent to the first packet, having the first predetermined duration; and a third packet, immediately subsequent to the second packet, having a second predetermined duration. 8. A method comprising: receiving and retransmitting one or more packets for a downstream device coupled to a serial bus; identifying the received and retransmitted one or more packets as a potential power state transaction which requests the downstream device to transition to a reduced power state; and measuring a termination resistance on the serial bus responsive to identifying the received and retransmitted one or packets as the potential power state transaction, wherein the termination resistance confirms the transition of the downstream device to the reduced power state; wherein identifying the received and retransmitted one or packets as the potential power state transaction comprises: measuring a duration of each packet on the serial bus; and identifying a series of sequential packets on the serial bus; wherein the series of sequential packets comprises: a first packet having a first duration; a second packet, immediately subsequent to the first packet, having the first duration; and a third packet, immediately subsequent to the second packet, having a second duration. 13. The method of claim 11, wherein identifying the value of termination resistance comprises: opening a switch connecting a first termination resistor and a second termination resistor to ground; activating a current source to drive a current into the first termination resistor and the second termination resistor responsive to opening the switch; comparing a voltage at the first termination resistor and the second termination resistor to a threshold voltage; and deeming the reduced power state to be active based on the voltage exceeding the threshold voltage. 9. A method comprising: receiving and retransmitting one or more packets for a downstream device coupled to a serial bus; identifying the received and retransmitted one or more packets as a potential power state transaction which requests the downstream device to transition to a reduced power state; and measuring a termination resistance on the serial bus responsive to identifying the received and retransmitted one or packets as the potential power state transaction, wherein the termination resistance confirms the transition of the downstream device to the reduced power state; wherein measuring the termination resistance comprises: opening a switch connecting a first termination resistor and a second termination resistor to ground; activating a current source to drive a current into the first termination resistor and the second termination resistor responsive to opening the switch; comparing a voltage at the first termination resistor and the second termination resistor to a threshold voltage; and deeming the reduced power state to be active based on the voltage exceeding the threshold voltage. 14. The method of claim 13, wherein: the current is approximately 20 microamperes; and the threshold voltage is approximately 100 milliamperes. 10. The method of claim 9, wherein: the current is approximately 20 microamperes; and the threshold voltage is approximately 100 milliamperes. 15. A circuit comprising: a control circuit; a power state transaction identification circuit coupled to the control circuit; a bus state identification circuit coupled to the control circuit; and a port circuit coupled to the power state transaction identification circuit and to the bus state identification circuit; wherein the port circuit comprises: a differential receiver having a first receiver input, a second receiver input, and a receiver output; a first resistor having a first resistor terminal and a second resistor terminal, the first resistor terminal coupled to the first receiver input; and a second resistor having a third resistor terminal and a fourth resistor terminal, the third resistor terminal coupled to the second receiver input and the fourth resistor terminal coupled to the second resistor terminal. 11. A circuit comprising: a control circuit; a power state transaction identification circuit coupled to the control circuit, the power state transaction identification circuit configured to identify one or more received and retransmitted packets as a potential power state transaction which requests a downstream device coupled to a serial bus to transition to a reduced power state, and the power state transaction identification circuit is configured to notify the control circuit of the potential power state transaction; a bus state identification circuit coupled to the control circuit, wherein the control circuit is configured to, responsive to receiving the notification of the potential power state transaction, trigger the bus state identification circuit to measure a termination resistance on the serial bus to confirm the transition by the downstream device to the reduced power state; and a port circuit coupled to the power state transaction identification circuit and to the bus state identification circuit; wherein the port circuit comprises: a differential receiver having a first receiver input, a second receiver input, and a receiver output; a first resistor having a first resistor terminal and a second resistor terminal, the first resistor terminal coupled to the first receiver input; and a second resistor having a third resistor terminal and a fourth resistor terminal, the third resistor terminal coupled to the second receiver input and the fourth resistor terminal coupled to the second resistor terminal. 16. The circuit of claim 15, therein the bus state identification circuit further comprises: a current source having a current input and a current output, the current output coupled to the second resistor terminal and to the fourth resistor terminal and the current input coupled to the control circuit; a switch having a first switch terminal, a second switch terminal, and a control terminal, the first switch terminal coupled to the second resistor terminal and to the fourth resistor terminal and the control terminal coupled to the control circuit; and a comparator having a first comparator input, a second comparator input, and a comparator output, the first comparator input coupled to the current output. 12. The circuit of claim 11, therein the bus state identification circuit further comprises: a current source having a current input and a current output, the current output coupled to the second resistor terminal and to the fourth resistor terminal and the current input coupled to the control circuit; a switch having a first switch terminal, a second switch terminal, and a control terminal, the first switch terminal coupled to the second resistor terminal and to the fourth resistor terminal and the control terminal coupled to the control circuit; and a comparator having a first comparator input, a second comparator input, and a comparator output, the first comparator input coupled to the current output. 17. The circuit of claim 15, further comprising a host coupled to the port circuit by the serial bus. 13. The circuit of claim 11, further comprising a host coupled to the port circuit by the serial bus . Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim s 1, 3, and 6-10 are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (U.S. Patent Application Publication Number 2019/0288743) and Cohn (U.S. Patent Number 9,729,350) . Regarding Claim 1 , Wang discloses a serial bus repeater (Figure 1, item 108, paragraph 0030) comprising: a port circuit configured to communicate via a serial bus (Figure 2, item 212, paragraph 0038); and a low power state detection circuit (paragraphs 0045-0046) comprising: a power state transaction identification circuit (paragraph 0071; i.e., receiving one or more signals from biasing control logic 328, such as an indication that the current-mode circuitry is in a low-power state, e.g., the U3 state); and a bus state identification circuit (paragraph 0071; i.e., tri-state control logic 324 detects the presence of the LFPS and controls the tri-state devices to exit high impedance mode). Wang does not expressly disclose wherein the power state transaction identification circuit comprises a packet timer circuit; wherein the power state transaction identification circuit comprises a packet sequence identification circuit coupled to the packet timer circuit. In the same field of endeavor (e.g., bus transaction detection techniques), Cohn teaches wherein the power state transaction identification circuit comprises a packet timer circuit (Column 6, lines 59-62); wherein the power state transaction identification circuit comprises a packet sequence identification circuit coupled to the packet timer circuit (Column 5, lines 57-61 and Column 6, lines 10-16; i.e., the “power state transaction identification circuit” receives packets that contain a sequence number and start the packet timer circuit if a packet is received out of order). Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined Cohn’s teachings of bus transaction detection techniques with the teachings of Wang, for the purpose of ensuring that data is received in the order that it was intended to be received, thereby preventing incorrect data from being processed at certain times. Regarding Claim 3 , Cohn teaches wherein the packet timer circuit is configured to measure a duration of each packet on the serial bus (Column 6, lines 32-35; i.e., a packet could be delayed in transit; the packet timer circuit measures this delay in receiving an expected packet, which is equivalent to the claimed “duration of each packet”). Regarding Claim 6 , Wang discloses wherein the port circuit comprises: a differential receiver (Figure 3, item 324); a first termination resistor (Figure 3, item R1) coupled to a first differential input terminal of the differential receiver (i.e., indirectly coupled to the input terminal of receiver 324); and a second termination resistor (Figure 3, item R2) coupled to a second differential input terminal of the differential receiver (i.e., indirectly coupled to the input terminal of receiver 324). Regarding Claim 7 , Wang teaches wherein the bus state identification circuit comprises a switch coupled to the first termination resistor and the second termination resistor (Figure 3, items 310 and 312), and configured to selectably connect the first termination resistor and the second termination resistor to ground (Figure 3, item 302); a current source coupled to the first termination resistor and the second termination resistor (Figure 3, item 322); and a comparator coupled to the current source (Figure 3, item 326). Regarding Claim 8 , Wang does not expressly disclose wherein the current source (Figure 3, item 322) is configured to provide a current of approximately 20 microamperes, however it would have been obvious to one of ordinary skill in the art to have provided 20 microamperes since it has been held that discovering the optimum or workable ranges involves only routine skill in the art and doing so would result in a functional device with minimal power usage [ see In re Aller , 220 F.2d 454, 456 (CCPA 1955)]). Regarding Claim 9 , Wang teaches wherein the bus state identification circuit is configured to: open the switch responsive to the power state transaction identification circuit identifying the power state transaction on the serial bus; activate the current source responsive to opening the switch; and compare a voltage at the first termination resistor and the second termination resistor to a predetermined threshold voltage (paragraph 0051). Regarding Claim 10 , Wang teaches wherein the predetermined threshold voltage is approximately 100 millivolts; and the bus state identification circuit is configured to close the switch responsive to the voltage at the first termination resistor and the second termination resistor being less than the predetermined threshold voltage (paragraph 0054) . 07-22-aia AIA Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Wang and Cohn as applied to claim 1 above, and further in view of Bruennert et al. (U.S. Patent Application Publication Number 2010/0030934) . Regarding Claim 2 , Wang and Cohn do not expressly disclose wherein the low power state detection circuit is configured to trigger the bus state identification circuit to measure the termination resistance on the serial bus responsive to the power state transaction identification circuit identifying the power state transaction on the serial bus. In the same field of endeavor (e.g., power conservation techniques), Bruennert teaches wherein the low power state detection circuit is configured to trigger the bus state identification circuit to measure the termination resistance (Figure 3, item 228, paragraph 0036; i.e., the resistance of each termination resistor 228 is determined based upon information received from the transmission control bus 214, which equivalent to the claimed “measuring” step) on the serial bus responsive to the power state transaction identification circuit identifying the power state transaction on the serial bus (paragraphs 0033-0034; i.e., the resistance value of termination resistor 228 is identified and adjusted responsive to the mode that the DRAM is operating in, which may be idle or powered down [paragraphs 0025 and 0065; either of which are equivalent to the claimed “low power state”]; the controller 204 confirms that the particular DRAM module 202 is in the low power state by reading the termination resistance value on the transmission control bus 214). Accordingly, it would have been obvious to one of ordinary skill in the art at the time the invention was made to have combined Bruennert’s teachings of power conservation techniques with the teachings of Wang and Cohn, for the purpose of being able to detect the power mode status more quickly than reading the specific commands from the host . 07-21-aia AIA Claim s 15-17 are rejected under 35 U.S.C. 103 as being unpatentable over Bruennert and Wang . Regarding Claim 15 , Bruennert discloses a circuit (Figure 2, item 200) comprising: a control circuit (Figure 2, item 204); a power state transaction identification circuit coupled to the control circuit (paragraph 0025; i.e., a “power state transaction” [e.g., an idle state or power down mode - see paragraph 0065] can be identified through the termination impedance values); a bus state identification circuit coupled to the control circuit (paragraph 0025; i.e., a circuit can identify that the bus is idle [the claimed “bus state”]); and a port circuit coupled to the power state transaction identification circuit and to the bus state identification circuit (Figure 3, item 212, paragraph 0028). Bruennert does not expressly disclose wherein the port circuit comprises: a differential receiver having a first receiver input, a second receiver input, and a receiver output; a first resistor having a first resistor terminal and a second resistor terminal, the first resistor terminal coupled to the first receiver input; and a second resistor having a third resistor terminal and a fourth resistor terminal, the third resistor terminal coupled to the second receiver input and the fourth resistor terminal coupled to the second resistor terminal. In the same field of endeavor (e.g., bus transaction detection techniques), Wang teaches wherein the port circuit comprises: a differential receiver (Figure 3, item 324) having a first receiver input (Figure 3, item RXP), a second receiver input (Figure 3, item RXN), and a receiver output (Figure 3, see output of item 324); a first resistor having a first resistor terminal and a second resistor terminal, the first resistor terminal coupled to the first receiver input (Figure 3, item R1; i.e., the top terminal of the R1 resistor is indirectly coupled to the first receiver input); and a second resistor having a third resistor terminal and a fourth resistor terminal, the third resistor terminal coupled to the second receiver input (Figure 3, item R2; i.e., the top terminal of the R2 resistor is indirectly coupled to the second receiver input) and the fourth resistor terminal coupled to the second resistor terminal (Figure 3; i.e., the bottom terminal of the R2 resistor is indirectly coupled to the bottom terminal of the R1 resistor). Accordingly, it would have been obvious to one of ordinary skill in the art at the time the invention was made to have combined Wang’s teachings of bus transaction detection techniques with the teachings of Bruennert, for the purpose of adjust the device resistance in accordance with the selected power save mode. Regarding Claim 16 , Wang discloses therein the bus state identification circuit further comprises: a current source (Figure 3, item 322) having a current input and a current output, the current output coupled to the second resistor terminal and to the fourth resistor terminal and the current input coupled to the control circuit (Figure 3); a switch (Figure 3, items 310) having a first switch terminal (i.e., the top of switch M3), a second switch terminal (i.e., the bottom of switch M3), and a control terminal (Figure 3, see connection to gate of switch M3), the first switch terminal coupled to the second resistor terminal and to the fourth resistor terminal (i.e., indirectly connected to the bottom of resistor R2) and the control terminal coupled to the control circuit (i.e., a control circuit located in the host device 102 [Figure 1] that transmits the RXP and RXN signals); and a comparator (Figure 3, item 326) having a first comparator input, a second comparator input, and a comparator output, the first comparator input coupled to the current output (Figure 3; i.e., indirectly connected to the output of current source 322). Regarding Claim 17 , Wang discloses a host coupled to the port circuit by the serial bus (Figure 1, item 102) . Allowable Subject Matter Claims 4-5 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims and if the Double Patenting rejection discussed above was overcome. Claims 11-14 would be allowable if the Double Patenting rejection discussed above was overcome. 13-03-01 AIA The following is a statement of reasons for the indication of allowable subject matter: Regarding Claim 4 , the prior art of record does not teach “wherein the packet sequence identification circuit is configured to identify a series of sequential packets on the serial bus, wherein each of the sequential packets has a duration indicative of the power state transaction.” Cohn teaches a packet sequence identification circuit is configured to identify a series of sequential packets on the serial bus. However, neither Cohn nor any other prior art of record teach wherein each of the sequential packets has a duration indicative of the power state transaction as required by the claim. Regarding Claim 11 , the prior art of record does not teach “identifying a power state transaction on the serial bus, wherein the power state transaction is indicative of entering the reduced power state; … wherein identifying the power state transaction comprises: measuring a duration of each packet on the serial bus; and identifying a series of sequential packets on the serial bus.” Bruennert teaches identifying a value of termination resistance on the serial bus responsive to identifying the power state transaction, wherein the value of termination resistance is indicative of entering the reduced power state. Further, Cohn teaches a packet sequence identification circuit is configured to identify a series of sequential packets on the serial bus. However, neither Bruennert nor Cohn nor any other prior art of record teach identifying a power state transaction on the serial bus, wherein the power state transaction is indicative of entering the reduced power state or wherein identifying the power state transaction comprises: measuring a duration of each packet on the serial bus; and identifying a series of sequential packets on the serial bus as required by the claim. All claims that are not specifically addressed are allowable due to a dependency . Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure because each reference discloses methods for identifying a low power state in a serial bus repeater . Any inquiry concerning this communication or earlier communications from the examiner should be directed to FAISAL M ZAMAN whose telephone number is (571)272-6495. The examiner can normally be reached on Monday - Friday, 8 am - 5 pm, alternate Fridays. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrew J. Jung can be reached on 571-270-3779. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see https://ppair-my.uspto.gov/pair/PrivatePair. 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If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /FAISAL M ZAMAN/ Primary Examiner, Art Unit 2175 Application/Control Number: 18/903,010 Page 2 Art Unit: 2175 Application/Control Number: 18/903,010 Page 3 Art Unit: 2175 Application/Control Number: 18/903,010 Page 4 Art Unit: 2175 Application/Control Number: 18/903,010 Page 5 Art Unit: 2175 Application/Control Number: 18/903,010 Page 6 Art Unit: 2175 Application/Control Number: 18/903,010 Page 7 Art Unit: 2175 Application/Control Number: 18/903,010 Page 8 Art Unit: 2175 Application/Control Number: 18/903,010 Page 9 Art Unit: 2175 Application/Control Number: 18/903,010 Page 10 Art Unit: 2175 Application/Control Number: 18/903,010 Page 11 Art Unit: 2175 Application/Control Number: 18/903,010 Page 12 Art Unit: 2175 Application/Control Number: 18/903,010 Page 13 Art Unit: 2175 Application/Control Number: 18/903,010 Page 14 Art Unit: 2175 Application/Control Number: 18/903,010 Page 15 Art Unit: 2175 Application/Control Number: 18/903,010 Page 16 Art Unit: 2175 Application/Control Number: 18/903,010 Page 17 Art Unit: 2175 Application/Control Number: 18/903,010 Page 18 Art Unit: 2175 Application/Control Number: 18/903,010 Page 19 Art Unit: 2175 Application/Control Number: 18/903,010 Page 20 Art Unit: 2175 Application/Control Number: 18/903,010 Page 21 Art Unit: 2175 Application/Control Number: 18/903,010 Page 22 Art Unit: 2175 Application/Control Number: 18/903,010 Page 23 Art Unit: 2175 Application/Control Number: 18/903,010 Page 24 Art Unit: 2175 Application/Control Number: 18/903,010 Page 25 Art Unit: 2175 Application/Control Number: 18/903,010 Page 26 Art Unit: 2175 Application/Control Number: 18/903,010 Page 27 Art Unit: 2175 Application/Control Number: 18/903,010 Page 28 Art Unit: 2175 Application/Control Number: 18/903,010 Page 29 Art Unit: 2175 Application/Control Number: 18/903,010 Page 30 Art Unit: 2175 Application/Control Number: 18/903,010 Page 31 Art Unit: 2175 Application/Control Number: 18/903,010 Page 32 Art Unit: 2175 Application/Control Number: 18/903,010 Page 33 Art Unit: 2175 Application/Control Number: 18/903,010 Page 34 Art Unit: 2175 Application/Control Number: 18/903,010 Page 35 Art Unit: 2175 Application/Control Number: 18/903,010 Page 36 Art Unit: 2175 Application/Control Number: 18/903,010 Page 37 Art Unit: 2175 Application/Control Number: 18/903,010 Page 38 Art Unit: 2175 Application/Control Number: 18/903,010 Page 39 Art Unit: 2175 Application/Control Number: 18/903,010 Page 40 Art Unit: 2175 Application/Control Number: 18/903,010 Page 41 Art Unit: 2175 Application/Control Number: 18/903,010 Page 42 Art Unit: 2175 Application/Control Number: 18/903,010 Page 43 Art Unit: 2175 Application/Control Number: 18/903,010 Page 44 Art Unit: 2175
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