DETAILED ACTION
Response to Amendment
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 15-17 are rejected under 35 U.S.C. 103 as being unpatentable over Bruennert et al. (U.S. Patent Application Publication Number 2010/0030934) and Wang et al. (U.S. Patent Application Publication Number 2019/0288743).
Regarding Claim 15, Bruennert discloses a circuit (Figure 2, item 200, paragraphs 0027-0028) comprising:
a control circuit (Figure 2, item 204, paragraph 0028);
a power state transaction identification circuit coupled to the control circuit (Figure 3, item 229, paragraphs 0025 and 0034-0035; i.e., a “power state transaction” [e.g., an idle state or power down mode - see paragraph 0065] is identified by the mapping circuit 229 [the claimed “power state transaction identification circuit”] and thereafter a termination resistance is calculated in order to set the termination resistor 228 accordingly; the mapping circuit 229 is coupled to the control circuit 204 via buses 212 and 214);
a bus state identification circuit coupled to the control circuit (Figure 3, item 227, paragraphs 0025, 0035, and 0068; i.e., the circuit 227 [the claimed “bus state identification circuit”] can identify that the bus is idle [the claimed “bus state”]; it can be a bus snooping unit that determines/identifies the bus transmission state; the circuit 227 is coupled to the control circuit 204 via bus 214); and
a port circuit coupled to the power state transaction identification circuit and to the bus state identification circuit (Figure 3, items 226 and 228, paragraphs 0028 and 0032-0033; i.e., the I/O node in each memory chip 202 together with data buffer 226 and termination resistor block 228 is equivalent to the claimed “port circuit” and is at least indirectly coupled to both the power state transaction identification circuit 229 and to the bus state identification circuit 227).
Bruennert does not expressly disclose wherein the port circuit comprises:
a differential receiver having a first receiver input, a second receiver input, and a receiver output;
a first resistor having a first resistor terminal and a second resistor terminal, the first resistor terminal coupled to the first receiver input; and
a second resistor having a third resistor terminal and a fourth resistor terminal, the third resistor terminal coupled to the second receiver input and the fourth resistor terminal coupled to the second resistor terminal.
In the same field of endeavor (e.g., bus transaction detection techniques), Wang teaches wherein the port circuit comprises:
a differential receiver (Figure 3, item 324) having a first receiver input (Figure 3, item RXP), a second receiver input (Figure 3, item RXN), and a receiver output (Figure 3, see output of item 324);
a first resistor having a first resistor terminal and a second resistor terminal, the first resistor terminal coupled to the first receiver input (Figure 3, item R1; i.e., the top terminal of the R1 resistor is indirectly coupled to the first receiver input); and
a second resistor having a third resistor terminal and a fourth resistor terminal, the third resistor terminal coupled to the second receiver input (Figure 3, item R2; i.e., the top terminal of the R2 resistor is indirectly coupled to the second receiver input) and the fourth resistor terminal coupled to the second resistor terminal (Figure 3; i.e., the bottom terminal of the R2 resistor is indirectly coupled to the bottom terminal of the R1 resistor).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time the invention was made to have combined Wang’s teachings of bus transaction detection techniques with the teachings of Bruennert, for the purpose of adjust the device resistance in accordance with the selected power save mode.
Regarding Claim 16, Wang discloses therein the bus state identification circuit further comprises:
a current source (Figure 3, item 322) having a current input and a current output, the current output coupled to the second resistor terminal and to the fourth resistor terminal and the current input coupled to the control circuit (Figure 3);
a switch (Figure 3, items 310) having a first switch terminal (i.e., the top of switch M3), a second switch terminal (i.e., the bottom of switch M3), and a control terminal (Figure 3, see connection to gate of switch M3), the first switch terminal coupled to the second resistor terminal and to the fourth resistor terminal (i.e., indirectly connected to the bottom of resistor R2) and the control terminal coupled to the control circuit (i.e., a control circuit located in the host device 102 [Figure 1] that transmits the RXP and RXN signals); and
a comparator (Figure 3, item 326) having a first comparator input, a second comparator input, and a comparator output, the first comparator input coupled to the current output (Figure 3; i.e., indirectly connected to the output of current source 322).
Regarding Claim 17, Wang discloses a host coupled to the port circuit by the serial bus (Figure 1, item 102).
Allowable Subject Matter
Claims 1, 2, and 4-14 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding Claim 1, Applicant’s arguments, see page 7, filed 9/4/26, with respect to Claims 1 and 3 have been fully considered and are persuasive. The rejection of 6/4/26 has been withdrawn.
Regarding Claim 11, the prior art of record does not teach “identifying a power state transaction on the serial bus, wherein the power state transaction is indicative of entering the reduced power state; … wherein identifying the power state transaction comprises: measuring a duration of each packet on the serial bus; and identifying a series of sequential packets on the serial bus.” Bruennert teaches identifying a value of termination resistance on the serial bus responsive to identifying the power state transaction, wherein the value of termination resistance is indicative of entering the reduced power state. Further, Cohn teaches a packet sequence identification circuit is configured to identify a series of sequential packets on the serial bus. However, neither Bruennert nor Cohn nor any other prior art of record teach identifying a power state transaction on the serial bus, wherein the power state transaction is indicative of entering the reduced power state or wherein identifying the power state transaction comprises: measuring a duration of each packet on the serial bus; and identifying a series of sequential packets on the serial bus as required by the claim.
All claims that are not specifically addressed are allowable due to a dependency.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure because each reference discloses methods for identifying a low power state in a serial bus repeater.
Response to Arguments
Applicant's arguments filed 9/4/26 have been fully considered but they are not persuasive.
Regarding Claim 15, Applicant argues “[a]s described in paragraph [0025], it is the ‘item 204’ itself (the same element that is mapped to the ‘control circuit’) that identifies the idle state. The paragraph does not disclose any additional circuits, such as the ‘state power transaction identification circuit’ or the ‘bus state identification circuit’ that are coupled to the ‘control circuit’ as claim 15 recites.” Response, page 8. The examiner disagrees. Contrary to Applicant’s argument, Bruennert does in fact disclose the argued limitations. To clarify the previous rejection, the mapping circuit 229 (Figure 3) was equated to the claimed “power state transaction identification circuit”, while the bus state determination circuit 227 was equated to the claimed “bus state identification circuit”. Both of these circuits are at least indirectly connected to the control circuit 204 (see Figures 2 and 3, e.g., via buses 212 and 214). Further, a “power state transaction” (e.g., an idle state or power down mode - see paragraph 0065) is identified by the mapping circuit 229 (the claimed “power state transaction identification circuit”) and thereafter a termination resistance is calculated in order to set the termination resistor 228 accordingly. See Bruennert, paragraphs 0025 and 0034-0035. The circuit 227 (the claimed “bus state identification circuit”) can identify that the bus is idle (the claimed “bus state”). The circuit 227 can be a bus snooping unit that determines/identifies the bus transmission state. See id. at paragraphs 0025, 0035, and 0068. Accordingly, it can be seen that Bruennert does in fact disclose the argued features.
Therefore, these claims stand as previously rejected.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FAISAL M ZAMAN whose telephone number is (571)272-6495. The examiner can normally be reached on Monday - Friday, 8 am - 5 pm, alternate Fridays.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrew J. Jung can be reached on 571-270-3779. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/FAISAL M ZAMAN/ Primary Examiner, Art Unit 2175
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