DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 26 May 2026 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-12, 14-15, and 23-26 are rejected under 35 U.S.C. 103 as being unpatentable over Jung et al. (hereinafter “Jung” US 2022 / 0225481) in view of Hyun et al. (hereinafter “Hyun” US 2021 / 0225266).
As pertaining to Claim 1, Jung discloses (see Fig. 7) a pixel (301-1, 200-1), comprising (see Page 11, Para. [0165]-[0172]):
a light-emitting element (200-1) including a first electrode (i.e., an upper electrode), and a second electrode (i.e., a lower electrode) connected to a low power line (VSS) which transmits a low power voltage (i.e., (VSS));
a pulse width modulator (320) which controls an emission time duration of the light-emitting element (200-1) based on a data voltage (Sig), the pulse width modulator (320) including:
a first driving transistor (321) including:
a gate electrode connected to a first node (i.e., a gate node);
a first electrode (i.e., an upper electrode) connected to a second node (i.e., an upper node); and
a second electrode (i.e., a lower electrode) connected to a third node (i.e., a lower node); and
a first initialization transistor (352), a first write transistor (323) and a first compensation transistor (322) respectively connected to the gate electrode, the first electrode (i.e., the upper electrode) and the second electrode (i.e., the lower electrode) of the first driving transistor (321); and
a constant current generator (310) which provides a driving current having a constant level to the light-emitting element (200-1) based on a constant current generation voltage (see (Sig)), the constant current generator (310) including:
a second driving transistor (311) including:
a gate electrode connected to a fourth node (i.e., a gate node);
a first electrode (i.e., an upper electrode) connected to a fifth node (i.e., an upper node); and
a second electrode (i.e., a lower electrode) connected to a sixth node (i.e., a lower node); and
a second initialization transistor (353), a second write transistor (313), and a second compensation transistor (312) respectively connected to the gate electrode, the first electrode (i.e., the upper electrode) and the second electrode (i.e., the lower electrode) of the second driving transistor (311),
wherein at least one of the first driving transistor (321) and the second driving transistor (311) is a P-type transistor (see Page 11 through Page 12, Para. [0174]-[0188] for a general description of the pixel of Figure 7).
Jung does not explicitly show that each of the first compensation transistor (322) and the first write transistor (323) of the pulse width modulator (320) is an N-type transistor, and each of the second compensation transistor (312) and the second write transistor (313) of the constant current generator (310) is an N-type transistor, while at least one of the first driving transistor (321) and the second driving transistor (322) is a P-type transistor.
However, Jung explicitly discloses that the transistors of the pixel circuit (301-1) can be implemented using any structure or type of thin film transistors (TFTs; see Page 6, Para. [0097]). In this regard, one of ordinary skill in the art would have readily recognized that there are, in fact, only two types of thin film transistors (TFTs) that are readily available for implementation in the pixel circuit (301-1) of Jung, namely the N-type transistor and the P-type transistor. Further, the usage of N-type TFTs, P-type TFTs, and mixed N-type and P-type TFTs in pixel circuits has been fully implemented in the art, and the technical aspects of substitution of an N-type TFT for a P-type TFT, and vice-versa, would have been well understood by one of ordinary skill in the art.
Therefore, even though Jung schematically shows the first compensation transistor (322) and the first write transistor (323) of the pulse width modulator (320) as P-type transistors and the second compensation transistor (312) and the second write transistor (313) of the constant current generator (310) as P-type transistors, it would have been obvious to one of ordinary skill in the art that at least one of the first compensation transistor (322) and the first write transistor (323) of the pulse width modulator (320) and at least one of the second compensation transistor (312) and the second write transistor (313) of the constant current generator (310) could be implemented as an N-type transistor through a simple substitution of known and widely available elements, namely the simple substitution of an N-type transistor for a P-type transistor. Again, only two types of thin film transistors (TFTs) are readily available for implementation in the pixel circuit (301-1). Further, the substitution of an N-type transistor for a P-type transistor would have been well-within the knowledge of one having ordinary skill in the art, and the results of the substitution would have been a predictable implementation of a known element in the art to provide a switching and/or current driving function, and would have been consistent with the suggestions of Jung (again, see Page 6, Para. [0097]).
Still, Jung does not explicitly disclose a specific combination of P-type and N-type transistors in the pixel (301-1, 200-1) wherein a compensation transistor (322, 312) and a write transistor (323, 313) are each implemented as N-type transistors while a driving transistor (321, 311) is implemented as a P-type transistor.
However, in the same field of endeavor, Hyun discloses (see Fig. 11) a pixel circuit (13), having a structure analogous to that of Jung, wherein the pixel circuit (13; see Page 4 through Page 5, Para. [0084]-[0091] and [0094]) comprises a specific combination of a driving transistor (M1) implemented as a P-type transistor while a write transistor (M3), connected to a first electrode of the driving transistor (M1), and a compensation transistor (M4), connected to a second electrode of the driving transistor (M1), are each implemented as N-type transistors (see Page 6, Para. [0106] and Page 8, Para. [0155]-[0157]). Hyun discloses that the utilization of mixed P-type and N-type transistors in the pixel circuit, including the specific implementation of a P-type driving transistor in combination with an N-type write transistor and an N-type compensation transistor, can allow for a pixel circuit structure requiring greatly reduced power consumption while taking advantage of the inherent features of each of the N-type and the P-type transistor to improve display quality (see Para. [0106]-[0108]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Jung with the teachings of Hyun, such that each of the first compensation transistor (322) and the first write transistor (323) of the pulse width modulator (320) of Jung is an N-type transistor, and each of the second compensation transistor (312) and the second write transistor (313) of the constant current generator (310) of Jung is an N-type transistor, while at least one of the first driving transistor (321) and the second driving transistor (322) of Jung is a P-type transistor, as suggested by the teachings of Hyun, in order to provide a pixel circuit structure that allows for greatly reduced power consumption while taking advantage of the inherent features of each of the N-type and the P-type transistor to improve display quality.
As pertaining to Claim 2, Jung discloses (see Fig. 7) that:
the first write transistor (323) includes:
a gate electrode which receives a scan signal (SPWM);
a first electrode (i.e., a left electrode) connected to a data line (Sig) which transmits the data voltage (see (Sig)); and
a second electrode (i.e., a right electrode) connected to the second node (i.e., the upper node of (321));
the first compensation transistor (322) includes:
a gate electrode which receives the scan signal (SPWM);
a first electrode (i.e., a right electrode) connected to the third node (i.e., the lower node of (321)); and
a second electrode (i.e., a left electrode) connected to the first node (i.e., the gate node of (321));
the first initialization transistor (352) includes:
a gate electrode which receives a first initialization gate signal (VST);
a first electrode (i.e., a lower electrode) which receives a first initialization voltage (Vini); and
a second electrode (i.e., an upper electrode) connected to the first node (i.e., the gate node of (321)); and
the pulse width modulator (320) further includes:
a first emission control transistor (331) including:
a gate electrode which receives an emission control signal (Emi);
a first electrode (i.e., an upper electrode) which receives a first high power voltage (VDD); and
a second electrode (i.e., a lower electrode) connected to the second node (i.e., the upper node of (321));
a second emission control transistor (332) including:
a gate electrode which receives the emission control signal (Emi);
a first electrode (i.e., an upper electrode) connected to the third node (i.e., the lower node of (321)); and
a second electrode (i.e., a lower electrode) connected to the fourth node (i.e., the gate node of (311));
a first capacitor (341) including:
a first electrode (i.e., a left electrode) which receives a sweep signal (Vsweep); and
a second electrode (i.e., a right electrode) connected to the first node (i.e., the gate node of (321); again, see Page 11 through Page 12, Para. [0174]-[0188] for a general description of the pixel of Figure 7).
As pertaining to Claim 3, the combined teachings of Jung and Hyun disclose (see Fig. 7 of Jung in combination with Fig. 11 of Hyun) that the first driving transistor (321) is a P-type transistor, and each of the first write transistor (323) and the first compensation transistor (322) is an N-type transistor (again, see Page 6, Para. [0097] of Jung with (M1), (M3), (M4) in Fig. 11 of Hyun).
As pertaining to Claim 4, the combined teachings of Jung and Hyun disclose (see Fig. 7 of Jung in combination with Fig. 11 of Hyun) that the first initialization transistor (352) is an N-type transistor (again, see Page 6, Para. [0097] of Jung with (M7) in Fig. 11 of Hyun; also again, see Page 6, Para. [0106] of Hyun).
As pertaining to Claim 5, neither Jung nor Hyun explicitly provides an implementation in which the first emission control transistor (331) and the second emission control transistor (332) is an N-type transistor.
However, again, Jung explicitly discloses (see Fig. 7) that the transistors of the pixel circuit (301-1) can be implemented using any structure or type of thin film transistors (TFTs; see Page 6, Para. [0097]). Further, and one of ordinary skill in the art would have readily recognized that there are, in fact, only two types of thin film transistors (TFTs) that are readily available for implementation in the pixel circuit (301-1), namely the N-type transistor and the P-type transistor. And again, the usage of N-type TFTs, P-type TFTs, and mixed N-type and P-type TFTs in pixel circuits has been fully implemented in the art, and the technical aspects of substitution of an N-type TFT for a P-type TFT, and vice-versa, would have been well understood by one of ordinary skill in the art. Further still, Hyun discloses that the utilization of mixed P-type and N-type transistors in the pixel circuit can allow for a pixel circuit structure requiring greatly reduced power consumption while taking advantage of the inherent features of each of the N-type and the P-type transistor to improve display quality (see Para. [0106]-[0108]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, given the combined teachings of Jung and Hyun, that each of the first emission control transistor (331) and the second emission control transistor (332) is an N-type transistor, as the implementation of the first emission control transistor (331) and the second emission control transistor (332) as an N-type transistor is a simple substitution of known and widely available elements, namely the simple substitution of an N-type transistor for a P-type transistor. Further, the substitution of an N-type transistor for a P-type transistor would have been well-within the knowledge of one having ordinary skill in the art, and the results of the substitution would have been a predictable implementation of a known element in the art to provide a switching and/or current driving function. Further still, the implementation of the first emission control transistor (331) and the second emission control transistor (332) as an N-type transistor provides for a pixel circuit structure that allows for greatly reduced power consumption while taking advantage of the inherent features of each of the N-type and the P-type transistor to improve display quality, as suggested by Hyun.
As pertaining to Claim 6, Jung discloses (see Fig. 7) that:
the second write transistor (313) includes:
a gate electrode which receives a constant current generation scan signal (SPAM);
a first electrode (i.e., a left electrode) connected to the data line (Sig) which transmits the constant current generation voltage (i.e., see (Sig)); and
a second electrode (i.e., a right electrode) connected to the fifth node (i.e., the upper node of (311));
the second compensation transistor (312) includes:
a gate electrode which receives the constant current generation scan signal (SPAM);
a first electrode (i.e., a right electrode) connected to the sixth node (i.e., the lower node of (311)); and
a second electrode (i.e., a left electrode) connected to the fourth node (i.e., the gate node of (311));
the second initialization transistor (353) includes:
a gate electrode which receives a second initialization gate signal (VST);
a first electrode (i.e., a left electrode) which receives the first initialization voltage (Vini); and
a second electrode (i.e., a right electrode) connected to the fourth node (i.e., the gate node of (311)); and
the constant current generator (310) further includes:
a third emission control transistor (333) including:
a gate electrode which receives the emission control signal (Emi);
a first electrode (i.e., an upper electrode) which receives a second high power voltage (VDD); and
a second electrode (i.e., a lower electrode) connected to the fifth node (i.e., the upper node of (311));
a fourth emission control transistor (334) including:
a gate electrode which receives the emission control signal (Emi);
a first electrode (i.e., an upper electrode) connected to the sixth node (i.e., the lower node of (311)); and
a second electrode (i.e., a lower electrode) connected to the first electrode (i.e., the upper electrode) of the light-emitting element (200-1);
a bypass transistor (354) including:
a gate electrode which receives a bypass gate signal (Test/Discharging);
a first electrode (i.e., a lower electrode) connected to a second initialization voltage line (VSS) which transmits a second initialization voltage (see (VSS)); and
a second electrode (i.e., an upper electrode) connected to the first electrode (i.e., the upper electrode) of the light-emitting element (200-1); and
a second capacitor (342) including:
a first electrode (i.e., a left electrode) which receives the second high power voltage (VDD); and
a second electrode (i.e., a right electrode) connected to the fourth node (i.e., the gate node of (311); again, see Page 11 through Page 12, Para. [0174]-[0188] for a general description of the pixel of Figure 7).
As pertaining to Claim 7, the combined teachings of Jung and Hyun disclose (see Fig. 7 of Jung in combination with Fig. 11 of Hyun) that the second driving transistor (311) is a P-type transistor, and each of the second write transistor (313) and the second compensation transistor (312) is an N-type transistor (again, see Page 6, Para. [0097] of Jung with (M1), (M3), (M4) in Fig. 11 of Hyun).
As pertaining to Claim 8, the combined teachings of Jung and Hyun disclose (see Fig. 7 of Jung in combination with Fig. 11 of Hyun) that the second initialization transistor (353) is an N-type transistor (again, see Page 6, Para. [0097] of Jung with (M7) in Fig. 11 of Hyun; also again, see Page 6, Para. [0106] of Hyun).
As pertaining to Claim 9, neither Jung nor Hyun explicitly provides an implementation in which the third emission control transistor (333) and the fourth emission control transistor (334) is an N-type transistor.
However, again, Jung explicitly discloses (see Fig. 7) that the transistors of the pixel circuit (301-1) can be implemented using any structure or type of thin film transistors (TFTs; see Page 6, Para. [0097]). Further, and one of ordinary skill in the art would have readily recognized that there are, in fact, only two types of thin film transistors (TFTs) that are readily available for implementation in the pixel circuit (301-1), namely the N-type transistor and the P-type transistor. And again, the usage of N-type TFTs, P-type TFTs, and mixed N-type and P-type TFTs in pixel circuits has been fully implemented in the art, and the technical aspects of substitution of an N-type TFT for a P-type TFT, and vice-versa, would have been well understood by one of ordinary skill in the art. Further still, Hyun discloses that the utilization of mixed P-type and N-type transistors in the pixel circuit can allow for a pixel circuit structure requiring greatly reduced power consumption while taking advantage of the inherent features of each of the N-type and the P-type transistor to improve display quality (see Para. [0106]-[0108]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, given the combined teachings of Jung and Hyun, that each of the third emission control transistor (333) and the fourth emission control transistor (334) is an N-type transistor, as the implementation of the third emission control transistor (333) and the fourth emission control transistor (334) as an N-type transistor is a simple substitution of known and widely available elements, namely the simple substitution of an N-type transistor for a P-type transistor. Further, the substitution of an N-type transistor for a P-type transistor would have been well-within the knowledge of one having ordinary skill in the art, and the results of the substitution would have been a predictable implementation of a known element in the art to provide a switching and/or current driving function. Further still, the implementation of the third emission control transistor (333) and the fourth emission control transistor (334) as an N-type transistor provides for a pixel circuit structure that allows for greatly reduced power consumption while taking advantage of the inherent features of each of the N-type and the P-type transistor to improve display quality, as suggested by Hyun.
As pertaining to Claim 10, the combined teachings of Jung and Hyun disclose (see Fig. 7 of Jung; and see Fig. 11 of Hyun) that the bypass transistor (see (354) in Fig. 7 of Jung corresponding to (M8) in Fig. 11 of Hyun) is an N-type transistor (again, see Page 6, Para. [0097] of Jung; and see Page 6, Para. [0102] of Hyun).
Again, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, given the combined teachings of Jung and Hyun, that the bypass transistor is an N-type transistor, as the implementation of the bypass transistor as an N-type transistor allows for greatly reduced power consumption while taking advantage of the inherent features of each of the N-type and the P-type transistor to improve display quality, as suggested by Hyun.
As pertaining to Claim 11, Jung does not explicitly show that a first electrode of the bypass transistor is connected to a second initialization voltage line that is separated from the lower power line to transmit the second initialization voltage.
However, again, Hyun discloses (see Fig. 11) a pixel circuit comprising a bypass transistor (M8) including a gate electrode which receives a bypass gate signal (Si), a second electrode connected to the first electrode (N4) of the light-emitting element (LD), and a first electrode connected to a second initialization voltage line (Vint2) which transmits a second initialization voltage (Vint2) and is separated from the lower power line (VSS) that is connected to a second electrode of the light-emitting element (LD; see Page 8, Para. [0148] and [0151]-[0152]; and Page 9, Para. [0163]-[0164]). It is a goal of Hyun to provide a bypass transistor that allows for greater control of the driving conditions of a display device in order to improve driving performance and to reduce flicker and incorrect emission through a separated second initialization voltage line (again, see Page 9, Para. [0163]-[0164]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Jung with the teachings of Hyun, such that a first electrode of the bypass transistor of Jung is connected to a second initialization voltage line that is separated from the lower power line to transmit the second initialization voltage, as suggested by Hyun, in order to allow for greater control of the driving conditions of the display device in order to improve driving performance and to reduce flicker and incorrect emission through the separated second initialization voltage line.
As pertaining to Claim 12, Hyun discloses (see Fig. 10) that a voltage level of the second initialization voltage (Vint2) is higher than or equal to a voltage level of the lower power voltage (VSS; again, see Page 8, Para. [0151]-[0152]).
As pertaining to Claim 14, Jung discloses (see Fig. 7) that one frame includes a display scan period (i.e., an arbitrary period during which (SPWM) is an “on” voltage for any arbitrary period and (322, 323) are turned “on” for any arbitrary period) in which the data voltage (Sig) is written and a self scan period (i.e., an arbitrary period during which (SPWM) is an “off” voltage for any arbitrary period and (322, 323) are turned “off” for any arbitrary period) in which the data voltage (Sig) is not written, and
the second initialization gate signal (VST) has a turn-on voltage level (i.e., any arbitrary voltage level) in a first initialization period (i.e., any arbitrary period) within the display scan period (i.e., an arbitrary period during which (SPWM) is an “on” voltage for any arbitrary period and (322, 323) are turned “on” for any arbitrary period) and a second initialization period (i.e., any arbitrary period) within the self scan period (i.e., an arbitrary period during which (SPWM) is an “off” voltage for any arbitrary period and (322, 323) are turned “off” for any arbitrary period; see Page 11, Para. [0176]-[0177] and Page 12, Para. [0186]-[0187]).
As pertaining to Claim 15, Jung discloses (see Fig. 7) that the first initialization gate signal (VST) has a turn-on voltage level (i.e., any arbitrary voltage level) in the first initialization period (i.e., any arbitrary period), and has a turn-off voltage level (i.e., any arbitrary voltage level) in the second initialization period (i.e., any arbitrary period; again, see Page 11, Para. [0176]-[0177] and Page 12, Para. [0186]-[0187] and note that the claimed periods are arbitrary).
As pertaining to Claim 23, Jung discloses (see Fig 1 and Fig. 6 in combination with Fig. 7) an electronic device comprising:
a display device (see Page 1, Para. [0002]), comprising:
a display panel (1000) including:
a plurality of pixels (301-1, 200-1), each of the plurality of pixels (300-1, 200-1) including (see Page 11, Para. [0165]-[0172]):
a light-emitting element (200-1) including a first electrode (i.e., an upper electrode), and a second electrode (i.e., a lower electrode) connected to a low power line (VSS) which transmits a low power voltage (i.e., (VSS));
a pulse width modulator (320) which controls an emission time duration of the light-emitting element (200-1) based on a data voltage (see (Sig)), the pulse width modulator (320) including:
a first driving transistor (321) including:
a gate electrode connected to a first node (i.e., a gate node);
a first electrode (i.e., an upper electrode) connected to a second node (i.e., an upper node); and
a second electrode (i.e., a lower electrode) connected to a third node (i.e., a lower node); and
a first initialization transistor (352), a first write transistor (323) and a first compensation transistor (322) respectively connected to the gate electrode, the first electrode (i.e., the upper electrode) and the second electrode (i.e., the lower electrode) of the first driving transistor (321); and
a constant current generator (310) which provides a driving current having a constant level to the light-emitting element (200-1) based on a constant current generation voltage (see (Sig)), the constant current generator (310) including:
a second driving transistor (311) including:
a gate electrode connected to a fourth node (i.e., a gate node);
a first electrode (i.e., an upper electrode) connected to a fifth node (i.e., an upper node); and
a second electrode (i.e., a lower electrode) connected to a sixth node (i.e., a lower node); and
a second initialization transistor (353), a second write transistor (313), and a second compensation transistor (312) respectively connected to the gate electrode, the first electrode (i.e., the upper electrode) and the second electrode (i.e., the lower electrode) of the second driving transistor (311);
a scan driver (see (830) in Fig. 6) which sequentially provides scan signals (SWPM, SPAM) to the plurality of pixels (301-1, 200-1); and
a data driver (820) which provides the data voltage (see (Sig)) and the constant current generation voltage (see (Sig)) to each of the plurality of pixels (see (301-1, 200-1; and see Page 9, Para. [0129], [0132], and [0134]),
wherein at least one of the first driving transistor (321) and the second driving transistor (311) is a P-type transistor (see Page 11 through Page 12, Para. [0174]-[0188] for a general description of the pixel of Figure 7).
Jung does not explicitly show that each of the first compensation transistor (322) and the first write transistor (323) of the pulse width modulator (320) is an N-type transistor, and each of the second compensation transistor (312) and the second write transistor (313) of the constant current generator (310) is an N-type transistor, while at least one of the first driving transistor (321) and the second driving transistor (322) is a P-type transistor.
However, Jung explicitly discloses that the transistors of the pixel circuit (301-1) can be implemented using any structure or type of thin film transistors (TFTs; see Page 6, Para. [0097]). In this regard, one of ordinary skill in the art would have readily recognized that there are, in fact, only two types of thin film transistors (TFTs) that are readily available for implementation in the pixel circuit (301-1) of Jung, namely the N-type transistor and the P-type transistor. Further, the usage of N-type TFTs, P-type TFTs, and mixed N-type and P-type TFTs in pixel circuits has been fully implemented in the art, and the technical aspects of substitution of an N-type TFT for a P-type TFT, and vice-versa, would have been well understood by one of ordinary skill in the art.
Therefore, even though Jung schematically shows the first compensation transistor (322) and the first write transistor (323) of the pulse width modulator (320) as P-type transistors and the second compensation transistor (312) and the second write transistor (313) of the constant current generator (310) as P-type transistors, it would have been obvious to one of ordinary skill in the art that at least one of the first compensation transistor (322) and the first write transistor (323) of the pulse width modulator (320) and at least one of the second compensation transistor (312) and the second write transistor (313) of the constant current generator (310) could be implemented as an N-type transistor through a simple substitution of known and widely available elements, namely the simple substitution of an N-type transistor for a P-type transistor. Again, only two types of thin film transistors (TFTs) are readily available for implementation in the pixel circuit (301-1). Further, the substitution of an N-type transistor for a P-type transistor would have been well-within the knowledge of one having ordinary skill in the art, and the results of the substitution would have been a predictable implementation of a known element in the art to provide a switching and/or current driving function, and would have been consistent with the suggestions of Jung (again, see Page 6, Para. [0097]).
Still, Jung does not explicitly disclose a specific combination of P-type and N-type transistors in the pixel (301-1, 200-1) wherein a compensation transistor (322, 312) and a write transistor (323, 313) are each implemented as N-type transistors while a driving transistor (321, 311) is implemented as a P-type transistor.
However, in the same field of endeavor, Hyun discloses (see Fig. 11) a pixel circuit (13), having a structure analogous to that of Jung, wherein the pixel circuit (13; see Page 4 through Page 5, Para. [0084]-[0091] and [0094]) comprises a specific combination of a driving transistor (M1) implemented as a P-type transistor while a write transistor (M3), connected to a first electrode of the driving transistor (M1), and a compensation transistor (M4), connected to a second electrode of the driving transistor (M1), are each implemented as N-type transistors (see Page 6, Para. [0106] and Page 8, Para. [0155]-[0157]). Hyun discloses that the utilization of mixed P-type and N-type transistors in the pixel circuit, including the specific implementation of a P-type driving transistor in combination with an N-type write transistor and an N-type compensation transistor, can allow for a pixel circuit structure requiring greatly reduced power consumption while taking advantage of the inherent features of each of the N-type and the P-type transistor to improve display quality (see Para. [0106]-[0108]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Jung with the teachings of Hyun, such that each of the first compensation transistor (322) and the first write transistor (323) of the pulse width modulator (320) of Jung is an N-type transistor, and each of the second compensation transistor (312) and the second write transistor (313) of the constant current generator (310) of Jung is an N-type transistor, while at least one of the first driving transistor (321) and the second driving transistor (322) of Jung is a P-type transistor, as suggested by the teachings of Hyun, in order to provide a pixel circuit structure that allows for greatly reduced power consumption while taking advantage of the inherent features of each of the N-type and the P-type transistor to improve display quality.
As pertaining to Claim 24, Jung discloses (see Fig. 7) that:
the first write transistor (323) includes:
a gate electrode which receives a scan signal (SPWM) of the scan signals (SPWM, SPAM);
a first electrode (i.e., a left electrode) connected to a data line (Sig) which transmits the data voltage (see (Sig)); and
a second electrode (i.e., a right electrode) connected to the second node (i.e., the upper node of (321));
the first compensation transistor (322) includes:
a gate electrode which receives the scan signal (SPWM);
a first electrode (i.e., a right electrode) connected to the third node (i.e., the lower node of (321)); and
a second electrode (i.e., a left electrode) connected to the first node (i.e., the gate node of (321));
the first initialization transistor (352) includes:
a gate electrode which receives a first initialization gate signal (VST);
a first electrode (i.e., a lower electrode) which receives a first initialization voltage (Vini); and
a second electrode (i.e., an upper electrode) connected to the first node (i.e., the gate node of (321)); and
the pulse width modulator (320) further includes:
a first emission control transistor (331) including:
a gate electrode which receives an emission control signal (Emi);
a first electrode (i.e., an upper electrode) which receives a first high power voltage (VDD); and
a second electrode (i.e., a lower electrode) connected to the second node (i.e., the upper node of (321));
a second emission control transistor (332) including:
a gate electrode which receives the emission control signal (Emi);
a first electrode (i.e., an upper electrode) connected to the third node (i.e., the lower node of (321)); and
a second electrode (i.e., a lower electrode) connected to the fourth node (i.e., the gate node of (311)); and
a first capacitor (341) including:
a first electrode (i.e., a left electrode) which receives a sweep signal (Vsweep); and
a second electrode (i.e., a right electrode) connected to the first node (i.e., the gate node of (321); again, see Page 11 through Page 12, Para. [0174]-[0188] for a general description of the pixel of Figure 7).
As pertaining to Claim 25, Jung discloses (see Fig. 7) that:
the second write transistor (313) includes:
a gate electrode which receives a constant current generation scan signal (SPAM);
a first electrode (i.e., a left electrode) connected to the data line (Sig) which transmits the constant current generation voltage (i.e., see (Sig)); and
a second electrode (i.e., a right electrode) connected to the fifth node (i.e., the upper node of (311)),
the second compensation transistor (312) includes:
a gate electrode which receives the constant current generation scan signal (SPAM);
a first electrode (i.e., a right electrode) connected to the sixth node (i.e., the lower node of (311)); and
a second electrode (i.e., a left electrode) connected to the fourth node (i.e., the gate node of (311)),
the second initialization transistor (353) includes:
a gate electrode which receives a second initialization gate signal (VST);
a first electrode (i.e., a left electrode) which receives the first initialization voltage (Vini); and
a second electrode (i.e., a right electrode) connected to the fourth node (i.e., the gate node of (311)); and
the constant current generator (310) further includes:
a third emission control transistor (333) including:
a gate electrode which receives the emission control signal (Emi);
a first electrode (i.e., an upper electrode) which receives a second high power voltage (VDD); and
a second electrode (i.e., a lower electrode) connected to the fifth node (i.e., the upper node of (311));
a fourth emission control transistor (334) including:
a gate electrode which receives the emission control signal (Emi);
a first electrode (i.e., an upper electrode) connected to the sixth node (i.e., the lower node of (311)); and
a second electrode (i.e., a lower electrode) connected to the first electrode (i.e., the upper electrode) of the light-emitting element (200-1);
a bypass transistor (354) including:
a gate electrode which receives a bypass gate signal (Test/Discharging);
a first electrode (i.e., a lower electrode) connected to a second initialization voltage line (VSS) which transmits a second initialization voltage (see (VSS)); and
a second electrode (i.e., an upper electrode) connected to the first electrode (i.e., the upper electrode) of the light-emitting element (200-1); and
a second capacitor (342) including:
a first electrode (i.e., a left electrode) which receives the second high power voltage (VDD); and
a second electrode (i.e., a right electrode) connected to the fourth node (i.e., the gate node of (311); again, see Page 11 through Page 12, Para. [0174]-[0188] for a general description of the pixel of Figure 7).
As pertaining to Claim 26, Jung does not explicitly show that the second initialization voltage line is separated from the lower power line.
However, again, Hyun discloses (see Fig. 11) a pixel circuit comprising a bypass transistor (M8) including a gate electrode which receives a bypass gate signal (Si), a second electrode connected to the first electrode (N4) of the light-emitting element (LD), and a first electrode connected to a second initialization voltage line (Vint2) which transmits a second initialization voltage (Vint2) and is separated from the lower power line (VSS) that is connected to a second electrode of the light-emitting element (LD; see Page 8, Para. [0148] and [0151]-[0152]; and Page 9, Para. [0163]-[0164]). It is a goal of Hyun to provide a bypass transistor that allows for greater control of the driving conditions of a display device in order to improve driving performance and to reduce flicker and incorrect emission through a separated second initialization voltage line (again, see Page 9, Para. [0163]-[0164]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Jung with the teachings of Hyun, such that a first electrode of the bypass transistor of Jung is connected to a second initialization voltage line that is separated from the lower power line to transmit the second initialization voltage, as suggested by Hyun, in order to allow for greater control of the driving conditions of the display device in order to improve driving performance and to reduce flicker and incorrect emission through the separated second initialization voltage line.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Jung in view of Hyun and further in view of Hashimoto (US 2023 / 0057215).
As pertaining to Claim 13, neither Jung nor Hyun explicitly discloses that a voltage level of the first high power voltage (VDD) of the pulse width modulator (320) is higher than a voltage level of the second high power voltage of the constant current generator (310).
However, in the same field of endeavor, Hashimoto discloses (see Fig. 2 and Fig. 4) that it was well-known in the art before the effective filing date of the claimed invention to implement a pixel circuit (200) comprising a pulse width modulator (121) in combination with a constant current generator (122), wherein a first high power voltage (Vpwm) of the pulse width modulator (121) is different from, and higher than, a voltage level of a second high power voltage (Vpam) of the constant current generator (122; see Page 2, Para. [0023]-[0025] and [0028]; and see Page 5, Para. [0047]), in order to provide improved grayscale control using a hybrid gamma setting for the pulse width modulator and the constant current generator that improves optical performance without significantly increasing cost (see Page 1, Para. [0005] and Page 6, Para. [0072]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Jung and Hyun with the teachings of Hashimoto, such that a voltage level of the first high power voltage (VDD) of the pulse width modulator (320) is higher than a voltage level of the second high power voltage of the constant current generator (310), in order to provide improved grayscale control using a hybrid gamma setting for the pulse width modulator and the constant current generator that improves optical performance without significantly increasing cost.
Claims 16-19 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (hereinafter “Kim” WO-2021 / 215817) in view of Hyun.
(It should be noted that the relevant portions of the Kim reference are cited with respect to the accompanying English Language Machine Translation of WO-2021 / 215817).
As pertaining to Claim 16, Kim discloses (see Fig. 4a and Fig. 4b) a pixel (110), comprising:
a light-emitting element (120) including a first electrode (i.e., an upper electrode), and a second electrode (i.e., a lower electrode) connected to a low power line (VSS) which transmits a low power voltage (i.e., (VSS));
a pulse width modulator (111) which controls an emission time duration of the light-emitting element (120) based on a data voltage (Vdata) and a scan signal (SPWM), and
a constant current generator (112) which provides a driving current having a constant level to the light-emitting element (120) based on a constant current generation voltage (see (Vdata)), the constant current generator (112) including:
a bypass transistor (T13) including:
a gate electrode which receives a bypass gate signal (Test/Discharging) which has a pulse width greater than a pulse width of the scan signal (SPWM; see Fig. 4b);
a first electrode (i.e., a lower electrode) connected to a second initialization voltage line (VSS) which transmits a second initialization voltage (see (VSS)); and
a second electrode (i.e., an upper electrode) connected to the first electrode (i.e., the upper electrode) of the light-emitting element (120),
wherein the pulse width modulator (111) receives a first initialization voltage (Vinitial; see Page 8 through Page 11 for a general description of the pixel of Figures 4a and 4b; and in particular, see the highlighted paragraphs of Pages 8 through 11).
Kim does not explicitly show that a first electrode of the bypass transistor is connected to a second initialization voltage line that is separated from the lower power line to transmit the second initialization voltage, wherein the second initialization voltage is different from the low power voltage and the first initialization voltage.
However, in the same field of endeavor, Hyun discloses (see Fig. 10) a pixel circuit comprising a bypass transistor (M8) including a gate electrode which receives a bypass gate signal (Si), a second electrode connected to the first electrode (N4) of a light-emitting element (LD), and a first electrode connected to a second initialization voltage line (Vint2) which transmits a second initialization voltage (Vint2) and is separated from a lower power line (VSS) that is connected to a second electrode of the light-emitting element (LD), wherein a pulse width modulator (M3, M1, M4) receives a first initialization voltage (Vint1), and the second initialization voltage (Vint2) is different from the low power voltage (VSS) and the first initialization voltage (Vint1; see Page 8, Para. [0148] and [0151]-[0152]; and Page 9, Para. [0163]-[0164]). It is a goal of Hyun to provide a bypass transistor that allows for greater control of the driving conditions of a display device in order to improve driving performance and to reduce flicker and incorrect emission through a separated second initialization voltage line (again, see Page 9, Para. [0163]-[0164]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Kim with the teachings of Hyun, such that a first electrode of the bypass transistor is connected to a second initialization voltage line that is separated from the lower power line to transmit the second initialization voltage, wherein the second initialization voltage is different from the low power voltage and the first initialization voltage, as suggested by Hyun, in order to allow for greater control of the driving conditions of the display device in order to improve driving performance and to reduce flicker and incorrect emission through the separated second initialization voltage line.
As pertaining to Claim 17, Hyun discloses (see Fig. 10) that a voltage level of the second initialization voltage (Vint2) is higher than or equal to a voltage level of the lower power voltage (VSS; again, see Page 8, Para. [0151]-[0152]).
As pertaining to Claim 18, Kim discloses (see Fig. 4a) that the pulse width modulator (111) includes:
a first driving transistor (T3) including:
a gate electrode connected to a first node (i.e., a gate node);
a first electrode (i.e., an upper electrode) connected to a second node (i.e., an upper node); and
a second electrode (i.e., a lower electrode) connected to a third node (i.e., a lower node); and
a first write transistor (T2) including:
a gate electrode which receives the scan signal (SPWM);
a first electrode (i.e., a left electrode) connected to a data line (Vdata) which transmits the data voltage (see (Vdata)); and
a second electrode (i.e., a right electrode) connected to the second node (i.e., the upper node of (T3));
a first compensation transistor (T4) including:
a gate electrode which receives the scan signal (SPWM);
a first electrode (i.e., a right electrode) connected to the third node (i.e., the lower node of (T3)); and
a second electrode (i.e., a left electrode) connected to the first node (i.e., the gate node of (T3));
a first emission control transistor (T1) including:
a gate electrode which receives an emission control signal (Emi);
a first electrode (i.e., an upper electrode) which receives a first high power voltage (VDD_PWM); and
a second electrode (i.e., a lower electrode) connected to the second node (i.e., the upper node of (T3));
a second emission control transistor (T5) including:
a gate electrode which receives the emission control signal (Emi);
a first electrode (i.e., an upper electrode) connected to the third node (i.e., the lower node of (T3)); and
a second electrode (i.e., a lower electrode) connected to a fourth node (i.e., the gate node of (T8));
a first initialization transistor (T12) including:
a gate electrode which receives a first initialization gate signal (VST);
a first electrode (i.e., a lower electrode) which receives the first initialization voltage (Vinitial); and
a second electrode (i.e., an upper electrode) connected to the first node (i.e., the gate node of (T3)); and
a first capacitor (C1) including:
a first electrode (i.e., a left electrode) which receives a sweep signal (Sweep); and
a second electrode (i.e., a right electrode) connected to the first node (i.e., the gate node of (T3); again, see Page 8 through Page 11 for a general description of the pixel of Figures 4a and 4b; and in particular, see the highlighted paragraphs of Pages 8 through 11).
As pertaining to Claim 19, Kim discloses (see Fig. 4a) that the first driving transistor (T3) is a P-type transistor (see the paragraph at the top of Page 23).
Kim does not explicitly show that at least one of the first write transistor (T2), the first compensation transistor (T4), and the first initialization transistor (T12) is an N-type transistor. However, Kim explicitly discloses that the transistors of the pixel circuit (110) can be implemented using any structure or type of thin film transistors (TFTs; see the first two paragraphs at the top of Page 23). In this regard, one of ordinary skill in the art would have readily recognized that there are, in fact, only two types of thin film transistors (TFTs) that are readily available for implementation in the pixel circuit (110) of Kim, namely the N-type transistor and the P-type transistor. Further, the usage of N-type TFTs, P-type TFTs, and mixed N-type and P-type TFTs in pixel circuits has been fully implemented in the art, and the technical aspects of substitution of an N-type TFT for a P-type TFT, and vice-versa, would have been well understood by one of ordinary skill in the art.
Therefore, even though Kim schematically shows the transistors (T4, T2, T12) of the pulse width modulator (111) as P-type transistors, it would have been obvious to one of ordinary skill in the art that at least one of the first write transistor (T2), the first compensation transistor (T4), and the first initialization transistor (T12) of the pulse width modulator (111) could be implemented as an N-type transistor through a simple substitution of known and widely available elements, namely the simple substitution of an N-type transistor for a P-type transistor. Again, only two types of thin film transistors (TFTs) are readily available for implementation in the pixel circuit (110). Further, the substitution of an N-type transistor for a P-type transistor would have been well-within the knowledge of one having ordinary skill in the art, and the results of the substitution would have been a predictable implementation of a known element in the art to provide a switching and/or current driving function, and would have been consistent with the suggestions of Kim (again, see the first two paragraphs at the top of Page 23).
Further, Hyun discloses (see Fig. 10) that the pixel circuit (12) has a structure analogous to that of Kim, wherein the pixel circuit (12; see Page 4 through Page 5, Para. [0084]-[0091] and [0094]) comprises a combination of a driving transistor (M1) implemented as a P-type transistor while a write transistor (M2), connected to a first electrode of the driving transistor (M1), a compensation transistor (M4), connected to a second electrode of the driving transistor (M1), and a first initialization transistor (M7), are all implemented as N-type transistors (see Page 6, Para. [0106] and Page 8, Para. [0155]-[0157]). Hyun discloses that the utilization of mixed P-type and N-type transistors in the pixel circuit, including the implementation of a P-type driving transistor in combination with an N-type write transistor, an N-type compensation transistor, and an N-type initialization transistor can allow for a pixel circuit structure requiring greatly reduced power consumption while taking advantage of the inherent features of each of the N-type and the P-type transistor to improve display quality (see Para. [0106]-[0108]).
Therefore, again, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the combined teachings of Kim and Hyun provide for the first driving transistor (T3) as a P-type transistor; and at least one of the first write transistor (T2), the first compensation transistor (T4), and the first initialization transistor (T12) as an N-type transistor, in order to provide a pixel circuit structure that allows for greatly reduced power consumption while taking advantage of the inherent features of each of the N-type and the P-type transistor to improve display quality.
Claims 20-21 are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Hyun and further in view of Kim et al. (hereinafter “Kim2” US 2021 / 0210003).
As pertaining to Claim 20, Kim discloses (see Fig. 4a and Fig. 4b) that the constant current generator (112) further includes:
a second driving transistor (T8) including:
a gate electrode connected to the fourth node (i.e., a gate node);
a first electrode (i.e., an upper electrode) connected to a fifth node (i.e., an upper node); and
a second electrode (i.e., a lower electrode) connected to a sixth node (i.e., a lower node); and
a second write transistor (T7) including:
a gate electrode which receives a constant current generation scan signal (SCCG);
a first electrode (i.e., a left electrode) connected to the data line (Vdata) which transmits the constant current generation voltage (i.e., see (Vdata)); and
a second electrode (i.e., a right electrode) connected to the fifth node (i.e., the upper node of (T8));
a second compensation transistor (T9) including:
a gate electrode which receives the constant current generation scan signal (SCCG);
a first electrode (i.e., a right electrode) connected to the sixth node (i.e., the lower node of (T9)); and
a second electrode (i.e., a left electrode) connected to the fourth node (i.e., the gate node of (T9));
a third emission control transistor (T6) including:
a gate electrode which receives the emission control signal (Emi);
a first electrode (i.e., an upper electrode) which receives a second high power voltage (VDD_CCG); and
a second electrode (i.e., a lower electrode) connected to the fifth node (i.e., the upper node of (T8));
a fourth emission control transistor (T10) including:
a gate electrode which receives the emission control signal (Emi);
a first electrode (i.e., an upper electrode) connected to the sixth node (i.e., the lower node of (T8)); and
a second electrode (i.e., a lower electrode) connected to the first electrode (i.e., the upper electrode) of the light-emitting element (120);
a second initialization transistor (T11) including:
a gate electrode which receives a second initialization gate signal (VST);
a first electrode (i.e., a left electrode) which receives the first initialization voltage (Vinitial); and
a second electrode (i.e., a right electrode) connected to the fourth node (i.e., the gate node of (T8)); and
a second capacitor (C2) including:
a first electrode (i.e., a left electrode) which receives the first high power voltage (VDD_PWM); and
a second electrode (i.e., a right electrode) connected to the fourth node (i.e., the gate node of (T8); again, see Page 8 through Page 11 for a general description of the pixel of Figures 4a and 4b; and in particular, see the highlighted paragraphs of Pages 8 through 11).
Neither Kim nor Hyun explicitly discloses that the first electrode (i.e., the left electrode) of the second capacitor (C2) receives the second high power voltage (VDD_CCG).
However, in the same field of endeavor, Kim2 discloses (see Fig. 12) a pixel circuit (110) comprising a constant current generator (112) wherein a second capacitor (C2) is arranged with a second electrode (i.e. a lower electrode) connected to a fourth node (i.e., a gate node of a second driving transistor (T8)), and a first electrode (i.e., an upper electrode) that receives a first high power voltage (VDD_PWM) of a pulse width modulation circuit (111) and a second high power voltage (VDD_PAM; see Page 9 through Page 10, Para. [0189], [0192], [0197]-[0199], [0201]-[0203], and [0205]-[0207]). It is a goal of Kim2 to provide a means for improving color reproducibility for an input image signal and for more efficiently and stably driving a pixel (see Page 2, Para. [0072]-[0073]). Further, in this regard, Kim2 discloses a constant current generator analogous to that of Kim and Hyun, wherein the first electrode (i.e., upper electrode corresponding to the left electrode of Kim) of the second capacitor (C2) receives the second high power voltage (i.e., VDD_PAM corresponding to VDD_CCG of Kim) in order to compensate for any voltage discrepancies caused by the first high power voltage (i.e., VDD_PWM) of a pulse width modulation circuit and the second high power voltage (i.e., VDD_PAM or VDD_CCG) of a constant current generator (see Page 10 through Page 11, Para. [0218]-[0221] and Page 13, Para. [0274]-[0277]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Kim and Hyun with the teachings of Kim2, such that the first electrode (i.e., the left electrode) of the second capacitor (C2) receives the second high power voltage (VDD_CCG), as suggested by Kim2, in order to provide a pixel circuit that improves color reproducibility for an input image signal and allows for more efficient and stable driving while compensating for any voltage discrepancies caused by the first high power voltage of the pulse width modulation circuit and the second high power voltage of the constant current generator.
As pertaining to Claim 21, Kim discloses (see Fig. 4a) that the second driving transistor (T8) is a P-type transistor (see the paragraph at the top of Page 23).
Kim does not explicitly show that at least one of the second write transistor (T7), the second compensation transistor (T9), and the second initialization transistor (T11) is an N-type transistor. However, Kim explicitly discloses that the transistors of the pixel circuit (110) can be implemented using any structure or type of thin film transistors (TFTs; see the first two paragraphs at the top of Page 23). In this regard, one of ordinary skill in the art would have readily recognized that there are, in fact, only two types of thin film transistors (TFTs) that are readily available for implementation in the pixel circuit (110) of Kim, namely the N-type transistor and the P-type transistor. Further, the usage of N-type TFTs, P-type TFTs, and mixed N-type and P-type TFTs in pixel circuits has been fully implemented in the art, and the technical aspects of substitution of an N-type TFT for a P-type TFT, and vice-versa, would have been well understood by one of ordinary skill in the art.
Therefore, even though Kim schematically shows the transistors (T7, T9, T11) of the constant current generator (112) as P-type transistors, it would have been obvious to one of ordinary skill in the art that at least one of the second write transistor (T7), the second compensation transistor (T9), and the second initialization transistor (T11) of the constant current generator (112) could be implemented as an N-type transistor through a simple substitution of known and widely available elements, namely the simple substitution of an N-type transistor for a P-type transistor. Again, only two types of thin film transistors (TFTs) are readily available for implementation in the pixel circuit (110). Further, the substitution of an N-type transistor for a P-type transistor would have been well-within the knowledge of one having ordinary skill in the art, and the results of the substitution would have been a predictable implementation of a known element in the art to provide a switching and/or current driving function, and would have been consistent with the suggestions of Kim (again, see the first two paragraphs at the top of Page 23).
Further, Hyun discloses (see Fig. 10) that the pixel circuit (12) has a structure analogous to that of Kim, wherein the pixel circuit (12; see Page 4 through Page 5, Para. [0084]-[0091] and [0094]) comprises a combination of a driving transistor (M1) implemented as a P-type transistor while a write transistor (M2), connected to a first electrode of the driving transistor (M1), a compensation transistor (M4), connected to a second electrode of the driving transistor (M1), and a first initialization transistor (M7), are all implemented as N-type transistors (see Page 6, Para. [0106] and Page 8, Para. [0155]-[0157]). Hyun discloses that the utilization of mixed P-type and N-type transistors in the pixel circuit, including the implementation of a P-type driving transistor in combination with an N-type write transistor, an N-type compensation transistor, and an N-type initialization transistor can allow for a pixel circuit structure requiring greatly reduced power consumption while taking advantage of the inherent features of each of the N-type and the P-type transistor to improve display quality (see Para. [0106]-[0108]).
Therefore, again, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the combined teachings of Kim and Hyun provide for the second driving transistor (T8) as a P-type transistor; and at least one of the second write transistor (T7), the second compensation transistor (T9), and the second initialization transistor (T11) as an N-type transistor, in order to provide a pixel circuit structure that allows for greatly reduced power consumption while taking advantage of the inherent features of each of the N-type and the P-type transistor to improve display quality.
Claim 22 is rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Hyun in view of Kim2 and further in view of Hashimoto.
As pertaining to Claim 22, none of Kim, Hyun, and Kim2 explicitly discloses that a voltage level of the first high power voltage (VDD_PWM) of the pulse width modulator (111) is higher than a voltage level of the second high power voltage (VDD_CCG) of the constant current generator (112).
However, in the same field of endeavor, Hashimoto discloses (see Fig. 2 and Fig. 4) that it was well-known in the art before the effective filing date of the claimed invention to implement a pixel circuit (200) comprising a pulse width modulator (121) in combination with a constant current generator (122), wherein a first high power voltage (Vpwm) of the pulse width modulator (121) is different from, and higher than, a voltage level of a second high power voltage (Vpam) of the constant current generator (122; see Page 2, Para. [0023]-[0025] and [0028]; and see Page 5, Para. [0047]), in order to provide improved grayscale control using a hybrid gamma setting for the pulse width modulator and the constant current generator that improves optical performance without significantly increasing cost (see Page 1, Para. [0005] and Page 6, Para. [0072]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Jung and Hyun with the teachings of Hashimoto, such that a voltage level of the first high power voltage (VDD_PWM) of the pulse width modulator (111) is higher than a voltage level of the second high power voltage (VDD_CCG) of the constant current generator (112), in order to provide improved grayscale control using a hybrid gamma setting for the pulse width modulator and the constant current generator that improves optical performance without significantly increasing cost.
Response to Arguments
Applicant's arguments filed 26 May 2026 have been fully considered but they are either not fully persuasive or are moot because a new ground of rejection presented above does not rely on a combination of references applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Firstly, the applicant has argued that the teachings of Jung, as relied upon by the examiner in the prior Office Action, do not provide for a “driving transistor” implemented as a “P-type transistor” in combination with each of a “compensation transistor” and a “write transistor” implemented as “N-type transistors.” In this regard, the applicant has argued that even assuming that “only two types of TFTs (i.e., N-type and P-type) are available” in the art, the teachings of Jung suggest a “uniform transistor-type configuration” rather than a mixed transistor-type configuration, and the teachings of Jung neither disclose nor suggest the specific combination of P-type and N-type transistors as recited in at least independent Claims 1 and 23 (see Remarks at Pages 21 through 28). This argument is found persuasive. However, the examiner respectfully maintains that the combined teachings of Jung and Hyun, as newly relied upon in the above rejections, appear to suggest the claimed specific combination of P-type and N-type transistors.
Secondly, the applicant has argued that the combined teachings of Kim and Hyun, as relied upon by the examiner in the prior Office Action, fail to teach or fairly suggest a “pulse width modulator” that “receives a first initialization voltage” and a “second initialization voltage” that “is different from the low power voltage and the first initialization voltage,” as recited in independent Claim 16 (see Remarks at Pages 29 through 31). The examiner respectfully disagrees for the reasons provided in the above rejections with respect to at least Figures 10 and 11 of Hyun.
For at least these reasons, the rejection of Claims 1-26 is maintained.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Wang et al. (US 2022 / 0189402) discloses a pixel circuit implementing a self scan period and a display scan period.
Conclusion
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/JASON M MANDEVILLE/Primary Examiner, Art Unit 2623
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