Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1, 2, 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hong (US 20210274645), in view of Kuramochi (US 6143990).
Regarding claim 1, Hong discloses an optical module comprising:
a package (communication device 400, Fig. 7A) including a substrate (the printed circuit board 410) that includes a first signal wiring (the layer containing the signal wiring 463) formed on a first wiring layer (the signal wiring 463), and a first ground wiring (the ground plain 466) formed on a second wiring layer (the layer containing the ground plain 466) located below the first wiring layer (463); and
a flexible printed circuit board (the flexible printed circuit board 500) including a second signal wiring (signal wiring 523), and a second ground wiring (the ground plain 525 and 526) formed on the lower surface wiring layer,
wherein the second signal wiring includes a lead portion (the portion of 523 near 4001) protruding from the base layer in a first direction,
the second ground wiring includes a ground terminal (connection 5001, Fig. 6C, on ground layer 525) located further inside the flexible printed circuit board in the first direction than the lead portion,
the lead portion is connected to the first signal wiring (523), and
the ground terminal is connected to the first ground wiring (525).
Hong does not explicitly disclose a flexible printed circuit board including an upper surface wiring layer, a lower surface wiring layer, and a base layer disposed between the upper surface wiring layer and the lower surface wiring layer.
Kuramochi teaches a flexible printed circuit board (the flexible circuit board 20, Fig. 2 & 4) including an upper surface wiring layer (surface containing the signal wring layer 32), a lower surface wiring layer (the surface containing the ground wiring layer 42), and a base layer (layer 41) disposed between the upper surface wiring layer and the lower surface wiring layer.
It would have been obvious to one having skill in the art at the effective filing date of the invention to include several wiring layers in a circuit substrate in order to fit all the intended components in the limited space of the circuit substrate.
Regarding claim 2, Hong, in view of Kuramochi, discloses the claimed invention as set forth in claim 1. Kuramochi further suggests the first ground wiring (the ground wiring layer 42, Fig. 4) is located further outside the package (layer 42 is on a surface of the substrate 41) in the first direction than the first signal wiring (32).
Regarding claim 4, Hong, in view of Kuramochi, discloses the claimed invention as set forth in claim 1. Kuramochi further suggests the upper surface wiring layer (layer 32 is on the surface of layer 41) is located on the base layer (41), and the lower surface wiring layer (layer 42 is on the surface of layer 41) is located under the base layer.
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hong (US 20210274645), in view of Hong (US 20210274645).
Regarding claim 5, Ban discloses a flexible printed circuit board (5, Fig. 2D) comprising:
an upper surface wiring layer (layer containing the signal line 1);
a lower surface wiring layer (the layer containing the ground line 3); and
a base layer (layer 5) disposed between the upper surface wiring layer and the lower surface wiring layer,
wherein a second signal wiring (the signal line layer 1) is formed on the upper surface wiring layer, a second ground wiring (the ground line layer 3) is formed on the lower surface wiring layer.
Ban does not explicitly disclose the second signal wiring includes a lead portion protruding from the base layer in a first direction, the second ground wiring includes a ground terminal located further inside the flexible printed circuit board in the first direction than the lead portion, the lead portion is connected to a first signal wiring of a substrate provided in a package of an optical module, and the ground terminal is connected to the first ground wiring of the substrate.
Ban suggests the module is an optical module (see abstract).
Hong teaches the second signal wiring (signal wiring 523) includes a lead portion (the portion around 5231) protruding from the base layer (5101) in a first direction, the second ground wiring (ground wiring 525) includes a ground terminal (5001, Fig. 6C) located further inside the flexible printed circuit board in the first direction than the lead portion, the lead portion is connected to a first signal wiring (523) of a substrate (substrate 400) provided in a package of an optical module (an optical module suggested by Ban), and the ground terminal (5001) is connected to the first ground wiring (466) of the substrate (400).
It would have been obvious to one having skill in the art at the effective filing date of the invention to modify the shape of the substrates in order to electrically connect to substrate together to form a complete circuitry of the circuit board.
Allowable Subject Matter
Claim 3 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Reasons for Allowance
The following is an examiner’s statement of reasons for allowance:
Regarding claim 3, the prior art of record, taken alone or in combination, fails to teach or fairly suggest, in combining with other limitations recited in claim 1, a combination of limitations that the substrate includes a first dielectric layer located between the first wiring layer and the second wiring layer, and a second dielectric layer located on a side opposite to the first dielectric layer when viewed from the second wiring layer, an end portion of the first signal wiring in a direction opposite to the first direction is separated from the base layer of the flexible printed circuit board, and an end portion of the second ground wiring in the first direction is separated from the first dielectric layer. None of the reference art of record discloses or renders obvious such a combination.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Shirao (US 20220057256) discloses an optical module having a substrate (40, Fig. 2) connected to a flexible circuit board (70), having signal line (71), and ground line 73.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BINH B TRAN whose telephone number is (571)272-9289. The examiner can normally be reached M-F 8:00 AM - 6:00 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy J Dole can be reached at 571-272-2229. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BINH B TRAN/Primary Examiner, Art Unit 2847
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