DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1-20 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claim 8-14 of copending Application No. 18903324 (reference application). Although the claims at issue are not identical, they are not patentably distinct from each other because the instant claims encompass and/or broader than and/or obvious variation of the reference claims.
Independent claims 1, 8, and 15
Reference claim 8 recites a system comprising one or more processing devices configured to: compute a color value within a first color space for a first pixel based on color values of neighboring pixels; compute a first chrominance value within a second color space for the first pixel based on the computed color value; compute a luminance value within the second color space for the first pixel based on the first chrominance value; and convert the luminance value and first chrominance value to an output pixel value within a third color space. Thus, reference claim 8 recites the same four data dependent image demosaicing operations recited in each of instant independent claims 1, 8, and 15.
Instant claim 1
Instant claim 1 differs from reference claim 8 principally by assigning the four operations to first, second, third, and fourth circuits and by expressly reciting that the respective intermediate values are provided between the communicatively coupled circuits. The claimed partitioning would have been an obvious variation of the system of reference claim 8. Reference claim 8 expressly permits the operations to be performed by “one or more processing devices.” A person of ordinary skill would have understood that the successive, data dependent operations could predictably be allocated among respective functional circuit portions of the one or more processing devices: interpolation circuitry performing the color value computation; chrominance circuitry performing the chrominance computation; luminance circuitry performing the luminance computation; and transformation circuitry performing the output conversion. The expressly recited dependencies in reference claim 8 necessarily require the result of each upstream computation to be available to the corresponding downstream computation. Providing the computed color value to the circuitry calculating chrominance, providing the chrominance value to the circuitry calculating luminance, and providing the luminance and chrominance values to the circuitry performing output conversion would therefore have been a predictable implementation of the operations already required by reference claim 8. The reference specification confirms the scope of “one or more processing devices” by describing an image demosaic circuit containing raw interpolation, chroma estimation, luma estimation, and color space transformation circuit portions, with the output of one circuit provided as the input to another. See Fig. 1 and the associated description. The specification is relied upon to construe the scope and contemplated implementations of reference claim 8, not as a separate prior art reference. Accordingly, the first through fourth circuit allocation of instant claim 1 constitutes an obvious functional partitioning of the same processing device operations recited in reference claim 8 and does not produce a different image processing function or result.
Instant claim 8
Instant claim 8 differs from reference claim 8 principally by expressly reciting: a memory device; and one or more circuit groups communicatively coupled to the memory device, rather than “one or more processing devices.” These differences do not establish patentable distinctness. A circuit group is an implementation of a processing device or a functional portion thereof. Providing memory communicatively coupled to image processing circuitry for storing input pixel values, intermediate chrominance and luminance values, output values, filter values, and processing instructions would have been a predictable implementation of the system claimed in reference claim 8. The reference specification confirms that the system encompassed by reference claim 8 may include memory communicatively coupled to an image-demosaic circuit and its constituent circuits or circuit groups. Figs. 1 and 6 and the associated description. Accordingly, instant claim 8 merely recites a memory coupled circuit group implementation of the same processing device system claimed in reference claim 8.
Instant claim 15
Instant claim 15 differs from reference claim 8 principally by reciting a memory device and allocating the operations between: a first circuit group that computes and provides the color value; and a second circuit group that computes chrominance, computes luminance, and performs output conversion. This two group allocation would have been an obvious variation of the “one or more processing devices” of reference claim 8. Reference claim 8 permits more than one processing device, and its data dependencies establish a natural processing boundary between the neighbor based interpolation operation and the subsequent chrominance, luminance, and output-conversion operations. The reference specification further confirms that the processing devices encompassed by reference claim 8 may be implemented as first and second communicatively coupled circuit groups and that outputs may be transferred directly or through memory. Fig. 1 and the associated description. Grouping the first operation separately from the three downstream operations constitutes no more than a predictable allocation of the functions already required by reference claim 8 and does not change the underlying image demosaicing process or its result.
Dependent claims
Instant claims 2, 9, and 16 further require determining a gradient direction and computing the color value from neighboring pixels along that gradient direction. Reference claim 9 recites the same additional operations. The assignment of those operations to the first circuit or first circuit group in the instant claims is an obvious functional allocation within the processing devices of reference claim 9. Therefore, instant claims 2, 9, and 16 are not patentably distinct from reference claim 9.
Instant claims 3, 10, and 17 further require applying a polyphase filter to the first chrominance value to obtain a smoothed chrominance value. Reference claim 10 recites the same polyphase filter operation. Assigning that operation to a particular circuit or circuit group does not alter the operation or its result. Therefore, instant claims 3, 10, and 17 are not patentably distinct from reference claim 10.
Instant claims 4, 11, and 18 further require modifying at least one value of the polyphase filter based on satisfaction of an outlier criterion. Reference claim 11 recites the same additional limitation. Therefore, instant claims 4, 11, and 18 are not patentably distinct from reference claim 11.
Instant claims 5, 12, and 19 further require modifying the luminance value using a luma zipper filter based on neighboring luminance values, a spatial filter kernel, and a range kernel. Reference claim 12 recites the same luma zipper filter limitation. Therefore, instant claims 5, 12, and 19 are not patentably distinct from reference claim 12.
Instant claims 6, 13, and 20 further require determining a gradient direction and gradient strength and modifying the luminance value based on the determined direction and strength. Reference claim 13 recites the same additional operations. Therefore, instant claims 6, 13, and 20 are not patentably distinct from reference claim 13.
Instant claims 7 and 14 further require applying a transformation matrix to the luminance and chrominance values during conversion to the output pixel value. Reference claim 14 recites the same transformation-matrix limitation. Therefore, instant claims 7 and 14 are not patentably distinct from reference claim 14.
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Allowable Subject Matter
Claims 1-20 would be allowable if rewritten, amended, or by filing a terminal disclaimer to overcome the rejection(s), set forth in this Office action.
The following is a statement of reasons for the indication of allowable subject matter:
The prior art of record, including Sun et al. ("A hybrid demosaicking algorithm for area scan industrial camera based on fuzzy edge strength and residual interpolation." IEEE Transactions on Industrial Informatics 16, no. 6 (2019): 4038-4048.); Gunturk et al. ("Demosaicking: color filter array interpolation." IEEE Signal processing magazine 22, no. 1 (2005): 44-54); Lee et al. ("A novel high dynamic range image compression scheme of color filter array data for the digital camera pipeline." In 2012 19th IEEE International Conference on Image Processing, pp. 325-328. IEEE, 2012.); Siddiqui et al. (US 20190141299 A ); and Chiu et al., (US 20050275736) does not teach or suggest the complete ordered processing of a same pixel in which an interpolated color value is used to compute chrominance, that chrominance is used to compute luminance, and the resulting luminance and chrominance are converted to an output pixel in another color space. .
Sun and Gunturk disclose color interpolation and color difference or luminance/chrominance processing, but do not disclose calculating luminance from the previously calculated chrominance value.
Lee discloses interpolated green, calculation of R−G and B−G, and calculation of luminance using those color differences, but does not disclose the complete downstream conversion and claimed circuit arrangement.
Siddiqui discloses neighbor based CFA resampling and, in a separate embodiment, chrominance extraction, chrominance dependent luminance extraction, and output image creation, but does not disclose those features combined in the claimed ordered arrangement.
Chiu discloses conversion of an intermediate Y,B−G,R−G representation to YCbCr, but does not disclose the preceding CFA interpolation and complete ordered pipeline.
The prior art further fails to disclose or suggest that processing in the respective claimed hardware arrangements: four communicatively coupled functional circuits in claim 1, memory coupled circuit group or groups in claim 8, and the first and second circuit group allocation recited in claim 15.
Conclusion
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/WASSIM MAHROUKA/Primary Examiner, Art Unit 2665
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