DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
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Claims 1-3, 8-9 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-4 of U.S. Patent No. 12,131,783. Although the claims at issue are not identical, they are not patentably distinct from each other because:
APPLICATION
US PAT. 12,131,783
Claim 1:
A memory device comprising:
a memory array; and
control logic, operatively coupled with the memory array, to perform operations comprising:
identifying a plurality of wordlines at an initial voltage different from a pass-through voltage; and
causing an early discharge sequence to be performed with respect to the plurality of wordlines, wherein the early discharge sequence comprises ramping at least a first set of wordlines of the plurality of wordlines from the initial voltage to a ramping voltage different from the pass-through voltage.
Claim 2:
wherein the initial voltage is a pass-through reset voltage
Claim 1:
A memory device comprising:
a memory array; and
control logic, operatively coupled with the memory array, to perform operations comprising:
initiating a read recovery process with respect to a plurality of wordlines at an initial voltage, wherein the initial voltage is a pass-through reset voltage (Vpass_rst) having a magnitude less than a pass-through voltage (Vpass); and
causing an early discharge sequence to be performed on a first set of wordlines of the plurality of wordlines during the read recovery process to alleviate latent read disturb, wherein the early discharge sequence comprises ramping the first set of wordlines from the initial voltage to a ramping voltage while maintaining a second set of wordlines of the plurality of wordlines at the initial voltage, and wherein the ramping voltage is different from Vpas.
Claim 3: wherein the ramping voltage is a ground voltage.
Claim 2:
wherein the ramping voltage is a ground voltage.
Claim 8:
A method comprising:
identifying a plurality of wordlines in a memory device at an initial voltage different from a pass-through voltage; and
causing an early discharge sequence to be performed with respect to the plurality of wordlines, wherein the early discharge sequence comprises ramping at least a first set of wordlines of the plurality of wordlines from the initial voltage to a ramping voltage different from the initial voltage and the pass-through voltage.
Claim 9: wherein the initial voltage is a pass-through reset voltage.
Claim 3:
A method comprising:
initiating a read recovery process associated with a block of a memory array, wherein the block comprises a plurality of wordlines at an initial voltage, wherein the initial voltage is a pass-through reset voltage (Vpassrst) having a magnitude less than a pass-through voltage (Vpass); and
causing an early discharge sequence to be performed on a first set of wordlines of the plurality of wordlines during the read recovery process to alleviate latent read disturb, wherein the early discharge sequence comprises ramping the first set of wordlines from the initial voltage to a ramping voltage while maintaining a second set of wordlines of the plurality of wordlines at the initial voltage, and wherein the ramping voltage has a magnitude that is less than or equal to a ground voltage.
Claim 10: wherein the ramping voltage is a ground voltage.
Claim 4:
wherein the ramping voltage is a ground voltage.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 5-10, 12-16, and 18-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Mitsuhira et al. (US Pat. 9,830,994).
Regarding claims 1 and 8, Fig. 8E of Mitsuhira discloses a memory device comprising:
a memory array [501, Fig. 5]; and
control logic [550, Fig. 5], operatively coupled with the memory array, to perform operations comprising:
identifying a plurality of wordlines at an initial voltage [VREAD] different from a pass-through voltage [Vpass, Fig. 7F. In addition, since applicant does not specifically define what a pass-through voltage is, any voltage greater than threshold but less than programming voltage can be considered a pass-through voltage]; and
causing an early discharge sequence [col. 17 lines 38 to 47] to be performed with respect to the plurality of wordlines [WLn-1, WL2, WL1, WL0], wherein the early discharge sequence comprises ramping at least a first set of wordlines [WLn-1, WL2] of the plurality of wordlines from the initial voltage [VREAD] to a ramping voltage [0v] different from the pass-through voltage [Vpass].
Regarding claims 2, 9 and 16, Fig. 8F of Mitsuhira discloses wherein the initial voltage is a pass-through reset voltage [according to application, specification, a pass-through reset voltage is a voltage less than programming voltage but greater than threshold voltage. VREAD meets that limitation].
Regarding claims 3 and 10, Fig. 8F of Mitsuhira discloses wherein the ramping voltage is a ground voltage [0V].
Regarding claims 5, 12, and 18, Fig. 8F of Mitsuhira discloses wherein: the early discharge sequence is a staggered early discharge sequence; and causing the staggered early discharge sequence to be performed comprises: causing the first set of wordlines [WL2] to be ramped from the initial voltage [VREAD] to the ramping voltage [0V]; and after causing the first set of wordlines [WL2] to be ramped from the initial voltage [VREAD] to the ramping voltage [0V], causing a second set of wordlines [WL1], adjacent to the first set of wordlines [WL2], to be ramped from the initial voltage [VREAD] to the ramping voltage [0V].
Regarding claims 6, 13, and 19, Fig. 8F of Mitsuhira discloses wherein: the early discharge sequence is a two-step early discharge sequence; and causing the two-step early discharge sequence to be performed comprises: causing the first set of wordlines [WL2] to be ramped from the initial voltage [VREAD] to an intermediate voltage [VX] greater than the ramping voltage [0V]; and after causing the first set of wordlines to be ramped from the initial voltage to the intermediate voltage, causing the first set of wordlines to be ramped from the intermediate voltage [VX] to the ramping voltage [0V].
Regarding claims 7, 14, and 20, Fig. 8F of Mitsuhira discloses wherein: the early discharge sequence is a gradient early discharge sequence [as shows in Fig. 8F, the sequence occurs in a gradient way]; and causing the gradient early discharge sequence to be performed comprises: causing the first set of wordlines [WL2] to be ramped from the initial voltage [VREAD] to an intermediate voltage [VX] greater than the ramping voltage [0V]; after causing the first set of wordlines [WL2] to be ramped from the initial voltage [VREAD] to the intermediate voltage [VX], causing a second set of wordlines [WL1], adjacent to the first set of wordlines [WL2], to be ramped from the initial voltage [VREAD] to the intermediate voltage [VX]; and after causing the second set of wordlines [WL1] to be ramped from the initial voltage [VREAD] to the intermediate voltage [VX], causing the first set of wordlines [WL2] to be ramped from the intermediate voltage [VX] to the ramping voltage [0V].
Regarding claim 15, Fig. 8F of Mitsuhira discloses a memory device comprising:
a memory array [501, Fig. 5]; and
control logic [550, Fig. 5], operatively coupled with the memory array [501], to perform operations comprising:
identifying a plurality of wordlines [WL0 to WLn, Fig. 8F] at a pass-through reset voltage [VREAD. According to application, a pass-through reset voltage is a voltage that is greater than a threshold voltage but less than programming voltage. VREAD meets that limitation]; and
causing an early discharge sequence [col. 17 lines 38 to 47] to be performed with respect to the plurality of wordlines [WL0 TO WLn], wherein the early discharge sequence comprises ramping at least a first set of wordlines [WL2] of the plurality of wordlines from the pass-through reset voltage [VREAD] to at least one of:
a ramping voltage [0V] different from the pass-through reset voltage [VREAD] and a pass-through voltage; or
an intermediate voltage [VX] different from the pass-through voltage [Vpass] and having a magnitude between the pass-through reset voltage [VREAD] and the ramping voltage [0V].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4, 11, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Mitsuhira et al. (US Pat. 9,830,994) in view of Oh (US Pat. 10,490,244).
Regarding claims 4, 11, and 17, Mitsuhira discloses all claimed invention, but does not wherein the ramping voltage is a negative voltage. However, Fig. 13A of Oh discloses wherein the ramping voltage is a negative voltage [Vnega].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the teachings of Oh’s memory device having discharging operation to the teachings of Mitsuhira’s memory having discharge operation such that Mitsuhira WL ramping to a negative voltage in a manner according to Ohs teachings for the purpose of compensating for the positive fringing field based on the program voltage [col. 16, lines 11 to 28].
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANTHAN T TRAN whose telephone number is (571)272-8709. The examiner can normally be reached MON-FRI, 9AM-5:00PM.
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/ANTHAN TRAN/Primary Examiner, Art Unit 2825
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