DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-7, 9-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Dabral et al. (US 2019/0319626 A1), and further in view of Jain et al. (US 11,133,256 B2).
Regarding claim 1, Dabral teaches a computing system comprising:
a compute chiplet arranged on a substrate and comprising an integrated circuit configured to perform logic operations or computations (Fig. 14, logic chips 104);
peripheral chiplets arranged on the substrate in a neighborhood around the compute chiplet, the peripheral chiplets including a nearest-neighbor chiplet and a next-nearest-neighbor chiplet, the nearest-neighbor chiplet being adjacent to the compute chiplet without a chiplet therebetween, and the nearest-neighbor chiplet being between the next-nearest-neighbor chiplets and the compute chiplet (memory chips 102 are arranged around the logic chip 104. In addition, the other logic circuits 104 can be considered peripheral chiplets); and
one or more embedded logic bridges embedded in the substrate, comprising active circuitry providing communications between the compute chiplet and the next-nearest-neighbor chiplet (logic bridge 150 and communication bar 160 are embedded in the substrate and comprises active circuitry, see ¶0069 and Fig. 15).
Dabral does not explicitly teach the one or more embedded logic bridges embedded in the packaging substrate.
Jain teaches the one or more embedded logic bridges embedded in the packaging substrate (Fig. 1, embedded bridge 110 is embedded in a packaging substrate 102. The embedded bridge coupled between two or more ID dies).
Thus, it would have been obvious to a person with the ordinary skill in the art before the effective filing date of the claimed invention to use Embedded Multi-die Interconnect Bridge (EMIB) for the reason the EMIB replaces expensive large silicon interposers which helps reduce productions costs.
Regarding claim 2, Dabral further teaches the computing system of claim 1, wherein the nearest-neighbor chiplet is in a first rank with respect to the compute chiplet and the next-nearest-neighbor chiplet is in a second rank with respect to the compute chiplet, and the second rank is farther from the compute chiplet than the first rank (Fig. 14).
Regarding claim 3, Dabral further teaches the computing system of claim 1, wherein: the one or more embedded logic bridges include an on-chip network comprising metal oxide semiconductor field effect transistors (active silicon 1504 comprises logic circuits which comprises MOS transistors. ¶0069).
Regarding claim 4, Dabral further teaches the computing system of claim 1, wherein: the one or more embedded logic bridges include physical-layer communication circuitry that drive signals from the next-nearest-neighbor chiplet to the compute chiplet (¶0088).
Regarding claim 5, Dabral further teaches the computing system of claim 4, wherein: the one or more embedded logic bridges include other physical-layer communication circuitry that drive other signals from the compute chiplet to the next-nearest-neighbor chiplet (¶0088).
Regarding claim 6, Dabral further teaches the computing system of claim 5, wherein: the one or more embedded logic bridges include a controller that processes data from the next-nearest-neighbor chiplet before the data is converted to the signals that are driven to the compute chiplet by the physical-layer communication circuitry; and the one or more embedded logic bridges include another controller that processes other data from the compute chiplet before the data is converted to the other signals that are driven to the next-nearest-neighbor chiplet by the other physical-layer communication circuitry (memory bar 150 comprises controllers, ¶0088).
Regarding claim 7, Dabral further teaches the computing system of claim 1, further comprising an interposer between the peripheral chiplets and the one or more embedded logic bridges, the interposer consisting of passive circuitry (¶0085).
Regarding claim 9, Dabral further teaches the computing system of claim 1, wherein the next-nearest-neighbor chiplet is a high bandwidth memory stack of dynamic random access memory (¶0087).
Regarding claim 10, Dabral further teaches the computing system of claim 9, wherein: the nearest-neighbor chiplet is another high bandwidth memory stack of dynamic random access memory; the one or more embedded logic bridges include first physical-layer communication circuitry that drive signals from the next-nearest-neighbor chiplet to the compute chiplet; the one or more embedded logic bridges include second physical-layer communication circuitry that drive signals from the nearest-neighbor chiplet to the compute chiplet; and the one or more embedded logic bridges include third physical-layer communication circuitry that drive the signals from the compute chiplet to the next-nearest-neighbor chiplet and the nearest-neighbor chiplet (Fig. 10A, Fig. 10B and ¶0087).
Regarding claim 11, Dabral further teaches the computing system of claim 9, wherein the one or more embedded logic bridges includes a first controller and a first physical layer near the next-nearest-neighbor chiplet, the first physical layer being configured to drive signals from the high bandwidth memory stack to the compute chiplet; and the one or more embedded logic bridges includes a second controller and a second physical layer near the compute chiplet, the second physical layer being configured to drive the signals from the compute chiplet to the next-nearest-neighbor chiplet, the second controller and the second physical layer being a die-to-die controller and a die-to-die physical layer, respectively (Fig. 10A, Fig. 10B and ¶0087 to ¶0088).
Regarding claim 12, Dabral further teaches the computing system of claim 1, wherein the next-nearest-neighbor chiplet is another compute chiplet or an I/O chiplet, and the I/O chiplet is configured to provide a serializer-deserializer based interface or double data rate based interface (Fig. 14, the chiplet next to the logic chip 104 can be another computing chip 104. The chips can be double rate based interface (DDR), see ¶0049. In addition, the communication bar can comprise serializer and deserializer, see ¶0073).
Regarding claim 13, Dabral further teaches the computing system of claim 12, wherein the one or more embedded logic bridges includes a first controller and a first physical layer near the next-nearest-neighbor chiplet, the first physical layer being configured to drive signals from the next-nearest-neighbor chiplet to the compute chiplet, the first controller and the first physical layer being a die-to-die controller and a die-to-die physical layer, respectively; and the one or more embedded logic bridges includes a second controller and a second physical layer near the compute chiplet, the second physical layer being configured to drive the signals from the compute chiplet to the next-nearest-neighbor chiplet, the second controller and the second physical layer being a die-to-die controller and a die-to-die physical layer, respectively ( Fig. 10A, Fig. 10B and ¶0087 to ¶0088).
Regarding claim 14, Dabral further teaches the computing system of claim 1, wherein the active circuitry includes components that extend a signal distance that communication signals can be sent between the compute chiplet and the next-nearest-neighbor chiplet (repeaters and other circuitries in the communication bar 160 and memory bar 150 extend a signal distance, ¶0069).
Regarding claim 15, Dabral further teaches the computing system of claim 1, wherein: the next-nearest-neighbor chiplet is spaced from the compute chiplet by at least a characteristic length of the peripheral chiplets; and the active circuitry extends a range of communications between the compute chiplet and the peripheral chiplets to be at least twice the characteristic length, wherein the characteristic length of the peripheral chiplets is a width or a length of one of the peripheral chiplets or the characteristic length is 6 mm, 8 mm, or 10 mm. (Fig. 14 and Fig. 15, the active circuit in the communication bar 160 and the memory bus 150 will extend a range of communication between the logic circuit 104 and the memory chips 102, where is the length is the length of the peripheral chips 102).
Regarding claim 16, Dabral further teaches the computing system of claim 1, wherein the active circuitry includes an amplifier that is configured to increase an amplitude of communication signals to compensate for signal attenuation over a distance greater than 8 mm, 10 mm, 12 mm, or 15 mm (The memory bar 150 and communication bar 160 comprises cache which sense and amplify data transferred through the bus, ¶0069).
Regarding claim 17, Dabral further teaches the computing system of claim 1, wherein the active circuitry includes a repeater that detects signals and then resends the signals (¶0069).
Regarding claim 18, Dabral further teaches the computing system of claim 1, wherein: the peripheral chiplets include an additional chiplet, the nearest-neighbor chiplet and the next-nearest-neighbor chiplet being arranged between the additional chiplet and the compute chiplet; and the nearest-neighbor chiplet is in a first rank with respect to the compute chiplet, the next-nearest-neighbor chiplet is in a second rank with respect to the compute chiplet, the additional chiplet is in a third rank with respect to the compute chiplet, and the third rank is farther from the compute chiplet than the second rank, and the second rank is farther from the compute chiplet than the first rank (Fig. 14).
Regarding claim 19, Dabral further teaches the computing system of claim 1, wherein: the compute chiplet is configured to perform a memory intensive task, and the peripheral chiplets include more HBMs than can fit along a shoreline of the compute chiplet; and the memory intensive task is one or more of (i) a high-performance computing task; (ii) a graphics processing task; or (iii) a machine learning task (memory system can be used for high performance computing task or graphic processing task, ¶0045).
Regarding claim 20, Dabral further teaches the computing system of claim 19, wherein the memory intensive task is the machine learning task and the machine learning task includes a calculation selected from the group consisting of a weighted sum calculation; rectified linear unit calculation, a matrix multiplication; an add and normalize calculation; and a multiheaded attention calculation (memory system taught by Dabral is for a multi-chip system which comprises a plurality of logic chips (CPU) which can perform the intended use functions such as weighted sum calculation).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Dabral as applied to claim 1 above.
Regarding claim 8, Dabral further teaches the computing system of claim 1, wherein: the active circuitry includes high-speed communication circuitry providing communication speeds greater than or equal to 1 Gbps, and the high-speed communication circuitry is configured to drive signals from the compute chiplet at least 10 mm without an amplitude of the signals being attenuated below a predefined detection threshold (Dabral teaches active circuitry in the memory bar 150 and the communication bar 160 which are used to maintain the transferred signal between the chips without drop in the amplitude of the signals. Where each memory chip is a few mm in size, ¶0067 and ¶0069. In addition, Dabral teaches the active circuitry are used to provide a high bandwidth communication between the chips. Dabral did not explicitly teach the speed to be greater than 1 Gbps. However, it is well-known in the art the current standards for high bandwidth memory (HBM) to have a higher speed than 1 Gbps and it would have been to any person in the art to maintain the current standards set by JEDEC. The communication bar comprises repeaters which amplify signal across the high speed communication bar to prevent reduction in the signal).
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHAMDAN N ALROBAIE whose telephone number is (571)270-7099. The examiner can normally be reached Monday to Thursday (8AM till 6PM).
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/Khamdan N. Alrobaie/ Primary Examiner, Art Unit 2824
