Prosecution Insights
Last updated: July 17, 2026
Application No. 18/903,799

Device and Method for Signal Retiming

Non-Final OA §102§103
Filed
Oct 01, 2024
Priority
Nov 21, 2023 — provisional 63/601,380
Examiner
PANWALKAR, VINEETA S
Art Unit
2635
Tech Center
2600 — Communications
Assignee
Microsemi Soc Corp.
OA Round
2 (Non-Final)
91%
Grant Probability
Favorable
2-3
OA Rounds
5m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 91% — above average
91%
Career Allowance Rate
575 granted / 631 resolved
+29.1% vs TC avg
Moderate +9% lift
Without
With
+8.6%
Interview Lift
resolved cases with interview
Typical timeline
2y 2m
Avg Prosecution
13 currently pending
Career history
646
Total Applications
across all art units

Statute-Specific Performance

§101
4.0%
-36.0% vs TC avg
§103
60.5%
+20.5% vs TC avg
§102
8.5%
-31.5% vs TC avg
§112
9.5%
-30.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 631 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Arguments Applicant’s arguments with respect to claim(s) 10-15 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. It is pointed out that claim 10 does not have the limitation “second clock from the second portion” that applicant is arguing, thus previously presented Miro Parades (US 20180013545 A1) anticipates claim 10. In the previous rejection, examiner inadvertently clubbed the rejection of claim 10 with that of claim 1, however, the scope of claim 10 is broader than that of claim 1 , specifically, claim 10 does not state that the first clock is received from the first portion and the second clock is received from the second portion. Thus, Miro-Parades anticipates claim 10, including the amended limitations. However, since the rejection is now based on 35 USC 102 rather than 35 USC 103, this action is made non-final. Claims 1-9, 16-22 are allowed in light of the amendments. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim 10 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by previously cited Miro Parades (US 20180013545 A1), hereinafter, Miro Parades. Regarding claim 10: Miro Parades discloses a device (Fig. 1 A) comprising: a first clock (Figs. 1A, 3A, 4A, clk 109) synchronizing a first portion (Fig. 1A, 102) of an integrated circuit (IC) (Paragraphs [0033]. [0034], [0041], [0051], [0078]; portion 102 comprises a synchronous device for synchronizing with the clock 109, i.e. claimed first clock synchronizing a first portion; the communication link 100 can be a link between two portions within same integrated circuit); a retiming circuit (Figs. 1A, 3A, 112, including flip flop 310 and stability detector 302 shown in Fig. 4A; see paragraphs [0040], [0041], [0050], [0051]) to generate a delayed clock from a second clock (Fig. 4A, delay 408 introduces a delay value) (Paragraph [0051]); second clock is clock 109 as provided to circuit 104) synchronizing a second portion of the IC (Paragraphs [0035], [0078]; the second portion 104 comprises a synchronous device 112 synchronizing with clock 109); a validation circuit (Figs. 3A, 4A, flip flops 301 and 406 ) (Paragraphs [0050], [0051]) including: a data input (Fig. 4A, data 107; paragraphs [0041], [0051]); a first sample memory (Fig. 4A,flip-flop 301) coupled to the data input, the first sample memory to sample the data input with the first clock (Paragraph [0040]); a second sample memory (Fig. 4A, flip-flop 406) coupled to the data input, the second sample memory to sample the data input with the delayed second clock (Paragraph [0051]); and a comparing circuit (Fig. 4A, XOR gate 412 ) to compare an output of the first sample memory with an output of the second sample memory (Paragraphs [0050], [0051]). Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Miro Parades in view of Pozzoni et al. (US 20240356537 A1), hereinafter, Pozzoni. Regarding claim 11: Miro Parades further discloses the device wherein the validation circuit needs a calibration mode (Paragraph [0075]). However, Miro Parades fails to explicitly disclose the validation circuit is to generate a test pattern to sequentially set a data value on the data input in the calibration mode. Pozzoni discloses a calibration circuit that generates data patterns (claimed test pattern) and sequentially sets a data value of a data input (Paragraphs [0036]-[0040], abstract; calibration circuit that generates data patterns (claimed test pattern) and sequentially supplies the patterns to the circuit i.e. sets the data value to one pattern and then sequentially shifted pattern). It would have been obvious to one of ordinary skill in the art to modify Miro-Parades’ validation circuit in calibration mode to generate a test pattern to sequentially set a data value on the data input in the calibration mode as disclosed by Pozzoni. It would have been obvious to do so in order to perform effective calibration. Allowable Subject Matter Claims 1- 9, 16-22 are allowed. Claims 12-15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to VINEETA S PANWALKAR whose telephone number is (571)272-8561. The examiner can normally be reached M-F 9:00am-5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, David C. Payne can be reached at 571-272-3024. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /VINEETA S PANWALKAR/Primary Examiner, Art Unit 2635
Read full office action

Prosecution Timeline

Oct 01, 2024
Application Filed
Dec 05, 2025
Non-Final Rejection mailed — §102, §103
Feb 26, 2026
Interview Requested
Mar 03, 2026
Examiner Interview Summary
Mar 03, 2026
Applicant Interview (Telephonic)
Mar 09, 2026
Response Filed
May 28, 2026
Examiner Interview (Telephonic)
Jun 05, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

2-3
Expected OA Rounds
91%
Grant Probability
99%
With Interview (+8.6%)
2y 2m (~5m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 631 resolved cases by this examiner. Grant probability derived from career allowance rate.

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