Prosecution Insights
Last updated: October 01, 2026
Application No. 18/903,955

APPLICATION PROGRAMMING INTERFACE TO DECOMPRESS INFORMATION

Non-Final OA §102§103
Filed
Oct 01, 2024
Examiner
NGUYEN, LINH V
Art Unit
2845
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
NVIDIA Corporation
OA Round
3 (Non-Final)
89%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
92%
With Interview

Examiner Intelligence

Grants 89% — above average
89%
Career Allowance Rate
1075 granted / 1206 resolved
+21.1% vs TC avg
Minimal +2% lift
Without
With
+2.4%
Interview Lift
resolved cases with interview
Fast prosecutor
1y 10m
Avg Prosecution
22 currently pending
Career history
1230
Total Applications
across all art units

Statute-Specific Performance

§101
3.8%
-36.2% vs TC avg
§103
45.6%
+5.6% vs TC avg
§102
38.9%
-1.1% vs TC avg
§112
4.9%
-35.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1206 resolved cases

Office Action

§102 §103
DETAILED ACTION 1. This office action is in response to communication filed on 08/31/2026. Claims 1, 6, 8. 13, and 15 have been amended. Claims 1-20 are pending on this application. Response to Arguments 2. Applicant’s arguments with respect to amended independent claims 1, 8 and 15 have been considered but they are not persuasive. Under remarks, applicant argued “Rasmussen does not teach an API, the reference also does not teach an identifier with respect to identifying a parameter indicating a compression algorithm. Additionally, Rasmussen is further silent with respect to scheduling a circuit to decompress the received data based on the parameter indicated in the API call.”. Examiner respectfully disagrees with the following: A parameter is construed as a limit, boundary, or defining characteristic that sets how a system, function, or process works. Schedule is construed as a plan or list that shows the times when specific events, tasks, or transportation services are supposed to happen. Fig. 1, Fig. 2 and Fig. 5 of Rasmussen teach an API (application program interface between Fig. 2 and Fig. 5), comprising an identifier (compression method identifier 520 in Fig. 5) with respect to identifying a parameter (limit, boundary , or defining characteristic of compressed data history 300) indicating a compression algorithm (221a…212b in Fig. 2) and to scheduling a circuit (plan or list that indicate time to select of switching circuit in Fig. 5 to perform decompression function or task) to decompress (512a…512c in Fig. 5) the received data (400 in Fig. 5) based on the parameter indicated (limit, boundary ,or defining characteristic of compressed data history 300) in the API call (application interface between Fig. 2 and Fig. 5 call for decompression the compressed data (400). From above, the rejection of claims 1-20 are sustained from references cited in previous office action. Claim Rejections - 35 USC § 102 3. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 4. Claims 1-2, 4-9,11-18 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Rasmussen Pub. No. 2003/0090397. Regarding claim 1. Fig. 1, Fig. 2 and Fig. 5 of Rasmussen discloses one or more processors (Fig. 2 and Fig. 5) comprising: circuitry (circuitry of Fig. 2 and Fig. 5) to, in response to perform an application programming interface (application program interface between Fig. 2 and Fig. 5) call (call for compression and decompression): identify (520 in Fig. 5) a parameter (limit, boundary , or defining characteristic of compressed data history 300) indicating a compression algorithm (212a….212n in Fig. 2) used to compress received data (210 in Fig. 2), wherein the API (application program interface between Fig. 2 and Fig. 5) call comprises an identifier (520 in Fig. 5) corresponding to the parameter; and schedule one or more circuits (plan or list that indicate time to select of switching circuit in Fig. 5 to perform decompression function or task) to decompress based, at least, on the parameter (limit, boundary , or defining characteristic of compressed data history 300)); and stored decompressed data (outputs of 512a,…512n in Fig. 5) in one or more storage locations (514a…514n in Fig. 5) indicated by a user (Fig. 1 HOST) . Regarding claim 2. The one or more processors of claim 1, Fig. 5 further comprising a copy engine (copy engine of 138 for transfer a copy data of 510 to each decompressor ) having data transfer circuits (data transfer select circuits of 138) that facilitate data transfer between a source (510) and a destination (514a…514n), wherein the one or more circuits (512a…512n) comprises a portion (portion of 512a…512v) of the copy engine (138) is designated to perform decompression (designated of 512a….512n). Regarding claim 4. The one or more processors of claim 1, Fig. 1, Fig. 2 and Fig. 5 further discloses wherein the API (115 in Fig. 1) causes the received data (400 in Fig. 5) to be decompressed (138), at least in part, by transferring compressed data (400) to the one or more circuits (512a…512n), wherein the one or more circuits (512a..512n) comprises hardware (hardware of 512a…512n) dedicated solely (selection) to performing decompression (138). Regarding claim 5. The one or more processors of claim 1, Fig. 2 and Fig. 5 further disclose wherein the one or more circuits (512a…512n) comprises a plurality of decompression circuits (51a…512n), and wherein the received data (400) is divided into a plurality of portions (portions of for 512a…512n) and distributed among the plurality of decompression circuits (512a…512n) to perform decompression (138) on each of the plurality of portions in parallel (parallel portions decompressor 512a…512n). Regarding claim 6. The one or more processors of claim 1, Fig. 2 and Fig. 5 further disclose wherein the one or more processor (Fig. 2 and Fig. 5) are further to, in response to a second perform (second decompression interface of Fig. 5) an API (application program interface between Fig. 2 and Fig. 5)) call allocate memory at the storage locations (514a…514n in Fig. 5) indicated by the user (HOST in Fig. 1) based, at least in part, on an identification (520 in Fig. 5) whether the memory at the storage locations (514a…514n) is able to store the received data (400) after decompression (512a…512n). Regarding claim 7. The one or more processors of claim 1, Fig. 1, Fig. 2 and Fig. 5 further disclose wherein the API (decompression interface of Fig. 5) causes the received data (400) to be decompressed, at least in part, by identifying whether the one or more processors (112) includes the one or more circuits (138) wherein the one or more circuits (512a…512n) comprises one or more decompression circuits (512a….512n) designated to decompress the received data (400). Regarding claim 8. Fig. 1, Fig. 2 and Fig. 5) of Rasmussen disclose a system (100) comprising: one or more processors (112) ; and memory (120) comprising one or more instructions (paragraph 0033) that, when executed by the one or more processors (112 in Fig. 1), cause the one or more processors (112): in response to an application programming interface (programing interface between compression Fig. 4 and decompression Fig. 5 ) call, identify a parameter (limit, boundary, or defining characteristic of compressed data history 300) indicating a compression algorithm (212a….212n Fig. 2) used to compress received data (compressed data 400 in Fig. 2) wherein the API call (programing interface between compression Fig. 4 and decompression Fig. 5 ) comprises an identifier (520 in Fig. 5) corresponding to the parameter (limit, boundary , or defining characteristic of compressed data history 300); and schedule one or more circuits (plan or list that indicate time of switching circuit in Fig. 5 to perform decompression function or task) to decompress the received data (compressed data 400 in Fig. 4) based at least on the parameter (Compressed data History in Fig. 5); and store decompressed data in one or more storage locations (514a…514n) indicated by a user (Fig. 1 HOST). Regarding claim 9. The system of claim 8, Fig. 1, Fig. 2 and Fig. 5 further disclose wherein the one or more processors (112) further comprise a copy engine (copy engine of 138 for transfer a copy data of 510 to each decompressor of Fig. 5) having data transfer circuits (selection circuits in Fig. 5) that facilitate data transfer between a source (510 in Fig. 5) and a destination (514a..514n ), wherein the one or more circuits (512a…512n) comprises a portion (portion of 512a…512v) of the copy engine (138) is designated to perform decompression (designated of 512a….512n). Regarding claim 11, The system of claim 8, Fig. 1, Fig. 2 and Fig. 5 further disclose wherein the API (115) causes the received data (400 in Fig. 5) to be decompressed (138 in Fig. 5), at least in part, by transferring compressed data (400 in Fig. 5) to the one or more circuits (512a…512n) , wherein the one or more circuits (512a…512n) comprises hardware circuit (hardware of 512a…512n) dedicated solely to performing decompression (138). Regarding claim 12. The system of claim 8, Fig. 1, Fig. 2 and Fig. 5 further disclose wherein the one or more circuits (512a…512n) comprises a plurality of decompression circuits (512a…512n), and wherein the received (400) is divided into a plurality of portions (portions of for 512a…512n) and distributed among the plurality of decompression circuits (512a…512n) to perform decompression (138) on each of the plurality of portions in parallel (parallel portions decompressor 512a…512n). Regarding claim 13. The system of claim 8 Fig. 2 and Fig. 5 further disclose wherein the one or more circuits (512a…512n) further cause the one or more processors (112) to: in response to a second perform (second decompression interface of Fig. 5) an API (115) call allocate memory at the storage locations (514a…514n in Fig. 5) indicated by the user (HOST in Fig. 1) based at least, on an identification (520 in Fig. 5) whether the memory at the storage locations (514a…514n) is able to store the received data (400) after decompression (512a…512n). Regarding claim 14. The system of claim 8, Fig. 1, Fig. 2 and Fig. 5 further disclose wherein the API (decompression interface of Fig. 5) causes the received data (400) to be decompressed, at least in part, by identifying whether the one or more processors (112) includes the one or more circuits (138) wherein the one or more circuits (512a…512n) comprises one or more decompression circuits (512a….512n) designated to decompress the received data (400). Regarding claim 15. (Fig. 1, Fig. 2 and Fig. 5 discloses a method comprising: in response to an application programming interface (application program interface between Fig. 2 and Fig. 5) call: identifying (identifier 520 in Fig. 5) a parameter (limit, boundary, or defining characteristic of compressed data history 300) indicating a compression algorithm (212a…212n in Fig. 2) used to compress received data (compressed data 400 in Fig 4), wherein the API call (application program interface between Fig. 2 and Fig. 5) comprises an identifier (520 in Fig. 5) corresponding to the parameter (limit, boundary, or defining characteristic of compressed data history 300); and schedule one or more circuits (plan or list that indicate time to select of switching circuit in Fig. 5 to perform decompression function or task) to decompress the received data (400 in Fig. 4) base at least on the parameter (limit, boundary, or defining characteristic of compressed data history 300); and storing decompressed data (output of 512a…512n) in one or more storage locations (514a…514n) indicated by a user (HOST in Fig. 1). Regarding claim 16. The method of claim 15, Fig. 1, Fig. 2 and Fig. 5 further comprising: transferring the received data (400) to be decompressed (138) to a copy engine (copy engine of 138 for transfer a copy data of 510 to each decompressor ) having data transfer circuits (selection circuits in Fig. 5) that facilitate data transfer between a source (510) and a destination (514A…514n in Fig. 5); and decompressing (512a…512n) the received data (400) using a portion (each portion data or 512…512n) of the copy engine (copy engine of 138 for transfer a copy data of 510 to each decompressor ) designated to perform decompression (138) , wherein the one or more circuits (512a…512n) comprises the portion (each portion data or 512…512n) of the copy engine (copy engine of 138 for transfer a copy data of 510 to each decompressor). Regarding claim 17. The method of claim 15, Fig. 1, Fig. 2 and Fig. 5 further comprising: identifying (520) whether one or more processors (112 in Fig. 1) includes the one or more circuits (512a…512n), wherein the one or more circuits (512a…512n) comprises one or more decompression circuits (512a…512n); and decompressing (138) the received data (400) using the one or more decompression circuits (512a…512n). Regarding claim 18. The method of claim 15, Fig. 1, Fig. 2 and Fig. 5 further comprising: identifying (520 in Fig. 5) whether memory (514a…514n) at the one or more storage locations (514a…514n) are able to store the received data (400 in Fig. 5) after decompression (512a…512n); and allocating the memory (514a…515n) at the one or more storage locations (514a…515n) to received data (400) after decompression (412a…512n). Regarding claim 20. The method of claim 15, Fig. 5 further comprising: dividing the received data (400) to be decompressed into a plurality of portions (portions of 512a…512n) ; distributing the plurality of portions among the one or more circuits (portions of 512a…512n) , wherein the one or more circuits (512a…512n) comprises a plurality of decompression circuits (512a…512n) ; and decompressing (512a…512n) each of the plurality of portions (each portion of 512a…512n) using the plurality of decompression circuits in parallel (parallel of 512a…512n). Claim Rejections - 35 USC § 103 5. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 6. Claims 3, 10 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Rasmussen as applied to claims 1, 8 and 15 above, respectively, in view of Mahony et al. U.S. patent No. 9,973,210. Rasmussen as applied to claims 1, 8 and 15 above, respectively, does not disclose wherein compression algorithm comprises at least one of a deflate compression algorithm, an LZ4 compression algorithm, or a Snappy compression algorithm. Fig. 1 and Fig. 2 of Mahony et al. discloses compressed data (132s of each 1301…1304; Col. 5 lines 34-35 or compressed data set 204 in Fig. 1) using at least one of a deflate compression algorithm, an LZ4 compression algorithm, or a Snappy compression algorithm (Col. 5 lines 44-55). Rasmussen and Mahony et al. are common subject matter of compressed data; therefore, it would have been obvious before the effective filing date of claimed invention to one ordinary skill in the art to which the claimed invention pertains to incorporate Mahony et al. into Rasmussen for the purpose of Lossless compression identifies and reduces statistical redundancy in order to encode without information loss (Col. 5 lines 45-47 of Mahony et al.). Contact Information 7. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Linh Van Nguyen whose telephone number is (571) 272-1810. The examiner can normally be reached from 8:30 – 5:00 Monday-Friday. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Mr. Dameon E. Levi can be reached at (571) 272-2105. The fax phone numbers for the organization where this application or proceeding is assigned are (571-273-8300) for regular communications and (571-273-8300) for After Final communications. 09/09/2026 /LINH V NGUYEN/Primary Examiner, Art Unit 2845
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Prosecution Timeline

Oct 01, 2024
Application Filed
Mar 04, 2026
Non-Final Rejection mailed — §102, §103
Jun 04, 2026
Response Filed
Jun 17, 2026
Final Rejection mailed — §102, §103
Aug 31, 2026
Request for Continued Examination
Sep 04, 2026
Response after Non-Final Action
Sep 11, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Prosecution Projections

3-4
Expected OA Rounds
89%
Grant Probability
92%
With Interview (+2.4%)
1y 10m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 1206 resolved cases by this examiner. Grant probability derived from career allowance rate.

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