DETAILED ACTION
As per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
In responding to this Office action, the applicant is requested to include specific references (figures, paragraphs, lines, etc.) to the drawings/specification of the present application and/or the cited prior arts that clearly support any amendments/arguments presented in the response, to facilitate consideration of the amendments/arguments.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Should applicant desire to obtain the benefit of foreign priority under 35 U.S.C. 119(a)-(d) prior to declaration of an interference, a certified English translation of the foreign application must be submitted in reply to this action. 37 CFR 41.154(b) and 41.202(e). Failure to provide a certified translation may result in no benefit being accorded for the non-English application.
Election/Restrictions
Applicant's election with traverse of Invention 1, sub-species 1, claims 1-10 in the reply filed on 06/15/2026 is acknowledged. The traversal is on the ground(s) that there are no series search burden. This is not found persuasive because the claimed subject matter is substantially different and requires different search considerations.
The requirement is still deemed proper and is therefore made FINAL.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: --MEMORY DEVICE WITH SHUNTED BIT LINES--
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, “word lines and bit lines intersect with source lines, the word lines and the bit lines extending in a first direction and the source lines extending in the second direction” as recited in claim 1 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim(s) 1-10 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim(s) 1 recite(s) the language (emphasis added) “word lines and bit lines intersect with source lines, the word lines and the bit lines extending in a first direction and the source lines extending in the second direction”, where the are no physical layout depictions of the memory device in the disclosure. Figures 1-8 are schematic representations of a circuit, and not a physical layout of the circuit, and the intersection of particular elements, or their arrangement is particular directions is not support in the disclosure.
Claim(s) 1 recite(s) the language (emphasis added) “in a first direction and the source lines extending in the second direction”, where “the second direction” lacks antecedent basis.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 4, 5, and 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nagey, US 20160133321 A1.
As to claim 1, Nagey discloses a memory device (see Nagey Fig 1), comprising:
a memory cell array (see Nagey Fig 1 Ref 50) including a plurality of memory cells (see Nagey Para [0041]) arranged in areas (see the annotated image of Nagey Fig 1 below) in which word lines (see Nagey Fig 1 Ref WL) and bit lines (see Nagey Fig 1 Ref BLref) intersect with source lines (see Nagey Fig 1 the line between the resistive memory element R and the ground symbol below the access transistor), the word lines and the bit lines extending in a first direction (see the annotated image of Nagey Fig 1 below) and the source lines extending in the second direction (see the annotated image of Nagey Fig 1 below), wherein
memory cells along the first direction, among the plurality of memory cells, are electrically coupled to a same word line (see Nagey Fig 1 the uppermost Ref WL) and a same bit line (see Nagey Fig 1 Ref BLref and Ref 27), memory cells along the second direction, among the plurality of memory cells, and the bit lines are shunted at one or more shunt nodes (see Nagey Fig 1 Ref 27); and a regulator (see Nagey Para [0041]; A regulator is required to apply the voltages required to read the memory cells.) configured to apply a bit line voltage (see Nagey Para [0041]) to a common node (see Nagey Fig 1 Ref 27) at which the bit lines are electrically coupled in common (see Nagey Para [0041]).
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Nagey does not appear to explicitly disclose are electrically coupled to a same source line.
However, it would have been obvious to one skilled in the art at the time of the effective filing of the invention that the grounds below the access transistors in the array could be commonly connected as a same source line. Common source lines are common and well known in the semiconductor memory arts and simplify interconnect arrangements.
As to claim 4, Nagey discloses the memory device of claim 1, wherein
the bit lines are electrically coupled to the common node without switches (see Nagey Fig 1 Ref 27).
As to claim 5, Nagey discloses the memory device of claim 1, wherein
each of the plurality of memory cells comprises: a variable resistor element (see Nagey Fig 1 Refs 111 and 112) having one end electrically coupled to a respective bit line (see Nagey Fig 1 Ref BLref); and a switch element operable in response to a voltage through a respective word line (see Nagey Fig 1 Ref 125), the switch element being electrically coupled between the other end of the variable resistor element and a respective source line (see Nagey Fig 1).
As to claim 8, Nagey discloses the memory device of claim 1, wherein
a word line decoder (see Nagey Fig 1 Ref 30) configured to apply a selection voltage to a target word line (see Nagey Para [0041]; Selection requires a voltage.), among the word lines, and configured to apply a non-selection voltage to remaining word lines (see Nagey Para [0041]).
Claim(s) 6 and 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nagey, US 20160133321 A1, in view of Sekar, US 20210295913 A1.
As to claim 6, Nagey discloses the memory device of claim 1, further comprising
a source line voltage source.
Nagey does not appear to explicitly disclose a source line decoder configured to apply voltages, corresponding to input values received from an external device, to the source lines, respectively.
Sekar discloses a source line decoder (see Sekar Fig 4B Ref 450) configured to apply voltages, corresponding to input values received from an external device (see Nagey Fig 8B Refs SL1-3; External device is inherent to the different operation voltages.), to the source lines, respectively.
It would have been obvious to one skilled in the art at the time of the effective filing of the invention that a memory device, as disclosed by Nagey, may implement particular access and biasing circuity, as disclose by Sekar. The inventions are well known variants of resistive memory access circuitry and the combination of known inventions which produces predictable results is obvious and not patentable. Further evidence to the obviousness of their combination is Sekar’s attempt to optimizing operation voltages (see Sekar Para [0079]).
As to claim 7, Nagey and Sekar disclose the memory device of claim 6, wherein
the source line decoder applies a first source line voltage to a source line when an input value corresponding to the source line is a first value and applies a second source line voltage to the source line when the input value corresponding to the source line is a second value (see Sekar Figs 6B and 8B Refs SL1-3).
Allowable Subject Matter
Claim(s) 2, 3, 9, and 10 is/are objected to as being dependent upon a rejected base claim and 112 rejections, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims and the 112 rejections overcome.
The following is a statement of reasons for the indication of allowable subject matter:
The prior art does not appear to disclose (as recited in claim 2):
the shunt nodes are spaced apart at regular distance intervals.
The prior art does not appear to disclose (as recited in claim 3):
the number of the shunt nodes is equal to the number of the source lines.
The prior art does not appear to disclose (as recited in claim 9):
further comprising an analog-to-digital converter configured to output a digital value corresponding to a cumulative cell current amount flowing through a sensing node electrically coupled to the common node.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Bertin, US 20230142173 A1 discloses a source line decoder.
Saxena, US 20220309328 A1 discloses a source line decoder.
Choi, US 20200035305 A1 discloses coupled to the common node without switches.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JEROME LARRY LEBOEUF whose telephone number is (571)272-7612. The examiner can normally be reached M-Th: 8:00AM - 6:00PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, RICHARD ELMS can be reached at (517)272-1869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JEROME LEBOEUF/Primary Examiner, Art Unit 2824
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