Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement(s) (IDS) submitted on 02/27/2025 has/have been considered by the examiner and made of record in the application file.
Claim Rejections - 35 USC § 112(b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim(s) 9 and 19 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 9 and 19 both recite the limitation “the insulating layer comprises an insulator having a K value between 1 to 3.9”. This limitation is unclear and indefinite as the examiner is unable to determine what applicant is referring to by the use of the phrase “K value”. Applicant has not identified what the K value is referring to and no units have been provided for the values. As far as the examiner can tell, the applicant may be referring to the thermal conductivity of the material which is commonly referred to in the art as “K-value”, however, these values have units such as W/(m·K). In the alternative, applicant may be referring to the κ-value which is the dielectric constant of an insulating material and does not have units but utilizes an entirely different symbol of the Greek letter kappa. As example materials, the applicant has only provided silicon dioxide (thermal conductivity 1.3-1.5 W/(m·K), i.e. in the range, and dielectric constant 3.6-4.2, i.e. in the range) and polysilicon, which has not been specified as being doped or undoped such that it has an incredibly variable thermal conductivity and dielectric constant without more details. As a result it is entirely unclear what “K-value” is referring to and it is further a possibility that applicant has not provided enablement (no 35 U.S.C. 112(a) rejection is given at this time since examiner does not know what the K-value is) for the entire range since it does not appear a material has been given that explicitly meets the lower end of the provided range depending on what the intended meaning is of “K-value”. Therefore, claim(s) 9 and 19 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. For the purposes of this examination, it will be interpreted that any insulator described as comprising silicon dioxide and/or polysilicon will meet this limitation since no alternative examples or contradictory examples have been provided.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2019/0198652 A1; Kushida et al.; 06/2019; (“Kushida”).
Regarding Claim 1. Kushida discloses A High-Electron-Mobility-Transistor (#10E, Figure 10, semiconductor device which is a HEMT) comprising:
a substrate (#500, Figure 10);
a first buffer layer (#51, Figure 10) formed on the substrate (Figure 10, #51 is formed on #500);
a barrier layer (#52, Figure 10, barrier layer) formed on the first buffer layer (Figure 10, #52 is formed on #51);
a doped structure (#104, Figure 10, p-type semiconductor region) surrounded by the barrier layer (Figure 10, #104 is at least partially surrounded by #52);
a second buffer layer (#53, Figure 10) formed on the barrier layer (Figure 10, #53 is formed on #52);
a spacer (#230, Figure 10, gate side insulating regions) formed on a portion of the doped structure (Figure 10, #230 is formed on a portion of #104);
an insulating layer (Figure 10, non-numbered diagonally shaded region interpreted to be silicon dioxide based on [0056]) formed over the second buffer layer (Figure 10, the non-numbered diagonally shaded region is formed over #53);
a gate electrode (#103, Figure 10, gate electrode) formed within the spacer (Figure 10, #103 is formed within #203) through the insulating layer (Figure 10, #103 is formed through the non-numbered diagonally shaded region), through the second buffer layer (Figure 10, #103 is formed through #53) and partially into the barrier layer (Figure 10, #103 is formed at least partially into #52), the gate electrode connected to the doped structure (Figure 10, #103 is connected to #104);
a drain terminal formed at a first side of the gate electrode (#101, Figure 10, drain electrode formed on the right side of #103); and
a source terminal formed at a second side of the gate electrode (#105, Figure 10, source electrode formed on the left side of #103).
Regarding Claim 2. Kushida discloses The High-Electron-Mobility-Transistor of claim 1, wherein the substrate comprises gallium nitride, diamond, silicon carbide, sapphire, aluminum nitride or silicon (Figure 10, #500 is gallium nitride).
Regarding Claim 3. Kushida discloses The High-Electron-Mobility-Transistor of claim 1, wherein the first buffer layer comprises a III-V compound semiconductor (Figure 10, #51 is GaN).
Regarding Claim 4. Kushida discloses The High-Electron-Mobility-Transistor of claim 1, wherein the first buffer layer comprises gallium nitride (Figure 10, #51 is GaN).
Regarding Claim 5. Kushida discloses The High-Electron-Mobility-Transistor of claim 1, wherein the barrier layer comprises aluminum gallium nitride (Figure 10, #52 is AlGaN).
Regarding Claim 6. Kushida discloses The High-Electron-Mobility-Transistor of claim 1, wherein the doped structure comprises P-doped gallium nitride (Figure 10, [0058], #104 is formed by introducing p-type impurities into the trench which includes GaN sidewalls such that #104 will include p-doped GaN).
Regarding Claim 7. Kushida discloses The High-Electron-Mobility-Transistor of claim 1, wherein the second buffer layer comprises a III-V compound semiconductor (Figure 10, #53 is GaN).
Regarding Claim 8. Kushida discloses The High-Electron-Mobility-Transistor of claim 1, wherein the second buffer layer comprises gallium nitride (Figure 10, #53 is GaN).
Regarding Claim 9. Kushida discloses The High-Electron-Mobility-Transistor of claim 1, wherein the insulating layer comprises an insulator having a K value between 1 to 3.9 (Figure 10, non-numbered diagonally shaded region interpreted to be silicon dioxide, having a thermal conductivity of 1.3-1.5 W/(m·K), i.e. in the range, and a dielectric constant of 3.6-4.2, i.e. in the range, based on [0056] which provides a silicon oxide from which silicon dioxide is one of the most common insulators in semiconductors).
Regarding Claim 10. Kushida discloses The High-Electron-Mobility-Transistor of claim 1, wherein the insulating layer comprises polysilicon, silicon dioxide or a mixture of polysilicon and silicon dioxide (Figure 10, non-numbered diagonally shaded region interpreted to be silicon dioxide based on [0056] which provides a silicon oxide from which silicon dioxide is one of the most common insulators in semiconductors).
Regarding Claim 11. Kushida discloses A method for producing a High-Electron-Mobility-Transistor (#10E, Figure 10, semiconductor device which is a HEMT and necessarily considers a method of making in so far as method steps are claimed below) comprising:
providing a substrate (#500, Figure 10);
forming a first buffer layer (#51, Figure 10) on the substrate (Figure 10, #51 is formed on #500);
forming a barrier layer (#52, Figure 10, barrier layer) over the first buffer layer (Figure 10, #52 is formed over #51);
forming a doped structure (#104, Figure 10, p-type semiconductor region) surrounded by the barrier layer (Figure 10, #104 is at least partially surrounded by #52);
forming a second buffer layer (#53, Figure 10) over the barrier layer (Figure 10, #53 is formed over #52);
forming a spacer (#230, Figure 10, gate side insulating regions) on a portion of the doped structure (Figure 10, #230 is formed on a portion of #104);
forming an insulating layer (Figure 10, non-numbered diagonally shaded region interpreted to be silicon dioxide based on [0056]) over the second buffer layer (Figure 10, the non-numbered diagonally shaded region is formed over #53);
forming a gate electrode (#103, Figure 10, gate electrode) within the spacer (Figure 10, #103 is formed within #203) through the insulating layer (Figure 10, #103 is formed through the non-numbered diagonally shaded region), through the second buffer layer (Figure 10, #103 is formed through #53) and partially into the barrier layer (Figure 10, #103 is formed at least partially into #52), the gate electrode connected to the doped structure (Figure 10, #103 is connected to #104);
forming a drain terminal at a first side of the gate electrode (#101, Figure 10, drain electrode formed on the right side of #103); and
forming a source terminal at a second side of the gate electrode (#105, Figure 10, source electrode formed on the left side of #103).
Regarding Claim 12. Kushida discloses The method for producing a High-Electron-Mobility-Transistor of claim 11, wherein the substrate comprises gallium nitride, diamond, silicon carbide, sapphire, aluminum nitride or silicon (Figure 10, #500 is gallium nitride).
Regarding Claim 13. Kushida discloses The method for producing a High-Electron-Mobility-Transistor of claim 11, wherein the first buffer layer comprises a III-V compound semiconductor (Figure 10, #51 is GaN).
Regarding Claim 14. Kushida discloses The method for producing a High-Electron-Mobility-Transistor of claim 11, wherein the first buffer layer comprises gallium nitride (Figure 10, #51 is GaN).
Regarding Claim 15. Kushida discloses The method for producing a High-Electron-Mobility-Transistor of claim 11, wherein the barrier layer comprises aluminum gallium nitride (Figure 10, #52 is AlGaN).
Regarding Claim 16. Kushida discloses The method for producing a High-Electron-Mobility-Transistor of claim 11, wherein the doped structure comprises P-doped gallium nitride (Figure 10, [0058], #104 is formed by introducing p-type impurities into the trench which includes GaN sidewalls such that #104 will include p-doped GaN).
Regarding Claim 17. Kushida discloses The method for producing a High-Electron-Mobility-Transistor of claim 11, wherein the second buffer layer comprises a III-V compound semiconductor (Figure 10, #53 is GaN).
Regarding Claim 18. Kushida discloses The method for producing a High-Electron-Mobility-Transistor of claim 11, wherein the second buffer layer comprises gallium nitride (Figure 10, #53 is GaN).
Regarding Claim 19. Kushida discloses The method for producing a High-Electron-Mobility-Transistor of claim 11, wherein the insulating layer comprises an insulator having a K value between 1 to 3.9 (Figure 10, non-numbered diagonally shaded region interpreted to be silicon dioxide, having a thermal conductivity of 1.3-1.5 W/(m·K), i.e. in the range, and a dielectric constant of 3.6-4.2, i.e. in the range, based on [0056] which provides a silicon oxide from which silicon dioxide is one of the most common insulators in semiconductors).
Regarding Claim 20. Kushida discloses The method for producing a High-Electron-Mobility-Transistor of claim 11, wherein the insulating layer comprises polysilicon, silicon dioxide or a mixture of polysilicon and silicon dioxide (Figure 10, non-numbered diagonally shaded region interpreted to be silicon dioxide based on [0056] which provides a silicon oxide from which silicon dioxide is one of the most common insulators in semiconductors).
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claim(s) 1, 3, 7, 4 and 8, 5, 6, 10, 11, 13, 17, 14 and 18, 15, 16, and 20 is/are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claim(s) 1, 4, 5, 6, 7, 9, 10, 11, 14, 15, 16, 17, 19, and 20 of co-pending Application No. 19/074,204 (reference application). Although the claims at issue are not identical, they are not patentably distinct from each other because the reference co-pending application claims a species of the device claimed by the instant application’s genus. The reference claims include all of the limitations in the instant application’s claims. At the same time, the instant application’s claims listed above do not claim anything which is not claimed by the co-pending reference application.
Claim(s) 1, 3, 7, 4 and 8, 5, 6, 10, 11, 13, 17, 14 and 18, 15, 16, and 20 is/are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claim(s) 1, 3, 4, 5, 6, 7, 9, 11, 13, 14, 15, 16, 17, and 19 of co-pending Application No. 19/074,144 (reference application). Although the claims at issue are not identical, they are not patentably distinct from each other because the reference co-pending application claims a species of the device claimed by the instant application’s genus. The reference claims include all of the limitations in the instant application’s claims. At the same time, the instant application’s claims listed above do not claim anything which is not claimed by the co-pending reference application.
Claim(s) 1, 2, 3, 4, 5, 6, 7, 8, 10, 11, 12, 13, 14, 15, 16, 17, 18, and 20 is/are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claim(s) 1, 2, 3, 4, 6, 7, 8, 9, 10, 11, 12, 13, 14, 16, 17, 18, 19, and 20 of co-pending Application No. 18/924,073 (reference application). Although the claims at issue are not identical, they are not patentably distinct from each other because the reference co-pending application claims a species of the device claimed by the instant application’s genus. The reference claims include all of the limitations in the instant application’s claims. At the same time, the instant application’s claims listed above do not claim anything which is not claimed by the co-pending reference application.
These are provisional nonstatutory double patenting rejections because the patentably indistinct claims have not in fact been patented.
Conclusion
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/TYLER J WIEGAND/Examiner, Art Unit 2812
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