Prosecution Insights
Last updated: July 17, 2026
Application No. 18/904,358

FORCE SENSOR

Non-Final OA §103§112
Filed
Oct 02, 2024
Priority
Sep 20, 2019 — JP 2019-172075 +2 more
Examiner
TRAN, TRAN M.
Art Unit
2855
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Japan Display Inc.
OA Round
1 (Non-Final)
74%
Grant Probability
Favorable
1-2
OA Rounds
9m
Est. Remaining
98%
With Interview

Examiner Intelligence

Grants 74% — above average
74%
Career Allowance Rate
471 granted / 633 resolved
+6.4% vs TC avg
Strong +24% interview lift
Without
With
+23.7%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
37 currently pending
Career history
657
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
88.1%
+48.1% vs TC avg
§102
3.4%
-36.6% vs TC avg
§112
7.7%
-32.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 633 resolved cases

Office Action

§103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Priority Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Specification Applicant is reminded of the proper language and format for an abstract of the disclosure. The abstract should be in narrative form and generally limited to a single paragraph on a separate sheet within the range of 50 to 150 words in length. The abstract should describe the disclosure sufficiently to assist readers in deciding whether there is a need for consulting the full patent text for details. The language should be clear and concise and should not repeat information given in the title. It should avoid using phrases which can be implied, such as, “The disclosure concerns,” “The disclosure defined by this invention,” “The disclosure describes,” etc. In addition, the form and legal phraseology often used in patent claims, such as “means” and “said,” should be avoided. The abstract of the disclosure is objected to because the abstract contains at least one of the phrases that can be implied, such as the phrase “according to an aspect”. Correction is required. See MPEP § 608.01(b). The disclosure is objected to because of the following informalities: the title is not descriptive. A new title that would include the inventive features of the claimed invention is respectfully requested. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. Claims 1-4 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as failing to set forth the subject matter which the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the applicant regards as the invention. Regarding claim 1, the recitations of “a first sensor electrode is coupled to the first transistor”, “a second sensor electrode is coupled to the second transistor”, and “the first sensor electrode, the second sensor electrode, and the counter electrode are located on the facing surface and do not overlap each other in a plan view” do not appear to have clear support from the specification, in describing a force sensor having the electrodes coupled to transistors and the electrodes do not overlap each other. The fourth embodiment, directed to at least Fig. 9 and 10, in the specification, does not appear to disclose the claimed limitations including the electrodes “do not overlap each other” and being “coupled to” the transistors. The first embodiment, directed to at least Fig. 1, does not appear to disclose the claimed limitations including the electrodes “do not overlap each other” and being “coupled to” the transistor. The second embodiment, directed to at least Fig. 5, does not appear to disclose the claimed limitations including the electrodes “do not overlap each other” and being “coupled to” the transistor, as disclosed in the claim. The embodiments, as disclosed in the specification, do not appear to distinguish between the electrodes and the counter electrode as being the first electrode, the second electrode, and the counter electrode, as disclosed in the claim. Further clarification is respectfully requested. Claims 2 and 3 are rejected as being dependent on the rejected base claim. Regarding claim 4, the recitations of “a first sensor electrode is coupled to the first transistor”, “a second sensor electrode is coupled to the second transistor”, and “the first sensor electrode, the second sensor electrode, and the counter electrode are located on the facing surface and do not overlap each other in a plan view” do not appear to have clear support from the specification, in describing a force sensor having the electrodes coupled to transistors and the electrodes do not overlap each other. The fourth embodiment, directed to at least Fig. 9 and 10, in the specification, does not appear to disclose the claimed limitations including the electrodes “do not overlap each other” and being “coupled to” the transistors. The first embodiment, directed to at least Fig. 1, does not appear to disclose the claimed limitations including the electrodes “do not overlap each other” and being “coupled to” the transistor. The second embodiment, directed to at least Fig. 5, does not appear to disclose the claimed limitations including the electrodes “do not overlap each other” and being “coupled to” the transistor, as disclosed in the claim. The embodiments, as disclosed in the specification, do not appear to distinguish between the electrodes and the counter electrode as being the first electrode, the second electrode, and the counter electrode, as disclosed in the claim. Further clarification is respectfully requested. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claims 1-4 are rejected under 35 U.S.C. 103 as being unpatentable over Kimura et al. (Pub. No. US 2016/0282990) (hereafter Kimura) in view of Gudan (Pat. No. US 9,127,992) (hereafter Gudan). Regarding claim 1, Kimura teaches a force sensor comprising: a force sensor sheet (i.e., liquid crystal 23) (see Fig. 7D) having a first surface and including conductive particles and insulating elastic materials; and a substrate (i.e., substrate 11) (see Fig. 11) including a first transistor and a second transistor and having a facing surface facing the first surface of the force sensor sheet (i.e., each pixel includes at least a transistor 63 and a liquid crystal element 64) (see paragraph section [0140]), wherein a first sensor electrode is coupled to the first transistor (i.e., conductive layer 22) (see Fig. 7D), a second sensor electrode is coupled to the second transistor (i.e., conductive layer 41) (see Fig. 7D), a counter electrode is located between the first sensor electrode and the second sensor electrode in a first direction parallel to the facing surface of the substrate (i.e., conductive layer 21) (see Fig. 7D), and the first sensor electrode, the second sensor electrode, and the counter electrode are located on the facing surface and do not overlap each other in a plan view (see Fig. 7D). Regarding claim 2, Kimura teaches that the force sensor sheet has a second surface opposed to the first surface, and a protective layer is disposed on the second surface of the force sensor sheet (i.e., substrate 12) (see Fig. 7D). Regarding claim 3, Kimura as disclosed above does not directly or implicitly teach an adhesive layer, wherein the substrate, the adhesive layer, the force sensor sheet, and the protective layer are stacked in a stacking direction, and the adhesive layer is made of an anisotropic conductive material and has conductivity in the stacking direction and insulation properties in a planar direction crossing the stacking direction. Regarding the adhesive layer, Gudan teaches an adhesive layer (i.e., anisotropic conductive film or anisotropic conductive adhesive) (see Column 19, line 47, to Column 20, line 47), and the adhesive layer is made of an anisotropic conductive material and has conductivity in the stacking direction and insulation properties in a planar direction crossing the stacking direction (i.e., conducts electrical signals exclusively in the "z" direction (between the top layer of the mat and the tape), but not the "x" or "y" direction (between lines on the mat or tape). It can also be cured at room temperature. Use of an anisotropic conductive adhesive ensures a good interconnect between the removable tape strip and the top layer of the mat) (see Column 19, line 47, to Column 20, line 47). In view of the teaching of Gudan, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have added an anisotropic adhesive layer in order to improve the interconnection between the layers. Regarding the stacking direction, Kimura as modified by Gudan as disclosed above does not directly or implicitly teach that the substrate, the adhesive layer, the force sensor sheet, and the protective layer are stacked in a stacking direction. However, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have optimally arranged the stacking order of the components, depending on the implementation of the sensor. Furthermore, it has been held that rearranging parts of an invention involves only routine skill in the art (see MPEP 2144.04 (VI-C)). Regarding claim 4, Kimura teaches a force sensor comprising: a force sensor sheet (i.e., liquid crystal 23) (see Fig. 7D) having a first surface and including conductive particles and insulating elastic materials; a substrate (i.e., substrate 11) (see Fig. 11) including a first transistor and a second transistor and having a facing surface facing the first surface of the force sensor sheet (i.e., each pixel includes at least a transistor 63 and a liquid crystal element 64) (see paragraph section [0140]); and wherein a first sensor electrode is coupled to the first transistor (i.e., conductive layer 22) (see Fig. 7D), a second sensor electrode is coupled to the second transistor (i.e., conductive layer 41) (see Fig. 7D), a counter electrode is located between the first sensor electrode and the second sensor electrode in a first direction parallel to the facing surface of the substrate (i.e., conductive layer 21) (see Fig. 7D), the first sensor electrode, the second sensor electrode, and the counter electrode are located on the facing surface and do not overlap each other in a plan view (see Fig. 7D); but does not explicitly teach a resin layer interposed between the substrate and the force sensor sheet, the resin layer has conductivity in the stacking direction and has insulation properties in a planar direction crossing the stacking direction, and that the substrate, the resin layer, and the force sensor sheet are stacked in a stacking direction Regarding the resin layer, Gudan teaches a resin layer interposed between the substrate and the force sensor sheet (i.e., anisotropic conductive film or anisotropic conductive adhesive) (see Column 19, line 47, to Column 20, line 47), the resin layer has conductivity in the stacking direction and has insulation properties in a planar direction crossing the stacking direction (i.e., conducts electrical signals exclusively in the "z" direction (between the top layer of the mat and the tape), but not the "x" or "y" direction (between lines on the mat or tape). It can also be cured at room temperature. Use of an anisotropic conductive adhesive ensures a good interconnect between the removable tape strip and the top layer of the mat) (see Column 19, line 47, to Column 20, line 47). In view of the teaching of Gudan, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have added a resin layer in order to improve the interconnection between the layers. Regarding the stacking direction, Kimura as modified by Gudan as disclosed above does not directly or implicitly teach that the substrate, the adhesive layer, the force sensor sheet, and the protective layer are stacked in a stacking direction. However, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have optimally arranged the stacking order of the components, depending on the implementation of the sensor. Furthermore, it has been held that rearranging parts of an invention involves only routine skill in the art (see MPEP 2144.04 (VI-C)). Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: see PTO-892. Any inquiry concerning this communication or earlier communications from the examiner should be directed to TRAN M. TRAN whose telephone number is (571)270-0307. The examiner can normally be reached Mon-Fri 11:30am - 7:00pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Laura Martin can be reached on (571)-272-2160. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Tran M. Tran/Examiner, Art Unit 2855
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Prosecution Timeline

Oct 02, 2024
Application Filed
Jun 26, 2026
Non-Final Rejection mailed — §103, §112 (current)

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Prosecution Projections

1-2
Expected OA Rounds
74%
Grant Probability
98%
With Interview (+23.7%)
2y 6m (~9m remaining)
Median Time to Grant
Low
PTA Risk
Based on 633 resolved cases by this examiner. Grant probability derived from career allowance rate.

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