DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-17 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Lee et al. (US 20240313705).
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With respect to claim 1, Lee et al. (US 20240313705) discloses a buffer circuit (fig. 1) configured to generate an output voltage (Vout) according to an input voltage (Vin), comprising: an input stage (input stage 100) configured to provide first (IN1 and IP1) and second differential (IN2 and IP2) currents to a load stage (200) or receive third and fourth differential currents from the load stage based on a difference between the input voltage (Vin) and the output voltage (Vout); the a-load stage (200) configured to apply gate voltages to first (P_01) and second (N_01) output transistors of an output stage (300) based on the first through fourth differential currents (I_N1, I_N2, I_P1 and I_P2); the output stage configured to regulate the output voltage based on the gate voltages applied to the first and the second output transistors; and a slew rate compensator (400) configured to regulate the gate voltages of the first and second output transistors by providing a source current (I_SOURCE) to the load stage or receiving a sink current (I_SINK) from the load stage (200), wherein the slew rate compensator (400) comprises: a source follower (N_SF1) configured to output a corrected input voltage (at P_COMP) obtained by reducing the input voltage (VIN) by a threshold voltage of a first source follower NMOS (N_SF1) transistor having a body connected in common with a source; and a first control circuit (N_SF2) configured to control a magnitude of the corrected input voltage output from the source follower.
With respect to claim 2, Lee et al. discloses the buffer circuit of claim 1, wherein the first control circuit comprises a first control NMOS transistor (N_SF2) having a drain connected to the source follower; a source connected to a ground voltage (at Vss); and a gate to which a gate voltage of the second output transistor (N_O1) is applied.
With respect to claim 3, Lee et al. discloses the buffer circuit of claim 1, wherein the slew rate compensator (400) further comprises: a first comparator (410; N_COMP) configured to enter an ON operating state or an OFF operating state based on the difference between the input voltage (Vin) and the output voltage (Vout) ; a second comparator (410; P_COMP) configured to enter an ON operating state or an OFF operating state based on a difference between the corrected input voltage (from N_SFT1) and the output voltage (VOUT); a source current circuit (I_SOURCE) configured to provide the source current to the load stage (200); a sink current circuit (I_SINK) configured to receive the sink current from the load stage; a slew rate compensation switch (450) configured to determine whether the source current circuit or the sink current circuit is operating; and a second control circuit (430) configured to control the corrected input voltage (at N_SF1) output from the source follower.
With respect to claim 4, Lee et al. discloses the buffer circuit of claim 3, wherein the second control circuit comprises: a first control PMOS transistor (P_SR1) configured to operate as a current source; and a second control PMOS transistor (P_SR2) having a drain connected to the first control PMOS transistor; a source connected to a power supply voltage (VDD); and a gate to which a gate voltage of the first output transistor (P_01) is applied.
With respect to claim 5, Lee discloses the buffer circuit of claim 4, wherein the first comparator (410; N_COMP) comprises an NMOS transistor having a gate connected to the input voltage (VIN); a drain connected to the source current circuit (I_SOURCE); and a source connected to the output voltage (VOUT), wherein the second comparator (410; P_COMP) comprises a PMOS transistor having a gate connected to the corrected input voltage (at N_SF1) output from the source follower (N_SF1); a drain connected to the sink current circuit (I_SINK); and a source connected to the output voltage (VOUT), and wherein the NMOS transistor has a body connected in common with the source and configured to receive the output voltage (VOUT).
With respect to claim 6, Lee discloses the buffer circuit of claim 5, wherein the first source follower NMOS transistor of the source follower (N_SF1) comprises: a first source follower NMOS transistor includes a gate connected to the input voltage (VIN), a drain connected to the power supply voltage (VDD), and the source connected to the gate of the PMOS transistor of the second comparator (P_COMP), and a body connected in common with the source, and wherein the source follower provides the corrected input voltage to the gate of the PMOS transistor of the second comparator (P_COMP).
With respect to claim 7, LEE et al. discloses the buffer circuit of claim 3, wherein the source current circuit comprises: a first source PMOS transistor (P_SR1) having a gate connected to the first comparator (N_COMP); a drain connected in common with the gate; and a source connected to a power supply voltage (VDD), and configured to allow a source reference current to flow therethrough; and a second source PMOS transistor (P_SR2) having a gate connected in common with the gate of the first source PMOS transistor (P_SR1); a drain connected to a fourth node (ND4) of the load stage (200) having a mirroring structure with and corresponding to a third node (at ND3) of the load stage connected to a gate terminal of the second output transistor (N_01); and a source connected to the power supply voltage (VDD), and configured to allow the source current to flow therethrough by mirroring the source reference current (I_SOURCE).
With respect to claim 8, LEE et al. discloses the buffer circuit of claim 3, wherein the sink current circuit comprises: a first sink NMOS transistor (N_SR1) having a gate connected to the second comparator (410; P_COMP); a drain connected in common with the gate; and a source connected to a ground voltage (VSS), and configured to allow a sink reference current (I_SINK) to flow therethrough; and a second sink NMOS transistor (N_SR2) having a gate connected in common with the gate of the first sink NMOS transistor; a drain connected to a second node (ND2) of the load stage having a mirroring structure with and corresponding to a first node of the load stage (ND1) connected to a gate terminal of the first output transistor (P_01); and a source connected to the ground voltage (VSS), and configured to allow the sink current to flow therethrough by mirroring the sink reference current (I_SINK).
With respect to claim 9, LEE et al. discloses the buffer circuit of claim 1, wherein the load stage (200) comprises: a first differential mirror circuit (210) having a current mirroring structure and a cascode structure, and configured to mirror the first and second (I_P1 and I_P2) third and fourth (I_N1 and I_N2) differential currents and the sink currents ;a second differential mirror circuit (220) having a current mirroring structure and a cascode structure, and configured to mirror the third and fourth(I_N1 and I_N2) first and second (I_P1 and I_P2) differential currents and the source current; and a third bias circuit (230) and a fourth bias circuit (240) connected between the first differential mirror circuit (210) and the second differential mirror circuit (220), and configured to control an operation in a static state and an amplification operation of the first differential mirror circuit (210) and the second differential mirror circuit (220).
With respect to claim 10, LEE discloses a buffer circuit configured to generate an output voltage (Vout) according to an input voltage (Vin), comprising: an input stage (100) configured to provide first and second differential currents (I_P1 and I_P2) to a load stage (200) or receive third and fourth differential currents (I_N1 and I_N2) from the load stage (200) based on a difference between the input voltage (Vin) and the output voltage (Vout); the load stage (200) configured to apply gate voltages to first (P_01) and second (P_02) output transistors of an output stage (300) based on the first through fourth differential currents (I_P1-I_N2); the output stage configured to regulate the output voltage (Vout) based on the gate voltages applied to the first (P_01) and second (P_02) output transistors; and a slew rate compensator (400) configured to regulate the gate voltages of the first (P_01) and second (P_02) output transistors by providing a source current (I_SOURCE) to the load stage or receiving a sink current (I_SINK) from the load stage (200), wherein the slew rate compensator comprises: a source follower (N_SF1) configured to output a corrected input voltage obtained by reducing the input voltage (VIN) by a threshold voltage of a MOS transistor (N_SF2) ; and a second control circuit comprising a first control PMOS transistor (P_SR2) operating as a current source and a second control PMOS transistor (P_SR1) whose gate receives a gate voltage of the first output transistor configured to control the corrected input voltage output from the source follower.
With respect to claim 11, LEE et al. disclose the buffer circuit of claim 10, wherein the second control PMOS transistor (430) comprises a drain connected to the first control PMOS transistor (P_SR2) and a source connected to a power supply voltage (VDD) circuit comprises: a first control PMOS transistor (P_SR2) configured to operate as a current source, and a second control PMOS transistor (P_SR1) having a drain connected to the first control PMOS transistor (P_SR2 ); a source connected to a power supply voltage (VDD); and a gate to which a gate voltage of the first output transistor (P_O1) is applied.
With respect to claim 12, LEE discloses the buffer circuit of claim 10, wherein the slew rate compensator further comprises: a first comparator (N_COMP) configured to enter an ON operating state or an OFF operating state based on the difference between the input voltage and the output voltage; a second comparator (P_COMP) configured to enter an ON operating state or an OFF operating state based on a difference between the corrected input voltage and the output voltage; a source current circuit (430) configured to provide the source current (I_SOURCE) to the load stage; a sink current circuit (440) configured to receive the sink current from the load stage; a slew rate compensation switch (450) configured to determine whether the source current circuit or the sink current circuit is operating; and a first control circuit (NSF2) configured to control a magnitude of a current of the source follower (N_SF1), wherein the source follower comprises a first source follower NMOS transistor having a gate connected to the input voltage; a drain connected to a power supply voltage; a source connected to a gate of a PMOS transistor (P_COMP) of the second comparator; and a body connected in common with the source, and wherein the source follower is configured to provide the corrected input voltage to the gate of the PMOS transistor of the second comparator.
With respect to claim 13, LEE discloses the buffer circuit of claim 12, wherein the first control circuit comprises: a first control NMOS transistor (N_SF2) having a drain connected to the source follower; a source connected to a ground voltage; and a gate to which a gate voltage of the second output transistor (N_O1) is applied.
With respect to claim 14, LEE discloses the buffer circuit of claim 12, wherein the first comparator comprises an NMOS transistor (N_COMP) having a gate connected to the input voltage; a drain connected to the source current circuit; and a source connected to the output voltage (VOUT), wherein the second comparator comprises a PMOS transistor (P_COMP) having a gate connected to the corrected input voltage output from the source follower (N_SF1); a drain connected to the sink current circuit; and a source connected to the output voltage (VOUT),, and wherein the NMOS transistor has a body connected in common with the source and configured to receive the output voltage.
With respect to claim 15, LEE discloses the buffer circuit of claim 12, wherein the source current circuit (430) comprises: a first source PMOS transistor (P_SR1) having a gate connected to the first comparator; a drain connected in common with the gate; and a source connected to a-the power supply voltage (VDD), and configured to allow a source reference current to flow therethrough; and a second source PMOS transistor (P_SR2) having a gate connected in common with the gate of the first source PMOS transistor; a drain connected to a fourth node of the load stage (200) having a mirroring structure with and corresponding to a third node of the load stage connected to a gate terminal of the second output transistor; and a source connected to the power supply voltage (VDD), and configured to allow the source current to flow therethrough by mirroring the source reference current.
With respect to claim 16, LEE discloses the buffer circuit of claim 12, wherein the sink current circuit (440) comprises: a first sink NMOS transistor (N_SR1) having a gate connected to the second comparator (P_COMP); a drain connected in common with the gate; and a source connected to a ground voltage (VSS), and configured to allow a sink reference current to flow therethrough; and a second sink NMOS transistor (N_SR2) having a gate connected in common with the gate of the first sink NMOS transistor; a drain connected to a second node of the load stage having a mirroring structure with and corresponding to a first node of the load stage connected to a gate terminal of the first output transistor (P_O1); and a source connected to the ground voltage (VSS), and configured to allow the sink current to flow therethrough by mirroring the sink reference current (I_SINK).
With respect to claim 17, LEE discloses the buffer circuit of claim 10, wherein the load stage (200) comprises: a first differential mirror circuit (210) having a current mirroring structure (PL_1 and PL_2) and a cascode structure (P_L3 and P_L4), and configured to mirror the first and second third and fourth differential currents and the sink current; a second differential mirror circuit (220) having a current mirroring structure (N_L1 and N_L2) and a cascode structure (N_L3 and N_L4), and configured to mirror the third and fourth first and second differential currents and the source current; and a third bias circuit (230) and a fourth bias circuit (240) connected between the first differential mirror circuit and the second differential mirror circuit, and configured to control an operation in a static state and an amplification operation of the first differential mirror circuit and the second differential mirror circuit.
Claim(s) 1 and 9 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by LEE (US 9543912).
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With respect to claim 1, Lee discloses, in Figs. 1-3 and 7-8, a buffer circuit (Fig. 1 further details of 110, 130, 160 and 150 are disclosed in Figs. 2-3 and 7-8) configured to generate an output voltage (VOUT) according to an input voltage (VIN), comprising: an input stage (110, details disclosed in Fig. 2) configured to provide first (ILD) and second (ILDB) differential currents to a load stage (to 130) or receive third (ILU) and fourth (ILUB) differential currents from the load stage (from 130) based on a difference between the input voltage and the output voltage (difference between VIN and VOUT based on the differential pairs of Fig. 2, see 110 of Fig. 2); the load stage (130 details disclosed in Fig. 3) configured to apply gate voltages (voltage at NCU of Fig. 3; voltage at NCD of Fig. 3) to first (MP8) and second (MN8) output transistors of an output stage (150) based on the first through fourth differential currents (first through fourth currents provided to load 130); the output stage configured to regulate the output voltage based on the gate voltages applied to the first and the second output transistors (Vout is regulated by 150 based on the voltages at NCU and NCD); and a slew rate compensator (160, further details disclosed in Figs. 3, 7 and 8) configured to regulate the gate voltages of the first and second output transistors by providing a source current to the load stage or receiving a sink current from the load stage (via the pull down, i.e., sinking, of NCD by MN15 of Fig. 7 and the pull up, i.e., souring, of NCM by MP15 of Fig. 7), wherein the slew rate compensator comprises:
a source follower configured to output a corrected input voltage obtained by reducing the input voltage by a threshold voltage (MN16 of Fig. 7; Vin applied to the gate of MN16 and the threshold drop provided by MN16) of a first source follower NMOS transistor having a body connected in common with a source (as shown in Fig. 8 the body if MN16 is connected to its source); and a first control circuit (MP12) configured to control a magnitude of the corrected input voltage output from the source follower (the bias signal at the gate of MP12 will control the magnitude of MN16 under control of the NCSP bias voltage).
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With respect to claim 9, LEE discloses the buffer circuit of claim 1, wherein the load stage (130) comprises: a first differential mirror circuit (MP4 and MP5) having a current mirroring structure and a cascode structure (MP6 and MP7), and configured to mirror the first and second (I_LU and I_LUB) third and fourth (ILDB and ILD) differential currents and the sink currents ;a second differential mirror circuit (MN4 and MN3) having a current mirroring structure and a cascode structure (MN6 and MN7), and configured to mirror the third and fourth(ILDB and ILD) first and second ((I_LU and I_LUB) differential currents and the source current; and a third bias circuit (C1) and a fourth bias circuit (C2) connected between the first differential mirror circuit (MP4 and MP5) and the second differential mirror circuit ((MN4 and MN3) and configured to control an operation in a static state and an amplification operation of the first differential mirror circuit and the second differential mirror circuit.
Allowable Subject Matter
Claims 18-20 allowed.
The following is an examiner’s statement of reasons for allowance:
With respect to claim 18, the prior art of record fails to suggest or disclose wherein the allowing of the output voltage to follow the rising transition or the falling transition of the input voltage further comprises: allowing a first control circuit to be turned on or turned off and a second control circuit to be turned on according to the rising transition of the input voltage or allowing the first control circuit to be turned on and the second control circuit to be turned off according to the falling transition of the input voltage.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHAREEM E ALMO whose telephone number is (571)272-5524. The examiner can normally be reached M-F (8:00am-4:00pm).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Menatoallah Youssef can be reached at M-F (8:00am-4:00pm). The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KHAREEM E ALMO/Examiner, Art Unit 2849
/THOMAS J. HILTUNEN/Primary Examiner, Art Unit 2836
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