DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
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Claims 2-21 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12,148,462. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims are substantially similar with minor differences and not distinguishing the overall appearance of one over the other. Note: the claims of the instant application are anticipated by the claims of the parent, as outlined in the table below.
Current application 18/904,454
U.S. Patent 12,148,462
2. A memory controller comprising: a command and address (CA) interface to be coupled to a first memory module and a second memory module, wherein the memory controller is to send first CA information to the first memory module and the second memory module via the CA interface, and wherein the memory controller is to configure the first memory module to share second CA information to the second memory module via a private bus responsive to the first memory module receiving the first CA information; and a data interface to be coupled to the first memory module, and the second memory module, wherein the memory controller is to receive first data from the first memory module responsive to the first memory module receiving the first CA information, and wherein the memory controller is to receive second data from at least one of the second memory module responsive to the second memory module receiving the second CA information…
1. A memory controller comprising: a command and address (CA) interface to be coupled to a first memory module, a second memory module, and…, wherein the memory controller is to send first CA information to the first memory module, the second memory module, and…, and wherein the memory controller is to configure the first memory module to share second CA information to at least the second memory module or … via a private bus responsive to receiving the first CA information…; and a data interface to be coupled to the first memory module via a first set of point-to-point links, the second memory module…, wherein the memory controller is to receive first data from the first memory module… responsive to receiving the first CA information, and wherein the memory controller is to receive second data from at least one of the second memory module via… point-to-point links or, responsive to receiving the second CA information.
3. The memory controller of claim 2, wherein the second memory module is a continuity module.
2. The memory controller of claim 1, wherein the second memory module or the third memory module is a continuity module.
4. The memory controller of claim 2, wherein the memory controller is integrated in a processor.
3. The memory controller of claim 1, wherein the memory controller is integrated in a processor.
5. The memory controller of claim 2, wherein the memory controller is to be disposed on a motherboard substrate comprising conductive traces of a multi-drop link to couple to the CA interface and point-to-point links to couple to the data interface.
4. The memory controller of claim 1, wherein the memory controller is disposed on a motherboard substrate comprising conductive traces of the multi-drop link and the first, second, and third sets of point-to-point links.
6. The memory controller of claim 2, wherein the first CA information comprises first chip select (CS) information, and the second CA information comprises second CS information.
5. The memory controller of claim 1, wherein the first CA information comprises first chip select (CS) information, and the second CA information comprises second CS information.
7. The memory controller of claim 6, wherein the first CS information comprise a first number of CS bits, and wherein the second CS information comprises the first number of CS bits and a second number of address bits.
6. The memory controller of claim 5, wherein the first CS information comprise a first number of CS bits, and wherein the second CS information comprises the first number of CS bits and a second number of address bits.
8. The memory controller of claim 2, wherein the first CA information comprises a first number of one-hot chip select (CS) bits, and the second CA information comprises the first number of one-hot CS bits and a second number of module address bits.
7. The memory controller of claim 1, wherein the first CA information comprises a first number of one-hot chip select (CS) bits, and the second CA information comprises the first number of one-hot CS bits and a second number of module address bits.
9. A memory controller comprising: a command and address (CA) interface to be coupled to a first memory module and a second memory module, the CA interface to send first CA information to the first memory module, and the CA interface to configure the first memory module to share second CA information to the second memory module via a private bus responsive to the first memory module receiving the first CA information, wherein the first CA information comprises chip select (CS) information, and wherein the second CA information comprises a copy of the CS information; and a data interface to be coupled to the first memory module and the second memory module, wherein the memory controller is to receive first data from the first memory module responsive to the first memory module receiving the first CA information, and wherein the memory controller is to receive second data from the second memory module, responsive to the second memory module receiving the second CA information…
8. A memory controller comprising: a command and address (CA) interface to be coupled to a first memory module and a second memory module via a multi-drop link, wherein the memory controller is to send first CA information to the first memory module …, and wherein the memory controller is to configure/program the first memory module to share second CA information to the second memory module via a private bus responsive to receiving the first CA information via the multi-drop link; and a data interface to be coupled to the first memory module via a first set of point-to-point links and the second memory module via a second set of point-to-point links, wherein the memory controller is to receive first data from the first memory module via the first set of point-to-point links responsive to receiving the first CA information, and wherein the memory controller is to receive second data from the second memory module via the second set of point-to-point links, responsive to receiving the second CA information.
10. The memory controller of claim 9, wherein the second memory module is a continuity module.
9. The memory controller of claim 8, wherein the second memory module is a continuity module.
11. The memory controller of claim 9, wherein the memory controller is integrated in a processor.
10. The memory controller of claim 8, wherein the memory controller is integrated in a processor.
12. The memory controller of claim 9, wherein the memory controller is to be disposed on a motherboard substrate comprising conductive traces of a multi-drop link to couple to the CA interface and point-to-point links to be coupled to the data interface.
11. The memory controller of claim 8, wherein the memory controller is disposed on a motherboard substrate comprising conductive traces of the multi-drop link and the first, second, and third sets of point-to-point links.
13. The memory controller of claim 9,
wherein the first CA information comprises first chip select (CS) information and the second CA information comprises second CS information.
12. The memory controller of claim 8, wherein the first CA information comprises first chip select (CS) information and the second CA information comprises second CS information.
14. The memory controller of claim 13, wherein the first CS information comprise a first number of CS bits, and wherein the second CS information comprises the first number of CS bits and a second number of address bits.
13. The memory controller of claim 12, wherein the first CS information comprise a first number of CS bits, and wherein the second CS information comprises the first number of CS bits and a second number of address bits.
15. The memory controller of claim 9, wherein the first CA information comprises a first number of one-hot chip select (CS) bits, and the second CA information comprises the first number of one-hot CS bits and a second number of module address bits.
14. The memory controller of claim 8, wherein the first CA information comprises a first number of one-hot chip select (CS) bits, and the second CA information comprises the first number of one-hot CS bits and a second number of module address bits.
16. A method of operating a memory controller, the method comprising: sending, using a command and address (CA) interface, first CA information to a first memory module and a second memory module; configuring the first memory module to share second CA information to the second memory module via a private bus responsive to the first memory module receiving the first CA information; receiving, using a data interface, first data from the first memory module responsive to the first memory module receiving the first CA information; and receiving, using the data interface, second data from at least one of the second memory module, responsive to the second memory module receiving the second CA information…
15. A method of operating a memory controller, the method comprising: sending, using command and address
(CA) interface, first CA information to a first memory module, a second memory module,… configuring the first memory module to share second CA information to at least the second memory module or the third memory module via a private bus responsive to receiving the first CA information…; receiving, using a data interface, first data from the first memory module via a first set of point-to-point links responsive to receiving the first CA information; and receiving, using the data interface, second data from at least one of the second memory module…, responsive to receiving the second CA information.
17. The method of claim 16, wherein the second memory module is a continuity module.
16. The method of claim 15, wherein the second memory module or the third memory module is a continuity module.
18. The method of claim 16, wherein the first CA information comprises first chip select (CS) information, and the second CA information comprises second CS information.
17. The method of claim 15, wherein the first CA information comprises first chip select (CS) information, and the second CA information comprises second CS information.
19. The method of claim 18, wherein the first CS information comprise a first number of CS bits, and wherein the second CS information comprises the first number of CS bits and a second number of address bits.
18. The method of claim 17, wherein the first CS information comprise a first number of CS bits, and wherein the second CS information comprises the first number of CS bits and a second number of address bits.
20. The method of claim 16, wherein the first CA information comprises a first number of one-hot chip select (CS) bits, and the second CA information comprises the first number of one-hot CS bits and a second number of module address bits.
19. The method of claim 15, wherein the first CA information comprises a first number of one-hot chip select (CS) bits, and the second CA information comprises the first number of one-hot CS bits and a second number of module address bits.
21. The method of claim 16, wherein the first CA information comprises a command, and wherein the second CA information comprises the command.
20. The method of claim 15, wherein the first CA information comprises a command, and wherein the second CA information comprises the command.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Khandekar et al. (US 6,639,820), LaBerge (US 8,006,057), Lee (US 7,707,355), Doblar et al. (US 2004/0123016), Wong et al. (US 2005/0058001) and Choi (US 9,753,651) do teach memory system comprised of command and/or address interface including multi-drop links that connect memory modules with memory controllers.
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/Elias Mamo/Primary Examiner, Art Unit 2184