DETAILED ACTION
Response to Amendment
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-15 are rejected under 35 U.S.C. 103 as being unpatentable over Hass et al. (U.S. Patent Number 6,330,977) and Wallinger et al. (U.S. Patent Application Publication Number 2024/0361816).
Regarding Claim 1, Hass discloses a circuit system (Figure 24B) comprising:
a first integrated circuit (Figure 24B, item 2414);
a second integrated circuit (Figure 24B, item 2400); and
a single-line communication line that couples the first integrated circuit and the second integrated circuit (Figure 24B, item 2412, Column 42, lines 30-32),
wherein the first integrated circuit and the second integrated circuit are coupled via an open-drain bidirectional (Column 6, lines 35-37) single-line interface using the communication line so as to allow them to communicate with each other (Column 42, lines 32-36),
wherein a plurality of low-level durations defined in a protocol (Column 42, lines 50-65) corresponding to a plurality of commands respectively (Column 49, lines 54-63 and Column 50, lines 1-7; i.e., both of the integrated circuits 2414 and 2400 can transmit commands and responses over the single-line communication line 2412 using “low times” [i.e., logic zeros] defined by the 1-Wire bus protocol; for example, a read command may include four logic zeros [“low times”] followed by four logic ones), and
wherein the first integrated circuit is structured to fix the electric potential of the communication line to the low level for the low-level duration that corresponds to a command to be transmitted, so as to allow any one of the plurality of commands to be transmitted as a first command to the second integrated circuit (Column 49, lines 54-63 and Column 50, lines 1-7; i.e., the first integrated circuit 2414 pulls the line 2412 low [“fix an electric potential of the communication line to a low level”] whenever it desires to transmit any one of a plurality of commands such as a reset or read command).
Hass does not expressly disclose each of the low-level durations being a length of a single period during which an electric potential of the communication line is fixed at a low level.
In the same field of endeavor (e.g., single line communications), Wallinger teaches each of the low-level durations being a length of a single period during which an electric potential of the communication line (Figure 1, item 195) is fixed at a low level (paragraphs 0024 and 0038).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined Wallinger’s teachings of single line communications with the teachings of Hass, for the purpose of expanding the number of commands that can be transmitted on the line (i.e., commands can be sent using only low level durations rather than both low and high level durations).
Regarding Claim 2, Hass discloses wherein, upon receiving the first command from among the plurality of commands, the second integrated circuit fixes the electric potential of the communication line to the low level so as to return an acknowledgment that corresponds to the first command to the first integrated circuit (Column 49, lines 58-63; i.e., the presence detect signal that is sent to the first integrated circuit 2414 acts as an acknowledgment since it is sent in response to the reset signal).
Regarding Claim 3, Hass discloses wherein, upon receiving the first command from among the plurality of commands, the second integrated circuit fixes the electric potential of the communication line to the low level during the same time as the low time that corresponds to the first command, so as to return an acknowledgment that is different for each command from among the plurality of commands (Column 50, lines 28-40).
Regarding Claim 4, Hass discloses wherein, upon receiving no acknowledgment that corresponds to the first command, the first integrated circuit executes error processing (Column 45, lines 34-35; i.e., the “error processing” would be that the first integrated circuit 2414 discontinues the communication process on the single-wire line).
Regarding Claim 5, Hass discloses wherein the second integrated circuit comprises a second sequencer, and wherein the plurality of commands is defined corresponding to transitions of a plurality of states of the second sequencer (Column 50, lines 28-67; i.e., the second integrated circuit 2400 sequences the transitions of when it pulls the line 2402 low and high based on the read command that is sent from the first integrated circuit 2414).
Regarding Claim 6, Hass discloses wherein the low time that corresponds to a synchronization signal is defined in the protocol,
wherein, after the transmission of the first command, the first integrated circuit fixes the electric potential of the communication line to the low level during the low time that corresponds to the synchronization signal, so as to allow the synchronization signal to be transmitted to the second integrated circuit, and
wherein the second sequencer operates in synchronization with the synchronization signal (Column 49, lines 52-67; i.e., by transmitting a reset signal and getting a presence detect signal in response, the two integrated circuits 2414 and 2400 synchronize their operations).
Regarding Claim 7, Hass discloses wherein, upon receiving the synchronization signal, the second integrated circuit fixes the electric potential of the communication line to the low level during the low time that corresponds to the synchronization signal (Column 49, lines 54-57; i.e., both the lowering of the line 2402 and subsequent releasing of the line 2402 is considered equivalent to the claimed “low time that corresponds to the synchronization signal”), so as to return an acknowledgment that corresponds to the synchronization signal to the first integrated circuit (Column 49, lines 52-67; i.e., by transmitting a reset signal and getting a presence detect signal in response, the two integrated circuits 2414 and 2400 synchronize their operations).
Regarding Claim 8, Hass discloses wherein the first integrated circuit comprises a first sequencer (Column 49, lines 52-67; i.e., the component within microcontroller 2414 that performs the reset sequence is equivalent to the “first sequencer”), and
wherein the first sequencer operates in synchronization with the acknowledgment that corresponds to the synchronization signal (Column 49, lines 52-67; i.e., the reset sequence operates in synchronization with the presence detect signal [“the acknowledgment”] that is transmitted by the module 2400).
Regarding Claim 9, Hass discloses wherein, upon receiving no acknowledgment (i.e., not receiving the presence detect signal) that corresponds to the synchronization signal transmitted from the first integrated circuit itself, the first integrated circuit executes error processing (Column 45, lines 34-35; i.e., the “error processing” would be that the first integrated circuit 2414 discontinues the communication process on the single-wire line).
Regarding Claim 10, Hass discloses wherein the first integrated circuit is structured as a power supply management circuit, and wherein the second integrated circuit is structured as a power supply circuit or a power supply management circuit (Column 48, lines 28-36; i.e., both the first integrated circuit 2414 and second integrated circuit 2400 manage their own power supply, either from an internal battery or from an external source and therefore “power supply management circuits”).
Regarding Claim 11, Hass discloses a main integrated circuit (Figure 24A, item 2404/Figure 24B, item 2414) that allows a circuit system to be structured together with an additional component integrated circuit (Figure 24B, item 2400), the main integrated circuit comprising:
a first interface pin (Column 49, lines 19-27) to be coupled to the additional component integrated circuit via a single-line communication line (Figure 24B, item 2412, Column 42, lines 30-32); and
a first interface circuit structured in an open-drain format coupled to the first interface pin (Column 42, lines 32-36),
wherein a plurality of low-level durations to be used as a plurality of commands are defined in a protocol (Column 42, lines 50-65) corresponding to the plurality of commands respectively (Column 49, lines 54-63 and Column 50, lines 1-7; i.e., both of the integrated circuits 2414 and 2400 can transmit commands and responses over the single-line communication line 2412 using “low times” [i.e., logic zeros] defined by the 1-Wire bus protocol; for example, a read command may include four logic zeros [“low times”] followed by four logic ones), and
wherein the first interface circuit fixes the electric potential of the communication line to the low level for the low-level duration that corresponds to a command to be transmitted, so as to allow any one of the plurality of commands to be transmitted as a first command to the additional component integrated circuit (Column 49, lines 54-63 and Column 50, lines 1-7; i.e., the first integrated circuit 2414 pulls the line 2412 low [“fix an electric potential of the communication line to a low level”] whenever it desires to transmit any one of a plurality of commands such as a reset or read command).
Hass does not expressly disclose each of the low-level durations being a length of a single period during which an electric potential of the communication line is fixed at a low level.
In the same field of endeavor, Wallinger teaches each of the low-level durations being a length of a single period during which an electric potential of the communication line (Figure 1, item 195) is fixed at a low level (paragraphs 0024 and 0038).
The motivation discussed above with regards to Claim 1 applies equally as well to Claim 11.
Regarding Claim 12, Hass discloses an additional component integrated circuit (Figure 24B, item 2400) that allows a circuit system to be structured together with a main integrated circuit (Figure 24A, item 2404/Figure 24B, item 2414), the additional component integrated circuit comprising:
a second interface pin (Column 49, lines 19-27; i.e., module 2400 would have a pin that connects to the line 2412 like the main integrated circuit 2404 has) to be coupled to the main integrated circuit via a single-line communication line (Figure 24B, item 2412, Column 42, lines 30-32); and
a second interface circuit structured in an open-drain format coupled to the second interface pin (Column 42, lines 32-36),
wherein a plurality of low-level durations to be used as a plurality of commands are defined in a protocol (Column 42, lines 50-65) corresponding to the plurality of commands respectively (Column 49, lines 54-63 and Column 50, lines 1-7; i.e., both of the integrated circuits 2414 and 2400 can transmit commands and responses over the single-line communication line 2412 using “low times” [i.e., logic zeros] defined by the 1-Wire bus protocol; for example, a read command may include four logic zeros [“low times”] followed by four logic ones), and
wherein the second interface circuit detects a duration during which the electric potential of the communication line is fixed to the low level by the main integrated circuit, so as to allow a first command that corresponds to the detected duration to be received from the main integrated circuit from among the plurality of commands (Column 49, lines 54-63 and Column 50, lines 1-7; i.e., the first integrated circuit 2414 pulls the line 2412 low [“fix an electric potential of the communication line to a low level”] whenever it desires to transmit any one of a plurality of commands such as a reset or read command).
Hass does not expressly disclose each of the low-level durations being a length of a single period during which an electric potential of the communication line is fixed at a low level.
In the same field of endeavor, Wallinger teaches each of the low-level durations being a length of a single period during which an electric potential of the communication line (Figure 1, item 195) is fixed at a low level (paragraphs 0024 and 0038).
The motivation discussed above with regards to Claim 1 applies equally as well to Claim 12.
Regarding Claim 13, Wallinger teaches wherein a handoff duration is defined to be longer than a transition time from the low level to a high level after the low-level duration that corresponds to the first command (Figure 3, item 395, paragraph 0035; i.e., the state “hands off” from the present state to the next state, which occurs with a duration longer than the transition time from the low level to the high level).
Regarding Claim 14, Wallinger teaches wherein a handoff duration is defined to be longer than a transition time from the low level to a high level after the low-level duration that corresponds to the first command (Figure 3, item 395, paragraph 0035; i.e., the state “hands off” from the present state to the next state, which occurs with a duration longer than the transition time from the low level to the high level).
Regarding Claim 15, Wallinger teaches wherein a handoff duration is defined to be longer than a transition time from the low level to a high level after the reception of the low-level duration that corresponds to the first command (Figure 3, item 395, paragraph 0035; i.e., the state “hands off” from the present state to the next state, which occurs with a duration longer than the transition time from the low level to the high level).
Response to Arguments
Applicant’s arguments with respect to claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FAISAL M ZAMAN whose telephone number is (571)272-6495. The examiner can normally be reached Monday - Friday, 8 am - 5 pm, alternate Fridays.
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/FAISAL M ZAMAN/ Primary Examiner, Art Unit 2175
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