DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to because the unlabeled rectangular boxes shown in the drawings (Figures 1 and 5) should be provided with descriptive text labels. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hass et al. (U.S. Patent Number 6,330,977).
Regarding Claim 1, Hass discloses a circuit system (Figure 24B) comprising:
a first integrated circuit (Figure 24B, item 2414);
a second integrated circuit (Figure 24B, item 2400); and
a single-line communication line that couples the first integrated circuit and the second integrated circuit (Figure 24B, item 2412, Column 42, lines 30-32),
wherein the first integrated circuit and the second integrated circuit are coupled via an open-drain bidirectional (Column 6, lines 35-37) single-line interface using the communication line so as to allow them to communicate with each other (Column 42, lines 32-36),
wherein a plurality of low times are defined in a protocol (Column 42, lines 50-65) corresponding to a plurality of commands respectively (Column 49, lines 54-63 and Column 50, lines 1-7; i.e., both of the integrated circuits 2414 and 2400 can transmit commands and responses over the single-line communication line 2412 using “low times” [i.e., logic zeros] defined by the 1-Wire bus protocol; for example, a read command may include four logic zeros [“low times”] followed by four logic ones), and
wherein the first integrated circuit is structured to fix an electric potential of the communication line to a low level during the low time that corresponds to a command to be transmitted, so as to allow any one of the plurality of commands to be transmitted as a first command to the second integrated circuit (Column 49, lines 54-63 and Column 50, lines 1-7; i.e., the first integrated circuit 2414 pulls the line 2412 low [“fix an electric potential of the communication line to a low level”] whenever it desires to transmit any one of a plurality of commands such as a reset or read command).
Regarding Claim 2, Hass discloses wherein, upon receiving the first command from among the plurality of commands, the second integrated circuit fixes the electric potential of the communication line to the low level so as to return an acknowledgment that corresponds to the first command to the first integrated circuit (Column 49, lines 58-63; i.e., the presence detect signal that is sent to the first integrated circuit 2414 acts as an acknowledgment since it is sent in response to the reset signal).
Regarding Claim 3, Hass discloses wherein, upon receiving the first command from among the plurality of commands, the second integrated circuit fixes the electric potential of the communication line to the low level during the same time as the low time that corresponds to the first command, so as to return an acknowledgment that is different for each command from among the plurality of commands (Column 50, lines 28-40).
Regarding Claim 4, Hass discloses wherein, upon receiving no acknowledgment that corresponds to the first command, the first integrated circuit executes error processing (Column 45, lines 34-35; i.e., the “error processing” would be that the first integrated circuit 2414 discontinues the communication process on the single-wire line).
Regarding Claim 5, Hass discloses wherein the second integrated circuit comprises a second sequencer, and wherein the plurality of commands is defined corresponding to transitions of a plurality of states of the second sequencer (Column 50, lines 28-67; i.e., the second integrated circuit 2400 sequences the transitions of when it pulls the line 2402 low and high based on the read command that is sent from the first integrated circuit 2414).
Regarding Claim 6, Hass discloses wherein the low time that corresponds to a synchronization signal is defined in the protocol,
wherein, after the transmission of the first command, the first integrated circuit fixes the electric potential of the communication line to the low level during the low time that corresponds to the synchronization signal, so as to allow the synchronization signal to be transmitted to the second integrated circuit, and
wherein the second sequencer operates in synchronization with the synchronization signal (Column 49, lines 52-67; i.e., by transmitting a reset signal and getting a presence detect signal in response, the two integrated circuits 2414 and 2400 synchronize their operations).
Regarding Claim 7, Hass discloses wherein, upon receiving the synchronization signal, the second integrated circuit fixes the electric potential of the communication line to the low level during the low time that corresponds to the synchronization signal (Column 49, lines 54-57; i.e., both the lowering of the line 2402 and subsequent releasing of the line 2402 is considered equivalent to the claimed “low time that corresponds to the synchronization signal”), so as to return an acknowledgment that corresponds to the synchronization signal to the first integrated circuit (Column 49, lines 52-67; i.e., by transmitting a reset signal and getting a presence detect signal in response, the two integrated circuits 2414 and 2400 synchronize their operations).
Regarding Claim 8, Hass discloses wherein the first integrated circuit comprises a first sequencer (Column 49, lines 52-67; i.e., the component within microcontroller 2414 that performs the reset sequence is equivalent to the “first sequencer”), and
wherein the first sequencer operates in synchronization with the acknowledgment that corresponds to the synchronization signal (Column 49, lines 52-67; i.e., the reset sequence operates in synchronization with the presence detect signal [“the acknowledgment”] that is transmitted by the module 2400).
Regarding Claim 9, Hass discloses wherein, upon receiving no acknowledgment (i.e., not receiving the presence detect signal) that corresponds to the synchronization signal transmitted from the first integrated circuit itself, the first integrated circuit executes error processing (Column 45, lines 34-35; i.e., the “error processing” would be that the first integrated circuit 2414 discontinues the communication process on the single-wire line).
Regarding Claim 10, Hass discloses wherein the first integrated circuit is structured as a power supply management circuit, and wherein the second integrated circuit is structured as a power supply circuit or a power supply management circuit (Column 48, lines 28-36; i.e., both the first integrated circuit 2414 and second integrated circuit 2400 manage their own power supply, either from an internal battery or from an external source and therefore “power supply management circuits”).
Regarding Claim 11, Hass discloses a main integrated circuit (Figure 24A, item 2404/Figure 24B, item 2414) that allows a circuit system to be structured together with an additional component integrated circuit (Figure 24B, item 2400), the main integrated circuit comprising:
a first interface pin (Column 49, lines 19-27) to be coupled to the additional component integrated circuit via a single-line communication line (Figure 24B, item 2412, Column 42, lines 30-32); and
a first interface circuit structured in an open-drain format coupled to the first interface pin (Column 42, lines 32-36),
wherein a plurality of low times to be used as a plurality of commands are defined in a protocol (Column 42, lines 50-65) corresponding to the plurality of commands (Column 49, lines 54-63 and Column 50, lines 1-7; i.e., both of the integrated circuits 2414 and 2400 can transmit commands and responses over the single-line communication line 2412 using “low times” [i.e., logic zeros] defined by the 1-Wire bus protocol; for example, a read command may include four logic zeros [“low times”] followed by four logic ones), and
wherein the first interface circuit fixes an electric potential of the communication line to a low level during the low time that corresponds to a command to be transmitted, so as to allow any one of the plurality of commands to be transmitted as a first command to the additional component integrated circuit (Column 49, lines 54-63 and Column 50, lines 1-7; i.e., the first integrated circuit 2414 pulls the line 2412 low [“fix an electric potential of the communication line to a low level”] whenever it desires to transmit any one of a plurality of commands such as a reset or read command).
Regarding Claim 12, Hass discloses an additional component integrated circuit (Figure 24B, item 2400) that allows a circuit system to be structured together with a main integrated circuit (Figure 24A, item 2404/Figure 24B, item 2414), the additional component integrated circuit comprising:
a second interface pin (Column 49, lines 19-27; i.e., module 2400 would have a pin that connects to the line 2412 like the main integrated circuit 2404 has) to be coupled to the main integrated circuit via a single-line communication line (Figure 24B, item 2412, Column 42, lines 30-32); and
a second interface circuit structured in an open-drain format coupled to the second interface pin (Column 42, lines 32-36),
wherein a plurality of low times to be used as a plurality of commands are defined in a protocol (Column 42, lines 50-65) corresponding to the plurality of commands (Column 49, lines 54-63 and Column 50, lines 1-7; i.e., both of the integrated circuits 2414 and 2400 can transmit commands and responses over the single-line communication line 2412 using “low times” [i.e., logic zeros] defined by the 1-Wire bus protocol; for example, a read command may include four logic zeros [“low times”] followed by four logic ones), and
wherein the second interface circuit detects a time during which an electric potential of the communication line is fixed to a low level by the main integrated circuit, so as to allow a first command that corresponds to the detected time to be received from the main integrated circuit from among the plurality of commands (Column 49, lines 54-63 and Column 50, lines 1-7; i.e., the first integrated circuit 2414 pulls the line 2412 low [“fix an electric potential of the communication line to a low level”] whenever it desires to transmit any one of a plurality of commands such as a reset or read command).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure because each reference discloses a system for communicating between two integrated circuits using a single-wire communication line.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FAISAL M ZAMAN whose telephone number is (571)272-6495. The examiner can normally be reached Monday - Friday, 8 am - 5 pm, alternate Fridays.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrew J. Jung can be reached at 571-270-3779. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/FAISAL M ZAMAN/ Primary Examiner, Art Unit 2175