DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 10/02/2024, 12/04/2024 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claim 2, 17 and 18 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 16, 6 and 15, respectively of U.S. Patent No. 11,758,515 B2 (see Table below).
Instant Application (18/904,770)
U.S. Patent No. 11,758,515 B2
2. A digital circuit, comprising:
a timer array configured to generate a plurality of timed triggers, the timer array comprising:
a reference counter operating from a reference clock;
a count translation logic block that is configured to translate a number of reference clock counts corresponding to each timed trigger of the plurality of timed triggers to a respective target offset value of the reference counter; and
a target translation logic block that is configured to translate, for each timed trigger of the plurality of timed triggers, a current value of the reference counter to an offset value based on a number of reference clock counts to the respective target offset value of the reference counter.
14. A digital circuit, comprising:
a timer array configured to generate a plurality of timed triggers, the timer array comprising:
a reference counter operating from a reference clock; and
a count translation logic block that is configured to translate a number of reference clock counts corresponding to each timed trigger of the plurality of timed triggers to a target offset value of the reference counter;
an array of a plurality of target registers configured to store respective target offset values of the plurality of timed triggers; a set valid flag logic block that is configured to: set a valid flag indicative of a requested timed trigger, and reset the valid flag indicative of completion of the requested timed trigger; an array of a plurality of valid flag registers configured to store respective valid flag values of the plurality of timed triggers; and an array of a plurality of comparators configured to compare a current value of the reference counter to the respective target offset values of the plurality of timed triggers.
16. The digital circuit of claim 14, wherein the timer array further comprises:
a target translation logic block that is configured to translate, for each time trigger of the plurality of timed triggers, a current value of the reference counter to an offset value based on a number of reference clock counts to the target offset value of the reference counter.
17. A radio frequency (RF) device, comprising:
an RF circuit configured to process an RF signal; and
a digital circuit configured to communicate with a master device separate from the RF device, the digital circuit comprising:
a timer array configured to generate a plurality of timed triggers for synchronization of events between the master device and the RF circuit, the timer array comprising:
a reference counter operating from a reference clock;
a count translation logic block that is configured to translate a number of reference clock counts corresponding to each timed trigger of the plurality of timed triggers to a target offset value of the reference counter; and
a target translation logic block that is configured to translate, for each time trigger of the plurality of timed triggers, a current value of the reference counter to an offset value based on a number of reference clock counts to the target offset value of the reference counter.
1. A radio frequency (RF) device, comprising:
an RF circuit configured to process an RF signal; and
a digital circuit configured to communicate with a master device separate from the RF device, the digital circuit comprising:
a timer array configured to generate a plurality of timed triggers for synchronization of events between the master device and the RF circuit, the timer array comprising:
an array of a plurality of target registers configured to store respective target offset values of the plurality of timed triggers;
a reference counter operating from a reference clock;
a count translation logic block that is configured to translate a number of reference clock counts corresponding to each timed trigger of the plurality of timed triggers to a target offset value of the reference counter; and a set valid flag logic block that is configured to: set a valid flag based on the time of request of the timed trigger, and reset the valid flag based on a time of completion of the timed trigger.
6. The RF device of claim 1, wherein the timer array further comprises:
a target translation logic block that is configured to translate, for each time trigger of the plurality of timed triggers, a current value of the reference counter to an offset value based on a number of reference clock counts to the target offset value of the reference counter.
18. A method for generating a plurality of timed trigger events, the method comprising:
providing a reference counter operating from a reference clock;
translating a requested timed trigger event of the plurality of timed trigger events into a target offset value of the reference counter;
translating a current value of the reference counter to an offset value based on a number of reference clock counts to the target offset value of the reference counter; and
generating the requested timed trigger event when the offset value is equal to the target offset value.
15. A method for generating a timed trigger event, the method comprising:
providing a reference counter operating from a reference clock;
establishing a plurality of timers by assigning to each timer a target offset register, a set valid flag register, and a comparator; translating a requested timed trigger event into a target offset value of the reference counter and
storing the target offset value to the target offset register of a respective timer of the plurality timers; setting a valid flag indicative of the requested timed trigger event and storing a value of the valid flag to the set valid flag register of the respective timer; based on the translating and the setting, comparing via a comparator of the respective timer a current value of the reference counter to the target offset value; and
based on the comparing,
generating the requested timed trigger event when the current value is equal to the target offset value.
Allowable Subject Matter
Claims 2, 17 and 18 would be allowable if rewritten or amended to overcome the nonstatutory double patenting rejections, set forth in this Office action.
Claims 3-16 and 19-21are objected to as being dependent upon a rejected base claims 2 and 18, respectively, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 2, the prior art Mishra (US 2021/0181788 A1) discloses a digital circuit, comprising: a timer array configured to generate a plurality of timed triggers, the timer array comprising: a reference counter operating from a reference clock; a count translation logic block that is configured to translate a number of reference clock counts corresponding to each timed trigger of the plurality of timed triggers to a respective target offset value of the reference counter.
Prior arts do not disclose or fairly suggest, alone or in combination, a digital circuit, comprising: a target translation logic block that is configured to translate, for each timed trigger of the plurality of timed triggers, a current value of the reference counter to an offset value based on a number of reference clock counts to the respective target offset value of the reference counter.
Regarding claim 17, this claim has substantially the same subject matter as that in claim 2. Therefore, claim 17 is allowable under the same rationale as claim 2 above.
Regarding claim 18, this claim has substantially the same subject matter as that in claim 2. Therefore, claim 18 is allowable under the same rationale as claim 2 above.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
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/SEOKJIN KIM/Primary Examiner, Art Unit 2844