Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on October 2, 2024 and May 9, 2025 were filed is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The following title is suggested:
--High Frequency Semiconductor Device Including A Third Substrate Having An Intermediate Layer Pattern--
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1, 2, 4-15 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 2, 4-15 of copending Application No. 19/363,226, hereinafter Copending, in view of Meliane et al. (U.S. Pub. 2018/0061725), hereinafter Meliane.
Instant Application Claim 1
Copending Claim 1
A semiconductor device comprising:
a first substrate including a first insulating substrate, a first wiring pattern layer and a plurality of first front-side pads formed on a front surface of the first insulating substrate, and a first base portion constituted by thick copper and formed on a back surface of the first insulating substrate, wherein a first opening reaching a front surface of the first base portion from the front surface is formed in the first insulating substrate;
a first semiconductor element mounted and fixed on the front surface of the first base portion of the first substrate via a first heat sink in the first opening of the first substrate, and electrically connected to a line constituting the first wiring pattern layer of the first substrate;
a second substrate including a second insulating substrate, a second wiring pattern layer and a plurality of second front-side pads formed on a front surface of the second insulating substrate, and a second base portion constituted by thick copper and formed on a back surface of the second insulating substrate, wherein a second opening reaching a front surface of the second base portion from the front surface is formed in the second insulating substrate;
a second semiconductor element mounted and fixed on the front surface of the second base portion of the second substrate via a second heat sink in the second opening of the second substrate, and electrically connected to a line constituting the second wiring pattern layer of the second substrate; and
a third substrate arranged between the first substrate and the second substrate in such a manner as to face the first substrate and the second substrate, the third substrate including a plurality of third back-side pads on a back surface thereof, each of the third back-side pads being connected to a corresponding one of the plurality of first front-side pads of the first substrate by a connection member, and a plurality of third front-side pads on a front surface thereof, each of the third front-side pads being connected to each of the plurality of second front-side pads of the second substrate by a connection member.
A semiconductor device comprising:
a first substrate
wherein the first substrate includes a first dielectric substrate in which the plurality of first front side pads is formed around a front surface
a first wiring pattern layer formed on the front surface of the first dielectric substrate
a first ground conductor constituted by thick copper formed on a back surface of the first dielectric substrate
a first opening reaching the front surface of the first ground conductor from the front surface of the first dielectric substrate
the first semiconductor element
mounted and fixed on a front surface of the first ground conductor in a first opening
electrically connected to a line constituting the first wiring pattern layer
a second substrate
the second substrate includes a second dielectric substrate in which the plurality of second front side pads is formed around a front surface
a second wiring pattern layer formed on the front surface of the second dielectric substrate
a second ground conductor constituted by thick copper formed on a back surface of the second dielectric substrate
a second opening reaching the front surface of the second ground conductor from the front surface of the second dielectric substrate.
the second semiconductor element
is mounted and fixed on a front surface of the second ground conductor in a second opening
electrically connected to a line constituting the second wiring pattern layer
a third substrate disposed between the first substrate and the second substrate in such a manner as to face the front surface of the first substrate and the front surface of the second substrate,
a plurality of third front side pads arranged around a front surface in such a manner as to face each of the plurality of second front side pads in the second substrate; a plurality of first connection members each electrically connecting a corresponding first front side pad of a plurality of first front side pads on the first substrate and a corresponding third back side pad of a plurality of third back side pads on the third substrate; a plurality of second connection members each electrically connecting a corresponding second front side pad of the plurality of second front side pads on the second substrate and a corresponding third front side pad of the plurality of third front side pads on the third substrate;
Copending does not include that the first semiconductor element is mounted and fixed via a first heat sink nor that the second semiconductor element is fixed via a second heat sink.
Meliane teaches a semiconductor device ((106A); Fig. 4, Paragraph [0050]), comprising:
- a first semiconductor element ((44); Fig. 4, Paragraph [0034]) mounted and fixed on the front surface of the first base portion ((110); Fig. 4, Paragraph [0049]) of the first substrate ((12); Fig. 4, Paragraph [0030]) via a first heat sink ((22); Fig. 4, Paragraph [0031]) in the first opening of the first substrate
- a second semiconductor element ((48); Fig. 4, Paragraph [0034]) mounted and fixed on the front surface of the second base portion ((100) and (98); Fig. 4, Paragraph [0045]) of the second substrate ((14); Fig. 4, Paragraph [0030]) via a second heat sink ((34) and (32); Fig. 4, Paragraph [0032]) in the second opening of the second substrate.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Meliane into the claimed device of Copending such that that the first semiconductor element is mounted and fixed via a first heat sink and that the second semiconductor element is fixed via a second heat sink. This would be due to the fact that doing so would improve thermal management by directing heat generated by the semiconductor devices away from them and towards the ground conductors (Melaine, Paragraph [0050]).
Instant Application Claim 2
Modified Copending Claim 2
semiconductor device according to claim 1,
wherein the first insulating substrate in the first substrate and the second insulating substrate in the second substrate are constituted by a same material and have a same thickness,
the first wiring pattern layer in the first substrate and the second wiring pattern layer in the second substrate are constituted by a same material and have a same thickness, and
the first base portion in the first substrate and the second base portion in the second substrate are constituted by a same material and have a same thickness.
semiconductor device according to claim 1,
wherein the first dielectric substrate in the first substrate and the second dielectric substrate in the second substrate are constituted by a same material and have a same thickness,
the first wiring pattern layer formed on the front surface of the first dielectric substrate and the second wiring pattern layer formed on the front surface of the second dielectric substrate are constituted by a same material and have a same thickness, and
the first ground conductor in the first substrate and the second ground conductor in the second substrate are constituted by a same material and have a same thickness.
Instant Application Claim 4
Modified Copending Claim 4
semiconductor device according to claim 1,
wherein the first semiconductor element is a semiconductor element having a high output amplification function, the second semiconductor element is a semiconductor element having a power supply control function, and the third substrate is a substrate that relays electrical connection between the first substrate and the second substrate.
semiconductor device according to claim 1,
wherein the first semiconductor element is a semiconductor element having a high output amplification function, the second semiconductor element is a semiconductor element having a power supply control function, and the third substrate is a dielectric substrate that relays electrical connection between the first substrate and the second substrate.
Instant Application Claim 5
Modified Copending Claim 5
semiconductor device according to claim 4,
See Claim 4 above for repeated limitations
further comprising a third semiconductor element having a driver amplification function, the third semiconductor element being mounted and fixed on the front surface of the second base portion of the second substrate via the second heat sink in the second opening of the second substrate, and electrically connected to the line constituting the second wiring pattern layer of the second substrate.
semiconductor device according to claim 1,
wherein the first semiconductor element is a semiconductor element having a high output amplification function, the second semiconductor element is a semiconductor element having a power supply control function, and the third substrate is a dielectric substrate that relays electrical connection between the first substrate and the second substrate,
the semiconductor device further comprising a third semiconductor element having a driver amplification function, the third semiconductor element being electrically connected to the line constituting the second wiring pattern layer on the front surface of the second ground conductor in the second opening of the second substrate.
Copending does not include that the third semiconductor element is mounted and fixed via a third heat sink.
Meliane teaches a semiconductor device ((106A); Fig. 4, Paragraph [0050]), comprising:
- a third semiconductor element ((50); Fig. 4, Paragraph [00]) mounted and fixed on the front surface of the second base portion ((100) and (98); Fig. 4, Paragraph [0045]) of the second substrate ((14); Fig. 4, Paragraph [0030]) via the second heat sink ((34) and (32); Fig. 4, Paragraph [0032]) in the second opening of the second substrate.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Meliane into the claimed device of Copending such that the third semiconductor element is mounted and fixed via a third heat sink. This would be due to the fact that doing so would improve thermal management by directing heat generated by the semiconductor device away from tit and towards the ground conductor (Melaine, Paragraph [0050]).
Instant Application Claim 6
Modified Copending Claim 7
semiconductor device according to claim 1,
wherein the first semiconductor element is a semiconductor element having a high output amplification function, the second semiconductor element is a semiconductor element having a power supply control function, at least one of the plurality of second front-side pads formed on the front surface of the second insulating substrate is arranged in a central portion of the front surface of the second insulating substrate, and the third substrate is a substrate that relays electrical connection between a front-side pad arranged in a central portion of the second substrate and a front-side pad arranged at a side portion of the second substrate.
semiconductor device according to claim 1,
wherein the first semiconductor element is a semiconductor element having a high output amplification function, the second semiconductor element is a semiconductor element having a power supply control function, at least one of the plurality of second front side pads formed on the front surface of the second dielectric substrate is arranged in a central portion of the front surface of the second dielectric substrate, and the third substrate is a substrate that relays electrical connection between a second front side pad arranged in a central portion of the second substrate and a second front side pad arranged at a side portion of the second substrate.
Regarding Claim 7, the initially modified Copending teaches the limitations of Claim 6 upon which it depends, but does not additionally include:
a heat radiator mounted on a back surface of the first base portion in the first substrate.
Meliane teaches a semiconductor device ((106A); Fig. 4, Paragraph [0050]), comprising:
a heat radiator ((112); Fig. 4, Paragraph [0050]) mounted on a back surface of the first base portion (e.g. (100) and (98); Fig. 4, Paragraph [0045]) in the first substrate ((12); Fig. 4, Paragraph [0030]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the further teachings of Meliane into the claimed device of Copending such that a heat radiator mounted on a back surface of the first base portion in the first substrate. This would be due to the fact that doing so would improve thermal management by irradiating heat generated by the semiconductor devices (Melaine, Paragraph [0050]).
Instant Application Claim 8
Modified Copending Claim 9
semiconductor device according to claim 1,
wherein the third substrate has an intermediate layer pattern between an uppermost layer pattern located on the front surface having the third front-side pads and a lowermost layer pattern located on a back surface having the third back-side pads, and the intermediate layer pattern includes a wiring path for electrically connecting the third front-side pad and the third back-side pad corresponding to the third front-side pad.
semiconductor device according to claim 1,
wherein the third substrate has an intermediate layer pattern between an uppermost layer pattern located on the front surface having the third front side pads and a lowermost layer pattern located on a back surface having the third back side pads, and the intermediate layer pattern includes a line for electrically connecting the third front side pad and the third back side pad corresponding to the third front side pad.
Instant Application Claim 9
Modified Copending Claim 10
semiconductor device according to claim 8,
wherein the intermediate layer pattern includes a first intermediate layer pattern and a second intermediate layer pattern that are arranged to face each other, and a third intermediate layer pattern that is arranged between the first intermediate layer pattern and the second intermediate layer pattern in such a manner as to face the first intermediate layer pattern and the second intermediate layer pattern, and that has a region other than vias that do not include a via set to a ground potential as a ground layer.
semiconductor device according to claim 9,
wherein the intermediate layer pattern includes a first intermediate layer pattern and a second intermediate layer pattern that are arranged to face each other, and a third intermediate layer pattern that is arranged between the first intermediate layer pattern and the second intermediate layer pattern in such a manner as to face the first intermediate layer pattern and the second intermediate layer pattern and has a region other than a via excluding a via set to a ground potential as a ground layer.
Instant Application Claim 10
Modified Copending Claim 11
semiconductor device according to claim 1,
wherein the first semiconductor element is a semiconductor element having a high output amplification function, the second semiconductor element is a semiconductor element having a power supply control function, and the third back-side pad of the third substrate is formed on a back surface of a single-layer insulating substrate, and the third front-side pad of the third substrate is formed on a front surface of the single-layer insulating substrate.
semiconductor device according to claim 1,
wherein the first semiconductor element is a semiconductor element having a high output amplification function, the second semiconductor element is a semiconductor element having a power supply control function, and the third back side pad of the third substrate is formed on a back surface of a single-layer insulating substrate, and the third front side pad of the third substrate is formed on a front surface of the single-layer insulating substrate.
Instant Application Claim 11
Modified Copending Claim 12
semiconductor device according to claim 1,
wherein the first semiconductor element is a semiconductor element having a high output amplification function, two output terminals, and a characteristic impedance of a 100 Ω system, an output synthesis circuit including a first transmission line and a second transmission line connected in series between an output node and one of the output terminals of the first semiconductor element, and a third transmission line connected between the output node and the other of the output terminals of the first semiconductor element is formed in the first wiring pattern layer in the first substrate, and a characteristic impedance of each of the first transmission line, the second transmission line, and the third transmission line is 100 Ω, and an electrical length of each of the first transmission line, the second transmission line, and the third transmission line is 50 degrees to 90 degrees.
semiconductor device according to claim 1,
wherein the first semiconductor element is a semiconductor element having a high output amplification function, two output terminals, and a characteristic impedance of a 100 Ω system, and an output combining circuit including a first transmission line and a second transmission line connected in series between an output branch point and a first output terminal of the first semiconductor element, and a third transmission line connected between the output branch point and a second output terminal of the first semiconductor element is formed in the first wiring pattern layer in the first substrate, and characteristic impedances of the first transmission line, the second transmission line, and the third transmission line are 100 Ω, and electrical lengths of the first transmission line, the second transmission line, and the third transmission line are 50 degrees to 90 degrees.
Instant Application Claim 12
Modified Copending Claim 14
semiconductor device according to claim 1,
wherein the second semiconductor element is a semiconductor element having a power supply control function.
semiconductor device according to claim 1,
wherein the second semiconductor element is a semiconductor element having a power supply control function.
Instant Application Claim 13
Modified Copending Claim 15
semiconductor device according to claim 12,
further comprising a third semiconductor element having a driver amplification function, the third semiconductor element being mounted and fixed on the front surface of the second base portion of the second substrate via the second heat sink in the second opening of the second substrate, and electrically connected to the line constituting the second wiring pattern layer of the second substrate.
semiconductor device according to claim 14,
further comprising a third semiconductor element having a driver amplification function, the third semiconductor element being mounted and fixed on the front surface of the second ground conductor of the second substrate via a second heat sink in the second opening of the second substrate, and electrically connected to the line constituting the second wiring pattern layer of the second substrate.
Regarding Claim 14, the initially modified Copending teaches the limitations of Claim 11 upon which it depends, but does not additionally include:
a heat radiator mounted on a back surface of the first base portion in the first substrate.
Meliane teaches a semiconductor device ((106A); Fig. 4, Paragraph [0050]), comprising:
a heat radiator ((112); Fig. 4, Paragraph [0050]) mounted on a back surface of the first base portion (e.g. (100) and (98); Fig. 4, Paragraph [0045]) in the first substrate ((12); Fig. 4, Paragraph [0030]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the further teachings of Meliane into the claimed device of Copending such that a heat radiator mounted on a back surface of the first base portion in the first substrate. This would be due to the fact that doing so would improve thermal management by irradiating heat generated by the semiconductor devices (Melaine, Paragraph [0050]).
Instant Application Claim 15
Modified Copending Claim 6
semiconductor device according to claim 1,
wherein the first semiconductor element is a semiconductor element having a high output amplification function, the second semiconductor element is a semiconductor element having a power supply control function, the plurality of first front-side pads on the first substrate is arranged around the first insulating substrate in such a manner as to surround the first wiring pattern, at least one of the plurality of second front-side pads on the second substrate is arranged in a central portion of the front surface of the second insulating substrate, and the remaining second front-side pads are arranged around the second insulating substrate in such a manner as to surround the second wiring pattern.
semiconductor device according to claim 1,
wherein the first semiconductor element is a semiconductor element having a high output amplification function, the second semiconductor element is a semiconductor element having a power supply control function, the plurality of first front side pads on the first substrate is arranged around the first dielectric substrate in such a manner as to surround the first wiring pattern, and at least one of the plurality of second front side pads on the second substrate is arranged in a central portion of the front surface of the second dielectric substrate, and a rest of the second front side pads is arranged around the second dielectric substrate in such a manner as to surround the second wiring pattern.
This is a provisional nonstatutory double patenting rejection.
Claim Rejections - 35 USC § 112(b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding Claim 1,
-The term “thick” as it relates to the copper of the first and second base portions is a relative term which renders the claim indefinite. The term “thick” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. This is especially important in the field of semiconductors wherein thickness scales are important for device functionality. For the purpose of this Office Action, Examiner will read this limitation as simply referencing a non 2-dimensional thickness.
-The limitations “a line constituting the first wiring pattern layer” and “a line constituting the second wiring pattern layer” are unclear as to the intention of structure of the claim. Without a definition given, the term “constituting” is read in the general sense, which is a closed definition (i.e. the first/second wiring pattern layers only contain a line each, see Merriam-Webster; transitive verb, (1)). These limitations also are unclear if “a line” is a shared element between the two pattern layers or if different elements are intended.
-The limitations “each of the third back-side pads being connected to a corresponding one of the plurality of first front-side pads of the first substrate by a connection member” and “each of the third front-side pads being connected to each of the plurality of second front-side pads of the second substrate by a connection member.” are unclear as to the intention of the structure of the claim. In intended difference of “connected to a corresponding one of the plurality” and “being connected to each of the plurality” is uncertain, and the second limitation in particular may be understood as each of the third front-side pads being connected to every individual second front-side pad of the plurality. Furthermore, these limitations also are unclear if “a connection” is a shared element or if different elements are intended.
For the purpose of this Office Action, the Examiner will read the Claim 1 as follows:
A semiconductor device comprising:
a first substrate including a first insulating substrate, a first wiring pattern layer comprising a first line, non-2D copper and formed on a back surface of the first insulating substrate, wherein a first opening reaching a front surface of the first base portion from the front surface is formed in the first insulating substrate;
a first semiconductor element mounted and fixed on the front surface of the first base portion of the first substrate via a first heat sink in the first opening of the first substrate, and electrically connected to the first line
a second substrate including a second insulating substrate, a second wiring pattern layer comprising a second line, non-2D copper and formed on a back surface of the second insulating substrate, wherein a second opening reaching a front surface of the second base portion from the front surface is formed in the second insulating substrate;
a second semiconductor element mounted and fixed on the front surface of the second base portion of the second substrate via a second heat sink in the second opening of the second substrate, and electrically connected to the second line
a third substrate arranged between the first substrate and the second substrate in such a manner as to face the first substrate and the second substrate, the third substrate including a plurality of third back-side pads on a back surface of the third substrate, each of the third back-side pads being connected to a corresponding one of the plurality of first front-side pads of the first substrate by a first connection member, and a plurality of third front-side pads on a front surface of the third substrate, each of the third front-side pads being connected to a corresponding one of the plurality of second front-side pads of the second substrate by a second connection member.
Regarding Claim 2, the claim is rejected based on its dependence on Claim 1, in addition:
-The limitations “constituted by a same material and have a same thickness” are unclear as to the intention of structure of the claim. Without a definition given, the term “constituting” is read in the general sense, which is a closed definition (as given above in Claim 1). Furthermore, these limitations are unclear if “a same material” and “a same thickness” are shared between the different pairs of elements or if they are intended to be specific to each pairing.
For the purpose of this Office Action, the Examiner will read the body of Claim 2 as follows:
the first insulating substrate in the first substrate and the second insulating substrate in the second substrate comprise a same insulating material and have a same substrate thickness,
the first wiring pattern layer in the first substrate and the second wiring pattern layer in the second substrate comprise a same wiring material and have a same wiring thickness, and
the first base portion in the first substrate and the second base portion in the second substrate comprise a same base material and have a same base thickness.
Regarding Claim 3, the claim is rejected based on its dependence on Claim 1, in addition:
-The limitation “the front surface and the back surface” is unclear as to what elements are being referenced. Based on the previously established elements, it is understood by the Examiner the intention are as follows.
For the purpose of this Office Action, the Examiner will read the body of Claim 3 as follows:
the third substrate has a ground layer that is a solid pattern on each of the front surface of the third substrate and the back surface of the third substrate.
Regarding Claim 4, the claim is rejected based on its dependence on Claim 1.
Regarding Claim 5, the claim is rejected based on its dependence on Claim 1.
Following the changes of Claim 1, the limitation “to the line constituting the second wiring pattern layer of the second substrate” will be read as “to the second line”
Regarding Claim 6, the claim is rejected based on its dependence on Claim 1, in addition:
The limitation “at least one of the plurality of second front-side pads formed on the front surface of the second insulating substrate” and “a front-side pad arranged in a central portion of the second substrate and a front-side pad arranged at a side portion of the second substrate.” are unclear as to the intention of structure of the claim. In particular the relationship of “at least of of the plurality of second front-side pads” and “a front side pad” in addition to which “a front-side pad is being reference”.
For the purpose of this Office Action, the Examiner will read the above cited limitations of Claim 6 as follows:
“at least one of the plurality of second front-side pads formed on the front surface of the second insulating substrate” will be read as --at least one of the plurality of second front-side pads-- and “a front-side pad arranged in a central portion of the second substrate and a front-side pad arranged at a side portion of the second substrate.” will be read as –the at least one of the plurality of second front-side pads arranged in the central portion and a front-side pad of the plurality of second front-side pads arranged at a side portion of the second substrate--
Regarding Claims 7, the claim is rejected based on its dependence on Claim 1 and Claim 6.
Regarding Claim 8, the claim is rejected based on its dependence on Claim 1, in addition:
-The limitations “on the front surface having the third front-side pads” and “on a back surface having the third back-side pads” unclear as to what elements are being referenced, particularly due to continued changing of how elements are referenced and the fact “a back surface” is seemingly establishing a new surface. Furthermore, “the third front-side pad” and “the third back-side pad” lack antecedent basis. Based on the previously established elements, it is understood by the Examiner the intention are as follows.
For the purpose of this Office Action, the Examiner will read the body of Claim 8 as follows:
the third substrate has an intermediate layer pattern between an uppermost layer pattern located on the front surface of the third substrate the back surface of the third substrate
the intermediate layer pattern includes a wiring path for electrically connecting a third front-side pad of the plurality of third front-side pads and a third back-side pad of the plurality of third back-side pads corresponding to the third front-side pad.
Regarding Claim 9, the claim is rejected based on its dependence on Claim 1 and Claim 8, in addition:
-The limitation “and that has a region other than vias that do not include a via set to a ground potential as a ground layer” is unclear as to the intention of structure of the claim. Both “a region other than vias that do not include a via” and “set to a ground potential as a ground layer” are repetitive in nature and obfuscate intention.
For the purpose of this Office Action, the Examiner will read the above cited limitation of Claim 9 as follows:
--and wherein the third intermediate layer pattern includes a region set to a ground potential and does not include vias--
Regarding Claim 10, the claim is rejected based on its dependence on Claim 1, in addition:
-The limitations “the third back-side pad of the third substrate” and “the third front-side pad of the third substrate” lack antecedent basis and are unclear as to what elements are being referenced, particularly due to continued changing of how elements are referenced.
For the purpose of this Office Action, the Examiner will read the above cited limitations of Claim 10 as follows:
--a third back-side pad of the plurality of third back-side pads-- and --a third front-side pad of the plurality of third front-side pads--
Regarding Claims 11 and 12, the claims are rejected based on their dependence on Claim 1.
Regarding Claim 13, the claim is rejected based on its dependence on Claim 1.
Following the changes of Claim 1, the limitation “to the line constituting the second wiring pattern layer of the second substrate” will be read as “to the second line”
Regarding Claims 14 and 15, the claims are rejected based on their dependence on Claim 1.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Meliane et al. (U.S. Pub. 2018/0061725), hereinafter Meliane.
Regarding Claim 1, Meliane teaches a semiconductor device ((106A); Fig. 4, Paragraph [0050]), comprising:
a first substrate ((12); Fig. 4, Paragraph [0030]) including a first insulating substrate ((18); Fig. 4, Paragraph [0030]), a first wiring pattern layer comprising a first line ((20(B)); Fig. 4, Paragraph [0030]), a plurality of first front-side pads (comprising (20(A)) and (20(C), hereinafter (FFP)); Fig. 4, Paragraph [0030]) formed on a first front surface of the first insulating substrate (e.g. top surface of (18) in Fig. 4), and a first base portion ((110); Fig. 4, Paragraph [0049]) constituted by non-2D copper (similarly to elements (100) and (98); Paragraph [0045]) and formed on a back surface of the first insulating substrate (18), wherein a first opening (filled with (22)) reaching a front surface of the first base portion (e.g. top surface of (110) in Fig. 4) from the front surface is formed in the first insulating substrate (18);
a first semiconductor element ((44); Fig. 4, Paragraph [0034]) mounted and fixed on the front surface of the first base portion (110) of the first substrate via a first heat sink ((22); Fig. 4, Paragraph [0030]) in the first opening of the first substrate, and electrically connected to the first line ((20(B)) via (56); Fig. 4, Paragraph [0035]);
a second substrate ((14); Fig. 4, Paragraph [0030]) including a second insulating substrate ((28); Fig. 4, Paragraph [0032]), a second wiring pattern layer comprising a second line ((36(B)); Fig. 4, Paragraph [0032]) and a plurality of second front-side pads (comprising (36(A)) and (36(C), hereinafter (SFP)); Fig. 4, Paragraph [0032]) formed on a front surface of the second insulating substrate (e.g. bottom surface of (28) in Fig. 4), and a second base portion constituted by non-2D copper ((100) and (98); Fig. 4, Paragraph [0045]) and formed on a back surface of the second insulating substrate (28), wherein a second opening (e.g. opening for (34)) reaching a front surface of the second base portion (e.g. bottom surface of (100) in Fig. 4) from the front surface is formed in the second insulating substrate (28);
a second semiconductor element ((48); Fig. 4, Paragraph [0034]) mounted and fixed on the front surface of the second base portion (e.g. (100) out of (98) and (100)) of the second substrate via a second heat sink (comprising (34) and (32), specifically portion (34); Fig. 4, Paragraph [0032]) in the second opening of the second substrate (28), and electrically connected to the second line ((36(B)) via (70); Fig. 4, Paragraph [0037]); and
a third substrate ((16); Fig. 4, Paragraph [0030]) arranged between the first substrate (12) and the second substrate (14) in such a manner as to face the first substrate and the second substrate (e.g. as in Fig. 4, facing upwards and downwards), the third substrate including a plurality of third back-side pads (e.g. bottom sections of (40) and (42) not laterally between portions (16), hereinafter (TBP); Fig. 4, Paragraph [0033]) on a back surface of the third substrate (e.g. bottom of (18); Fig. 4), each of the third back-side pads (TBP) being connected to a corresponding one of the plurality of first front-side pads (FFP) of the first substrate (12) by a first connection member (e.g. bottom (82); Fig. 4, Paragraph [0041]), and a plurality of third front-side pads (e.g. top sections of (40) and (42) not laterally between portions (16), hereinafter (TFP); Fig. 4) on a front surface of the third substrate (16), each of the third front-side pads (TFP) being connected to a corresponding one of the plurality of second front-side pads (SFP) of the second substrate (14) by a second connection member (e.g. top (82); Fig. 4).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Meliane.
Regarding Claim 2, Meliane teaches the semiconductor device ((106A); Fig. 4, Paragraph [0050]), of Claim 1, wherein:
-the first insulating substrate (18) and the second insulating substrate (28) are both end layers (bottom/top) of a multi-layer substrate (Paragraphs [0030] and [0032]) that necessarily must be insulating for device functionality.
-the first wiring pattern layer (20(B)) in the first substrate and the second wiring pattern layer (36(B)) in the second substrate comprise a same wiring material (e.g. ‘metal’; Paragraphs [0030] and [0032])
- the first base portion (110) in the first substrate and the second base portion ((98) and (100)) in the second substrate comprise a same base material (‘non-2D Copper’)
Meliane further suggests based on the disclosed Figures and methodology (e.g. embodiment Fig. 4 and method Fig. 5A, Paragraph [0052]), but does not explicitly state:
- the first insulating substrate in the first substrate and the second insulating substrate in the second substrate have a same substrate thickness.
-the first wiring pattern layer in the first substrate and the second wiring pattern layer in the second substrate have a same wiring thickness.
- the first base portion in the first substrate and the second base portion in the second substrate have a same base thickness.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Melaine to ensure that the first insulating substrate in the first substrate and the second insulating substrate in the second substrate comprise a same insulating material and have a same substrate thickness; the first wiring pattern layer in the first substrate and the second wiring pattern layer in the second substrate have a same wiring thickness; the first base portion in the first substrate and the second base portion in the second substrate have a same base thickness. This would be due to the fact that doing so would produce the predictable result of simplifying manufacturing and improving efficiency by using repeated material process steps.
Claims 3 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Meliane in view of Omae et al. (U.S. Pub. 2021/0168950), hereinafter Omae.
Regarding Claim 3, Meliane teaches the semiconductor device ((106A); Fig. 4, Paragraph [0050]), of Claim 1 upon which it depends but does not explicitly disclose:
-the third substrate has a ground layer that is a solid pattern on each of the front surface of the third substrate and the back surface of the third substrate.
Omae teaches an intermediary substrate ((100); Figs. 4A-4C, Paragraph [0028]) connecting first and second elements ((200) and (300), respectively; Fig. 4B, paragraph [0027]) comprising:
- a ground layer ((102); Figs. 4A and 4B, Paragraph [0028]) that is a solid pattern (e.g. not fixed liquid) on each of the front surface of the intermediary substrate (e.g. top of (100); Fig. 4B) and the back surface of the intermediary substrate (e.g. bottom of (100); Fig. 4B)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Omae into the device of Meliane such that the third substrate has a ground layer that is a solid pattern on each of the front surface of the third substrate and the back surface of the third substrate. This would be due to the fact that doing so would reduce current leakage and noise (Omae, Paragraphs [0041] and [0042]).
Regarding Claim 8, Meliane teaches the semiconductor device ((106A); Fig. 4, Paragraph [0050]), of Claim 1 comprising:
-a intermediate layer pattern (comprising (40) and (42) laterally between (16), hereinafter (ILP); Fig. 4, Paragraph [0033]) includes a wiring path (e.g. (ILP) on the right; Fig. 4) for electrically connecting a third front-side pad (e.g. (TFP) on the right; Fig. 4) of the plurality of third front-side pads (TFP) and a third back-side pad (e.g. (TBP) on the right; Fig. 4) of the plurality of third back-side pads (TBP) corresponding to the third front-side pad.
Meliane does not explicitly teach:
-the third substrate has an intermediate layer pattern between an uppermost layer pattern located on the front surface of the third substrate and a lowermost layer pattern located on the back surface of the third substrate.
Omae teaches an intermediary substrate ((100); Figs. 4A-4C, Paragraph [0028]) connecting first and second elements ((200) and (300), respectively; Fig. 4B, paragraph [0027]) comprising:
-the intermediary substrate (100) has an intermediate layer pattern (comprising (103) and (104); Fig. 4C, Paragraph [0037]) between an uppermost layer pattern (e.g. top (101); Fig. 4B, Paragraph [0028]) located on the front surface of the intermediary substrate (e.g. top of (100); Fig. 4B) and a lowermost layer pattern (e.g. bottom (101); Fig. 4B) located on the back surface of the intermediary substrate (e.g. bottom of (100); Fig. 4B).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Omae into the device of Meliane such that the third substrate has an intermediate layer pattern between an uppermost layer pattern located on the front surface of the third substrate and a lowermost layer pattern located on the back surface of the third substrate. This would be due to the fact that doing so would reduce current leakage and noise (Omae, Paragraphs [0041] and [0042]).
Claims 4-7, 10, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Meliane in view of Shinozaki (U.S. Pub. 2022/0190849), hereinafter Shinozaki.
Regarding Claim 4, Meliane teaches the semiconductor device ((106A); Fig. 4, Paragraph [0050]), of Claim 1, wherein:
-the third substrate (16) is a substrate that relays electrical connection (e.g. with (40) and (42), Paragraph [0033]) between the first substrate (12) and the second substrate (14).
Meliane further teaches:
-the field of endeavor of the disclosure is high frequency devices (Paragraph [0003] and [0005])
Meliane does not explicitly state:
-the first semiconductor element is a semiconductor element having a high output amplification function,
-the second semiconductor element is a semiconductor element having a power supply control function
Shinozaki teaches a high frequency device ((1); Figs. 1-4, Paragraph [0026]) including
-the first semiconductor element is a semiconductor element having a high output amplification function ((112); Figs. 3 and 4, Paragraph [0032]),
-the second semiconductor element is a semiconductor element having a power supply control function (‘control circuit’, Paragraph [0035])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Shinozaki into the device of Meliane the first semiconductor element is a semiconductor element having a high output amplification function and the second semiconductor element is a semiconductor element having a power supply control function. This would be due to the fact that doing so would produce the predictable result of incorporating electronic elements to form a functioning high frequency device (Shinozaki, Paragraph [0027]).
Regarding Claim 5, Meliane as initially modified by Shinozaki teaches the semiconductor device ((106A); Fig. 4, Paragraph [0050]), of Claim 4, wherein:
-a third semiconductor element (Meliane, (50); Fig. 4, Paragraph [0034]) being mounted and fixed on the front surface of the second base portion (Meliane, portion (98)) of the second substrate (Meliane, (14)) via the second heat sink (Meliane, portion (32)) in the second opening of the second substrate, and electrically connected to the second line (Meliane, (36(B)) via (78); Fig. 4, Paragraph [0038])
Shinozaki further teaches:
-a third semiconductor element having a driver amplification function ((111); Figs. 3 and 4, Paragraph [0032])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the further teachings of Shinozaki into the device of Meliane as initially modified by Shinozaki such that it includes a third semiconductor element having a driver amplification function. This would be due to the fact that doing so would produce the predictable result of incorporating electronic elements to form a functioning high frequency device (Shinozaki, Paragraph [0027]).
Regarding Claim 6, Meliane teaches the semiconductor device ((106A); Fig. 4, Paragraph [0050]), of Claim 1, wherein:
at least one of the plurality of second front-side pads (e.g. left (SFP), pad (36(A)) is arranged in a central portion (e.g. broadly as any area slightly beyond the side) of the front surface of the second insulating substrate (28), and the third substrate is a substrate that relays electrical connection (See note below) between the at least one of the plurality of second front-side pads arranged in the central portion (36(A)) and a front-side pad of the plurality of second front-side pads (e.g. right (SFP), pad (36(C)) arranged at a side portion (e.g. broadly as any area at the side) of the second substrate.
Note: without any limiting definition to “relays electrical connection” Examiner will interpret the electrical connection as cumulative. Thus, (36(A)) connects to (40) which connects to (20(A)) which connects to (60) which connects to (20(B)) which connects to (44) which connects to (20(C)) which connects to (42) which connects to (36(C)). Thus the limitation is fulfilled.
Meliane further teaches:
-the field of endeavor of the disclosure is high frequency devices (Paragraph [0003] and [0005])
Meliane does not explicitly state:
-the first semiconductor element is a semiconductor element having a high output amplification function,
-the second semiconductor element is a semiconductor element having a power supply control function
Shinozaki teaches a high frequency device ((1); Figs. 1-4, Paragraph [0026]) including
-the first semiconductor element is a semiconductor element having a high output amplification function ((112); Figs. 3 and 4, Paragraph [0032]),
-the second semiconductor element is a semiconductor element having a power supply control function (‘control circuit’, Paragraph [0035])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Shinozaki into the device of Meliane the first semiconductor element is a semiconductor element having a high output amplification function and the second semiconductor element is a semiconductor element having a power supply control function. This would be due to the fact that doing so would produce the predictable result of incorporating electronic elements to form a functioning high frequency device (Shinozaki, Paragraph [0027]).
Regarding Claim 7, Meliane as modified by Shinozaki teaches the semiconductor device ((106A); Fig. 4, Paragraph [0050]), of Claim 6, but does not embody:
-a heat radiator mounted on a back surface of the first base portion in the first substrate.
Meliane further teaches a heat radiator ((112); Fig. 4, Paragraph [0049]) mounted on a back surface of a base portion ((98); Fig. 4, Paragraph [0045])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the further teachings of Meliane into the chosen embodiment of Meliane as modified by Shinozaki such that it further comprises a heat radiator mounted on a back surface of the first base portion in the first substrate. This would be due to the fact that doing so would improve thermal management of the first semiconductor device (Meliane, Paragraph [0049]).
Regarding Claim 10, Meliane teaches the semiconductor device ((106A); Fig. 4, Paragraph [0050]), of Claim 1, wherein:
- a third back-side pad of the plurality of third back-side pads (e.g. right (TBS)) is formed on a back surface of a single-layer insulating substrate ((16) is defined as consisting as a single layer ‘perimeter wall’ when excluding vias, which necessarily is insulating to have a functional device; Paragraph [0033], hereinafter main (16)) and a third front-side pad of the plurality of third front-side pads (e.g. right (TFP); Fig. 4) is formed on a front surface of the single-layer insulating substrate (main (16)).
Meliane further teaches:
-the field of endeavor of the disclosure is high frequency devices (Paragraph [0003] and [0005])
Meliane does not explicitly state:
-the first semiconductor element is a semiconductor element having a high output amplification function,
-the second semiconductor element is a semiconductor element having a power supply control function
Shinozaki teaches a high frequency device ((1); Figs. 1-4, Paragraph [0026]) including
-the first semiconductor element is a semiconductor element having a high output amplification function ((112); Figs. 3 and 4, Paragraph [0032]),
-the second semiconductor element is a semiconductor element having a power supply control function (‘control circuit’, Paragraph [0035])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Shinozaki into the device of Meliane the first semiconductor element is a semiconductor element having a high output amplification function and the second semiconductor element is a semiconductor element having a power supply control function. This would be due to the fact that doing so would produce the predictable result of incorporating electronic elements to form a functioning high frequency device (Shinozaki, Paragraph [0027]).
Regarding Claim 15, Meliane teaches the semiconductor device ((106A); Fig. 4, Paragraph [0050]), of Claim 1, wherein:
-the plurality of first front-side pads (FFP) on the first substrate (12) is arranged around the first insulating substrate (18) in such a manner as to surround (e.g. laterally; Fig. 4) the first wiring pattern (20(B)), at least one of the plurality of second front-side pads (e.g. right (SFP), (36(C)) on the second substrate (14) is arranged in a central portion (e.g. broadly as any area slightly beyond the side) of the front surface of the second insulating substrate (28), and the remaining second front-side pads (no explicit limitation preventing inclusion of all second front-side pads as being part of “the remaining”) are arranged around the second insulating substrate (28) in such a manner as to surround the second wiring pattern (36(B)).
Meliane further teaches:
-the field of endeavor of the disclosure is high frequency devices (Paragraph [0003] and [0005])
Meliane does not explicitly state:
-the first semiconductor element is a semiconductor element having a high output amplification function,
-the second semiconductor element is a semiconductor element having a power supply control function
Shinozaki teaches a high frequency device ((1); Figs. 1-4, Paragraph [0026]) including
-the first semiconductor element is a semiconductor element having a high output amplification function ((112); Figs. 3 and 4, Paragraph [0032]),
-the second semiconductor element is a semiconductor element having a power supply control function (‘control circuit’, Paragraph [0035])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Shinozaki into the device of Meliane the first semiconductor element is a semiconductor element having a high output amplification function and the second semiconductor element is a semiconductor element having a power supply control function. This would be due to the fact that doing so would produce the predictable result of incorporating electronic elements to form a functioning high frequency device (Shinozaki, Paragraph [0027]).
Claims 11 is rejected under 35 U.S.C. 103 as being unpatentable over Meliane in view of Torii et al. (WO 2021/220338), hereinafter Torii, in further view of Jiang et al. (U.S. Pub. 2017/0084553), hereinafter Jiang. The english publication of Torii (U.S. Pub. 2022/0407468) is utilized in this rejection for translational purposes only, with all matter considered disclosed in the WIPO publication.
Regarding Claim 11, Meliane teaches the semiconductor device ((106A); Fig. 4, Paragraph [0050]), of Claim 1 upon which it depends, but does not explicitly disclose:
-the first semiconductor element is a semiconductor element having a high output amplification function, two output terminals, and a characteristic impedance of a 100 Ω system,
-an output synthesis circuit including a first transmission line and a second transmission line connected in series between an output node and one of the output terminals of the first semiconductor element, and a third transmission line connected between the output node and the other of the output terminals of the first semiconductor element is formed in the first wiring pattern layer in the first substrate, and
-a characteristic impedance of each of the first transmission line, the second transmission line, and the third transmission line is 100 Ω, and an electrical length of each of the first transmission line, the second transmission line, and the third transmission line is 50 degrees to 90 degrees.
Torii teaches a semiconductor element ((1) including the output synthesis circuit; Fig. 1, Paragraph [0024]) comprising:
-a high output amplification function (Paragraphs [0003] and [0009]), two output terminals (as part of (2); Fig. 1, Paragraph [0025]), and a characteristic impedance of the system (Paragraph [0009]),
-an output synthesis circuit (1) (See Paragraphs [0004] and [0005]) including a first transmission line ((7); Fig. 1, Paragraph [0024]) and a second transmission line ((3); Fig. 1, Paragraph [0026]) connected in series between an output node ((9); Fig. 1, Paragraph [0024]) and one of the output terminals of the first semiconductor element (e.g. top output of (2); Fig. 1), and a third transmission line ((8); Fig. 1, Paragraph [0028]) connected between the output node (9) and the other of the output terminals (e.g. bottom output of (2); Fig. 1), and
and an electrical length of each of the first transmission line (e.g. 70 degrees, Paragraph [0040]), the second transmission line (e.g. 70 degrees, See Note), and the third transmission line (e.g. 90 degrees, Paragraph [0040]) is 50 degrees to 90 degrees.
Note: The second transmission line’s electrical length (θa) and the electrical length of (4) (θb = electrical length of (8) minus electrical length of (7)) added together equals the phase difference (Paragraphs [0026] and [0036]; Fig. 1)
This phase difference is given as e.g. 90 degrees (Paragraph [0074])
Thus, 90 – (90 – 70)) = 70 -> The second transmission line’s electrical length is 50 degrees to 90 degrees, the limitation is fulfilled.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Torri into the device of Meliane such that -the first semiconductor element is a semiconductor element having a high output amplification function, two output terminals, and includes a characteristic impedance, an output synthesis circuit including a first transmission line and a second transmission line connected in series between an output node and one of the output terminals of the first semiconductor element, and a third transmission line connected between the output node and the other of the output terminals of the first semiconductor element is formed in the first wiring pattern layer in the first substrate, and an electrical length of each of the first transmission line, the second transmission line, and the third transmission line is 50 degrees to 90 degrees. Futhermore, the incorporation would be done such that and the other of the output terminals of the first semiconductor element is formed in the first wiring pattern layer in the first substrate, for the sake of functionality between different elements. This would be due to the fact that doing so would incorporate an amplifier device with high efficiency (Torii, Paragraph [0010]).
Neither Meliane nor Torii explicitly state:
-a characteristic impedance of a 100 Ω system
-a characteristic impedance of each of the first transmission line, the second transmission line, and the third transmission line is 100 Ω,
Jiang teaches a semiconductor device ((100); Fig. 1, Paragraph [0015]) wherein:
-a characteristic impedance of a transmission line is 100 Ω ((111); Fig. 1, Paragraph [0022])
Further wherein the disclosure relates that electronic elements may have a characteristic impendence of 100 Ω when transmitting differential signals (Paragraph [0026])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Jiang into the device of Meliane as modified by Torii such that the first semiconductor element has a characteristic impedance of a 100 Ω system and a characteristic impedance of each of the first transmission line, the second transmission line, and the third transmission line is 100 Ω,. This would be due to the fact that doing so would ensure proper impedance to transmit differential signals (Jian, Paragraph [0024]).
Claims 12-14 are rejected under 35 U.S.C. 103 as being unpatentable over Meliane, Torii, and Jiang in view of Shinozaki.
Regarding Claim 12, Meliane, Torii, and Jiang teach the semiconductor device ((106A); Fig. 4, Paragraph [0050]), of Claim 11, upon which it depends, and further teaches:
-the field of endeavor of the disclosure is high frequency devices (Meliane, Paragraphs [0003] and [0005])
but does not explicitly teach:
-the second semiconductor element is a semiconductor element having a power supply control function.
Shinozaki teaches a high frequency device ((1); Figs. 1-4, Paragraph [0026]) including
-the second semiconductor element is a semiconductor element having a power supply control function (‘control circuit’, Paragraph [0035])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Shinozaki into the device of Meliane, Torii, and Jiang such that the second semiconductor element is a semiconductor element having a power supply control function. This would be due to the fact that doing so would produce the predictable result of incorporating electronic elements to form a functioning high frequency device (Shinozaki, Paragraph [0027]).
Regarding Claim 13, Meliane, Torii, and Jiang as initially modified by teach the semiconductor device ((106A); Fig. 4, Paragraph [0050]), of Claim 12, upon which it depends, wherein:
-a third semiconductor element (Meliane, (50); Fig. 4, Paragraph [0034]) being mounted and fixed on the front surface of the second base portion (Meliane, portion (98)) of the second substrate (Meliane, (14)) via the second heat sink (Meliane, portion (32)) in the second opening of the second substrate, and electrically connected to the second line (Meliane, (36(B)) via (78); Fig. 4, Paragraph [0038])
Shinozaki further teaches:
-a third semiconductor element having a driver amplification function ((111); Figs. 3 and 4, Paragraph [0032])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the further teachings of Shinozaki into the device of Meliane as initially modified by Shinozaki such that it includes a third semiconductor element having a driver amplification function. This would be due to the fact that doing so would produce the predictable result of incorporating electronic elements to form a functioning high frequency device (Shinozaki, Paragraph [0027]).
Regarding Claim 14, Meliane, Torii, and Jiang as modified by Shinozaki teaches the semiconductor device ((106A); Fig. 4, Paragraph [0050]), of Claim 11, but does not embody:
-a heat radiator mounted on a back surface of the first base portion in the first substrate.
Meliane further teaches a heat radiator ((112); Fig. 4, Paragraph [0049]) mounted on a back surface of a base portion ((98); Fig. 4, Paragraph [0045])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the further teachings of Meliane into the chosen embodiment of Meliane as modified by Shinozaki such that it further comprises a heat radiator mounted on a back surface of the first base portion in the first substrate. This would be due to the fact that doing so would improve thermal management of the first semiconductor device (Meliane, Paragraph [0049]).
Allowable Subject Matter
Claim 9 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding Claim 9, the best prior art of record does not teach or fairly suggest, along with the other claimed features, which are necessary in establishing the structure, a semiconductor device comprising:
-and wherein the third intermediate layer pattern includes a region set to a ground potential and does not include vias.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DMITRI MIHALIOV whose telephone number is (571)270-5220. The examiner can normally be reached weekdays 7:30 - 17:30 US Eastern Time.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached at (571) 272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DMITRI MIHALIOV/ Examiner, Art Unit 2812
/DAVIENNE N MONBLEAU/ Supervisory Patent Examiner, Art Unit 2812
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