DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 11 is objected to because of the following informalities:
In claim 11 line 2, “a second passive component” ---, should be corrected to ---, “the second passive component” ---.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 1 is rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Shimamura et al (US Publication No. 20150016066).
Regarding claim 1, Shimamura discloses an electronic device (i.e., such as electronic device 100B; see for example fig. 10, para. [0120]- [0128]), comprising: a first circuit module (i.e., such as first circuit module 31, 32; see for example fig. 10, para. [0120]- [0128]); and a first shield (i.e., such as first shield 5B; see for example fig. 10, para. [0120]- [0128]) disposed at a lateral side (i.e., such as lateral side the left wall and the right wall of the shield 5B in the Y-axis; see for example fig. 10, para. [0120]- [0128]) of the first circuit module (i.e., such as first circuit module 31, 32; see for example fig. 10, para. [0120]- [0128]) and comprising a first opening (i.e., such as first opening 513B; see for example fig. 10, para. [0120]- [0128]) configured to reduce (i.e., such as configured to reduce as to prevent the capacitive coupling; for instance, according to this embodiment, it is also possible to prevent the parasitic capacitance (capacitive coupling) between the electronic component 31 and the conductive shield 5B from being generated. Moreover, it is possible to regulate the thickness of the entire circuit module 100B, and to reduce the circuit module 100B in size; see for example fig. 10, para. [0120]- [0128]) a parasitic coupling (i.e., such as parasitic coupling; for instance, according to this embodiment, it is also possible to prevent the parasitic capacitance (capacitive coupling) between the electronic component 31 and the conductive shield 5B from being generated. Moreover, it is possible to regulate the thickness of the entire circuit module 100B, and to reduce the circuit module 100B in size; see for example fig. 10, para. [0120]- [0128]) of the first circuit module (i.e., such as first circuit module 31, 32; see for example fig. 10, para. [0120]- [0128]) and the first shield (i.e., such as first shield 5B; see for example fig. 10, para. [0120]- [0128]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Shimamura et al (US Publication No. 20150016066) in view of Yazaki et al (US Publication No. 20190363055).
Regarding claim 2, Shimamura discloses the electronic device (i.e., such as electronic device 100B; see for example fig. 10, para. [0120]- [0128]); wherein the first circuit module (i.e., such as first circuit module 31, 32; see for example fig. 10, para. [0120]- [0128]) includes a capacitor (i.e., such as capacitor 31; see for example fig. 10, para. [0120]- [0128]), and the first opening (i.e., such as first opening 513B; see for example fig. 10, para. [0120]- [0128]) is configured to reduce (i.e., such as configured to reduce as to prevent the capacitive coupling; for instance, according to this embodiment, it is also possible to prevent the parasitic capacitance (capacitive coupling) between the electronic component 31 and the conductive shield 5B from being generated. Moreover, it is possible to regulate the thickness of the entire circuit module 100B, and to reduce the circuit module 100B in size; see for example fig. 10, para. [0120]- [0128]) a parasitic capacitance (i.e., such as parasitic capacitance; for instance, according to this embodiment, it is also possible to prevent the parasitic capacitance (capacitive coupling) between the electronic component 31 and the conductive shield 5B from being generated. Moreover, it is possible to regulate the thickness of the entire circuit module 100B, and to reduce the circuit module 100B in size; see for example fig. 10, para. [0120]- [0128]) between the capacitor (i.e., such as capacitor 31; see for example fig. 10, para. [0120]- [0128]) and the first shield (i.e., such as first shield 5B; see for example fig. 10, para. [0120]- [0128]).
Shimamura does not explicitly disclose a capacitor.
Yazaki discloses a shielded electronic component (i.e., see for example fig. 7, para. [0103]- [0112]); wherein a capacitor (i.e., such as capacitor 52; see for example fig. 7, para. [0103]- [0112]).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the capacitor device in Shimamura, as taught by Yazaki, as it provides the advantage of optimizing the circuit design.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Shimamura et al (US Publication No. 20150016066) in view of Suzuki et al (US Publication No. 20170295643).
Regarding claim 3, Shimamura discloses the electronic device (i.e., such as electronic device 100B; see for example fig. 10, para. [0120]- [0128]).
Shimamura does not explicitly disclose wherein the first circuit module is configured to clamp a voltage of the electronic device.
Suzuki discloses an electronic circuit module (i.e., see for example fig. 5, para. [0042]- [0050]); wherein the first circuit module (i.e., such as the first circuit module 32; see for example fig. 5, para. [0042]- [0050]) is configured to clamp (i.e., such as 32 is configured to clamp via land pattern 23; see for example fig. 5, para. [0042]- [0050]) a voltage (i.e., such as voltage of power supply pattern 24; see for example fig. 5, para. [0042]- [0050]) of the electronic device (i.e., such as the electronic device fig. 5; see for example fig. 5, para. [0042]- [0050]).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally clamped the power supply in Shimamura, as taught by Suzuki, as it provides the advantage of optimizing the circuit design.
Claims 4, 8-9 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Shimamura et al (US Publication No. 20150016066) in view of Miwa (US Publication No. 20170347462).
Regarding claim 4, Shimamura discloses the electronic device (i.e., such as electronic device 100B; see for example fig. 10, para. [0120]- [0128]).
Shimamura does not explicitly disclose further comprising a second circuit module and a second shield disposed at a lateral side of the second circuit module, wherein the second shield comprises a second opening configured to reduce a parasitic coupling of the second circuit module and the second shield.
Miwa discloses a shielded encapsulated circuit module (i.e., see for example fig. 8d, para. [0159]); wherein further comprising a second circuit module (i.e., such as second circuit module 200; see for example fig. 8d, para. [0159]) and a second shield (i.e., such as second shield 600; see for example fig. 8d, para. [0159]) disposed at a lateral side (i.e., such as lateral side 110X; see for example fig. 8d, para. [0159]) of the second circuit module (i.e., such as second circuit module 200; see for example fig. 8d, para. [0159]), wherein the second shield (i.e., such as second shield 600; see for example fig. 8d, para. [0159]) comprises a second opening (i.e., such as second opening 630; see for example fig. 8d, para. [0159]) configured to reduce (i.e., such as configured to reduce the interference/trapped waves/parasitic coupling; for instance, if the electronic component 200 is, for example, a transceiver, the electronic component 200 must communicate with an external electronic component using, for example, radio waves. In such a case, the shield layer 600 that cuts off the electromagnetic waves could interfere with the communication using radio waves. In consideration of this, an area without the shield layer 600 is provided as an opening of the shield layer 600 in an area required for such communication, e.g., directly above the electronic component 200 that performs communication. This allows the electronic component 200 in the encapsulated circuit module which performs communication to communicate while protecting other electronic component(s) by the shield layer 600; see for example fig. 8d, para. [0146]- [0159]) a parasitic coupling (i.e., such as parasitic coupling/interference/trapped waves; for instance, if the electronic component 200 is, for example, a transceiver, the electronic component 200 must communicate with an external electronic component using, for example, radio waves. In such a case, the shield layer 600 that cuts off the electromagnetic waves could interfere with the communication using radio waves. In consideration of this, an area without the shield layer 600 is provided as an opening of the shield layer 600 in an area required for such communication, e.g., directly above the electronic component 200 that performs communication. This allows the electronic component 200 in the encapsulated circuit module which performs communication to communicate while protecting other electronic component(s) by the shield layer 600; see for example fig. 8d, para. [0146]- [0159]) of the second circuit module (i.e., such as second circuit module 200; see for example fig. 8d, para. [0159]) and the second shield (i.e., such as second shield 600; see for example fig. 8d, para. [0159]).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the second circuit module in Shimamura, as taught by Miwa, as it provides the advantage of optimizing the circuit design.
Regarding claim 8, Shimamura in view Miwa and the teachings of Shimamura as modified by Miwa have been discussed above.
Shimamura further discloses the electronic device (i.e., such as electronic device 100B; see for example fig. 10, para. [0120]- [0128]); an electronic device (i.e., such as electronic device 100B; see for example fig. 10, para. [0120]- [0128]), comprising: a circuit module (i.e., such as circuit module 31, 32; see for example fig. 10, para. [0120]- [0128]) comprising a first passive component (i.e., such as first passive component 31; see for example fig. 10, para. [0120]- [0128]); and a shield (i.e., such as shield 5B; see for example fig. 10, para. [0120]- [0128]) disposed at a lateral side (i.e., such as lateral side the left wall and the right wall of the shield 5B in the Y-axis; see for example fig. 10, para. [0120]- [0128]) of the circuit module (i.e., such as circuit module 31, 32; see for example fig. 10, para. [0120]- [0128]) and comprising an opening (i.e., such as opening 513B; see for example fig. 10, para. [0120]- [0128]) faced toward (i.e., such as faced toward in the Z-axis; see for example fig. 10, para. [0120]- [0128]) the first passive component (i.e., such as first passive component 31; see for example fig. 10, para. [0120]- [0128]).
Miwa furthermore discloses the shielded encapsulated circuit module (i.e., see for example fig. 8d, para. [0159]); the first passive component (i.e., such as the first passive component 200; see for example fig. 8d, para. [0159]).
Regarding claim 9, Shimamura in view Miwa and the teachings of Shimamura as modified by Miwa have been discussed above.
Shimamura further discloses the electronic device (i.e., such as electronic device 100B; see for example fig. 10, para. [0120]- [0128]); wherein the circuit module (i.e., such as circuit module 31, 32; see for example fig. 10, para. [0120]- [0128]) further comprises a second passive component (i.e., such as second passive component 32; see for example fig. 10, para. [0120]- [0128]), and the first passive component (i.e., such as first passive component 31; see for example fig. 10, para. [0120]- [0128]) has a first volume (i.e., such as first volume of 31; see for example fig. 10, para. [0120]- [0128]) larger than (i.e., such as volume of 31 > volume of 32; see for example fig. 10, para. [0120]- [0128]) a second volume (i.e., such as second volume of 32; see for example fig. 10, para. [0120]- [0128]) of the second passive component (i.e., such as second passive component 32; see for example fig. 10, para. [0120]- [0128]).
Miwa furthermore discloses the shielded encapsulated circuit module (i.e., see for example fig. 8d, para. [0159]); the first passive component (i.e., such as the first passive component 200; see for example fig. 8d, para. [0159]) and the second passive component (i.e., such as the second passive component 200; see for example fig. 8d, para. [0159]).
Regarding claim 11, Shimamura in view Miwa and the teachings of Shimamura as modified by Miwa have been discussed above.
Shimamura further discloses the electronic device (i.e., such as electronic device 100B; see for example fig. 10, para. [0120]- [0128]); further comprising a carrier (i.e., such as carrier 2/25; see for example fig. 10, para. [0120]- [0128]) for supporting the circuit module (i.e., such as circuit module 31, 32; see for example fig. 10, para. [0120]- [0128]), wherein the circuit module (i.e., such as circuit module 31, 32; see for example fig. 10, para. [0120]- [0128]) further comprises a second passive component (i.e., such as second passive component 32; see for example fig. 10, para. [0120]- [0128]), and wherein the first passive component (i.e., such as first passive component 31; see for example fig. 10, para. [0120]- [0128]) is higher than (i.e., such as height of 31 > height of 32; see for example fig. 10, para. [0120]- [0128]) the second passive component (i.e., such as second passive component 32; see for example fig. 10, para. [0120]- [0128]) with respect to the carrier (i.e., such as carrier 2/25; see for example fig. 10, para. [0120]- [0128]).
Miwa furthermore discloses the shielded encapsulated circuit module (i.e., see for example fig. 8d, para. [0159]); the first passive component (i.e., such as the first passive component 200; see for example fig. 8d, para. [0159]) and the second passive component (i.e., such as the second passive component 200; see for example fig. 8d, para. [0159]).
Claims 5 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Shimamura et al (US Publication No. 20150016066) in view of Miwa (US Publication No. 20170347462) and further in view of Bolognia (US Publication No. 20140159226).
Regarding claim 5, Shimamura in view of Miwa and the teachings of Shimamura as modified by Miwa have been discussed above.
Neither Shimamura nor Miwa explicitly discloses further comprising a carrier for supporting the first circuit module and the second circuit module, wherein the first opening is substantially aligned with the second opening in a direction perpendicular to a long side of the carrier.
Bolognia discloses a compact sensor module (i.e., see for example fig. 3, para. [0029]- [0033]); wherein further comprising a carrier (i.e., such as carrier 18; see for example fig. 3, para. [0029]- [0033]) for supporting the first circuit module (i.e., such as the first circuit module 7; see for example fig. 3, para. [0029]- [0033]) and the second circuit module (i.e., such as the second circuit module 7; see for example fig. 3, para. [0029]- [0033]), wherein the first opening (i.e., such as the first opening 5; see for example fig. 3, para. [0029]- [0033]) is substantially aligned (i.e., such as 5 is substantially aligned between each 6; see for example fig. 3, para. [0029]- [0033]) with the second opening (i.e., such as the second opening 5; see for example fig. 3, para. [0029]- [0033]) in a direction (i.e., such as direction Z-axis/width of 18; see for example fig. 3, para. [0029]- [0033]) perpendicular to a long side (i.e., such as long side in X-axis/length of 18; see for example fig. 3, para. [0029]- [0033]) of the carrier (i.e., such as carrier 18; see for example fig. 3, para. [0029]- [0033]).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the carrier in Shimamura, as taught by Bolognia, as it provides the advantage of optimizing the circuit design.
Regarding claim 7, Shimamura in view of Miwa and further in view of Bolognia and the teachings of Shimamura as modified by Miwa have been discussed above. Also, the teachings of Shimamura as modified by Bolognia have been discussed above as well.
Bolognia further discloses the compact sensor module (i.e., see for example fig. 3, para. [0029]- [0033]); wherein the first shield (i.e., such as the first shield 6; see for example fig. 3, para. [0029]- [0033]) is spaced apart (i.e., such as each 6 is spaced apart via space 24; see for example fig. 3, para. [0029]- [0033]) from the second shield (i.e., such as the second shield 6; see for example fig. 3, para. [0029]- [0033]).
Claims 13-17 and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Shimamura et al (US Publication No. 20150016066) in view of Miwa (US Publication No. 20170347462) and further in view of Brewer et al (US Publication No. 20220140794).
Regarding claim 13, Shimamura in view Miwa and the teachings of Shimamura as modified by Miwa have been discussed above.
Neither Shimamura nor Miwa explicitly discloses wherein the opening overlaps a top surface and a lateral surface of the first passive component.
Brewer discloses an IC chip apparatus (i.e., see for example figs. 3C and 4, para. [0094]- [0110]); wherein the opening (i.e., such as the opening g; see for example figs. 3C and 4, para. [0094]- [0110]) overlaps (i.e., such as overlaps; see for example figs. 3C and 4, para. [0094]- [0110]) a top surface (i.e., such as top surface at numerals 272/275-1A/275-2; see for example figs. 3C and 4, para. [0094]- [0110]) and a lateral surface (i.e., such as lateral surface at numerals 275-1B/273-3; see for example figs. 3C and 4, para. [0094]- [0110]) of the first passive component (i.e., such as the first passive component Input Harmonic Termination elements; see for example figs. 3C and 4, para. [0094]- [0110]).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the opening overlap in Shimamura, as taught by Brewer, as it provides the advantage of optimizing the circuit design.
Regarding claim 14, Shimamura in view Miwa and further in view of Brewer and the teachings of Shimamura as modified by Miwa have been discussed above. Also, the teachings of Shimamura as modified by Brewer have been discussed above as well.
Brewer further discloses the IC chip apparatus (i.e., see for example figs. 3C and 4, para. [0094]- [0110]); wherein the circuit module (i.e., such as the circuit module 10; see for example figs. 3C and 4, para. [0094]- [0110]) further comprises an encapsulation layer (i.e., such as encapsulation layer 170; see for example figs. 3C and 4, para. [0094]- [0110]) encapsulating (i.e., such as encapsulating; see for example figs. 3C and 4, para. [0094]- [0110]) the first passive component (i.e., such as the first passive component Input Harmonic Termination elements; see for example figs. 3C and 4, para. [0094]- [0110]), wherein the encapsulation layer (i.e., such as encapsulation layer 170; see for example figs. 3C and 4, para. [0094]- [0110]) and the shield (i.e., such as the shield 175-1/175-2; see for example figs. 3C and 4, para. [0094]- [0110]) define the opening (i.e., such as the opening g; see for example figs. 3C and 4, para. [0094]- [0110]).
Regarding claim 15, Shimamura in view Miwa and further in view of Brewer and the teachings of Shimamura as modified by Miwa have been discussed above. Also, the teachings of Shimamura as modified by Brewer have been discussed above as well.
Brewer further discloses the IC chip apparatus (i.e., see for example figs. 3C and 4, para. [0094]- [0110]); wherein the encapsulation layer (i.e., such as encapsulation layer 170; see for example figs. 3C and 4, para. [0094]- [0110]) has a top surface (i.e., such as top surface at numeral 272; see for example figs. 3C and 4, para. [0094]- [0110]) and a lateral surface (i.e., such as lateral surface at numeral 273-3; see for example figs. 3C and 4, para. [0094]- [0110]), wherein the opening (i.e., such as the opening g; see for example figs. 3C and 4, para. [0094]- [0110]) exposes the top surface (i.e., such as top surface at numeral 272; see for example figs. 3C and 4, para. [0094]- [0110]) and the lateral surface (i.e., such as lateral surface at numeral 273-3; see for example figs. 3C and 4, para. [0094]- [0110]).
Regarding claim 16, Shimamura in view Miwa and further in view of Brewer and the teachings of Shimamura as modified by Miwa have been discussed above. Also, the teachings of Shimamura as modified by Brewer have been discussed above as well.
Brewer further discloses the IC chip apparatus (i.e., see for example figs. 3C and 4, para. [0094]- [0110]); wherein the circuit module (i.e., such as the circuit module 10; see for example figs. 3C and 4, para. [0094]- [0110]) further comprises a second passive component (i.e., such as second passive component Output Impedance Match elements; see for example figs. 3C and 4, para. [0094]- [0110]), wherein the second passive component (i.e., such as second passive component Output Impedance Match elements; see for example figs. 3C and 4, para. [0094]- [0110]) overlaps the opening (i.e., such as the opening g; see for example figs. 3C and 4, para. [0094]- [0110]).
Regarding claim 17, Shimamura in view Miwa and further in view of Brewer and the teachings of Shimamura as modified by Miwa have been discussed above. Also, the teachings of Shimamura as modified by Brewer have been discussed above as well.
Brewer further discloses the IC chip apparatus (i.e., see for example figs. 3C and 4, para. [0094]- [0110]); wherein the first passive component (i.e., such as the first passive component Input Harmonic Termination elements; see for example figs. 3C and 4, para. [0094]- [0110]) is configured to transmit (i.e., such as configured to transmit via 62; see for example figs. 3C and 4, para. [0094]- [0110]) a first signal (i.e., such as first signal RF In; see for example figs. 3C and 4, para. [0094]- [0110]) and the second passive component (i.e., such as second passive component Output Impedance Match elements; see for example figs. 3C and 4, para. [0094]- [0110]) is configured to transmit (i.e., such as configured to transmit via 64; see for example figs. 3C and 4, para. [0094]- [0110]) a second signal (i.e., such as second signal RF Out; see for example figs. 3C and 4, para. [0094]- [0110]), wherein the first signal (i.e., such as first signal RF In; see for example figs. 3C and 4, para. [0094]- [0110]) is differential (i.e., such as RF In is differential to RF Out; see for example figs. 3C and 4, para. [0094]- [0110]) to the second signal (i.e., such as second signal RF Out; see for example figs. 3C and 4, para. [0094]- [0110]).
Regarding claim 22, Shimamura in view Miwa and further in view of Brewer and the teachings of Shimamura as modified by Miwa have been discussed above. Also, the teachings of Shimamura as modified by Brewer have been discussed above as well.
Brewer further discloses the IC chip apparatus (i.e., see for example figs. 3C and 4, para. [0094]- [0110]); wherein the top surface (i.e., such as top surface at numerals 272/275-1A/275-2; see for example figs. 3C and 4, para. [0094]- [0110]) and the lateral surface (i.e., such as lateral surface at numerals 275-1B/273-3; see for example figs. 3C and 4, para. [0094]- [0110]) of the encapsulation layer (i.e., such as encapsulation layer 170; see for example figs. 3C and 4, para. [0094]- [0110]) are faced toward (i.e., such as faced toward numeral 174; see for example figs. 3C and 4, para. [0094]- [0110]) the opening (i.e., such as the opening g; see for example figs. 3C and 4, para. [0094]- [0110]), and wherein the encapsulation layer (i.e., such as encapsulation layer 170; see for example figs. 3C and 4, para. [0094]- [0110]) and the shield (i.e., such as the shield 175-1/175-2; see for example figs. 3C and 4, para. [0094]- [0110]) together define boundaries (i.e., such as together define boundaries 174; see for example figs. 3C and 4, para. [0094]- [0110]) of the opening (i.e., such as the opening g; see for example figs. 3C and 4, para. [0094]- [0110]), and wherein a depth (i.e., such depth of 170; see for example figs. 3C and 4, para. [0094]- [0110]) of the opening (i.e., such as the opening g; see for example figs. 3C and 4, para. [0094]- [0110]) is greater (i.e., such as depth of 170 > thickness of 170; see for example figs. 3C and 4, para. [0094]- [0110]) than a thickness (i.e., such as thickness of 170; see for example figs. 3C and 4, para. [0094]- [0110]) of the encapsulation layer (i.e., such as encapsulation layer 170; see for example figs. 3C and 4, para. [0094]- [0110]) in a first direction (i.e., such as first direction Y-axis; see for example figs. 3C and 4, para. [0094]- [0110]) substantially perpendicular (i.e., such as Y-axis is substantially perpendicular on plane 60; see for example figs. 3C and 4, para. [0094]- [0110]) to the top surface (i.e., such as top surface at numerals 272/275-1A/275-2; see for example figs. 3C and 4, para. [0094]- [0110]), and wherein a first width (i.e., such as first width of g with respect to numeral 273-4 in the Z-axis of plane 60; see for example figs. 3C and 4, para. [0094]- [0110]) of the opening (i.e., such as the opening g; see for example figs. 3C and 4, para. [0094]- [0110]) is greater (i.e., such as first width of g with respect to numeral 273-4 > second width of g with respect to numeral 273-3 in the X-axis of plane 60; see for example figs. 3C and 4, para. [0094]- [0110]) than a second width (i.e., such as second width of g with respect to numeral 273-3 in the X-axis of plane 60; see for example figs. 3C and 4, para. [0094]- [0110]) of the encapsulation layer (i.e., such as encapsulation layer 170; see for example figs. 3C and 4, para. [0094]- [0110]) in a second direction (i.e., such as second direction Z-axis; see for example figs. 3C and 4, para. [0094]- [0110]) substantially perpendicular (i.e., such as Z-axis of plane 60 is substantially perpendicular on Y-axis; see for example figs. 3C and 4, para. [0094]- [0110]) to the first direction (i.e., such as first direction Y-axis; see for example figs. 3C and 4, para. [0094]- [0110]).
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Shimamura et al (US Publication No. 20150016066) in view of Doyle et al (US Publication No. 20240219450).
Regarding claim 18, Shimamura discloses the electronic device (i.e., such as electronic device 100B; see for example fig. 10, para. [0120]- [0128]); an electronic device (i.e., such as electronic device 100B; see for example fig. 10, para. [0120]- [0128]), comprising: a carrier (i.e., such as carrier 2/25; see for example fig. 10, para. [0120]- [0128]) having a long side (i.e., such as the long side of 2/25 in the Y-axis; see for example fig. 10, para. [0120]- [0128]); a circuit module (i.e., such as circuit module 31, 32; see for example fig. 10, para. [0120]- [0128]) disposed over the carrier (i.e., such as carrier 2/25; see for example fig. 10, para. [0120]- [0128]); and a shield (i.e., such as shield 5B; see for example fig. 10, para. [0120]- [0128]) surrounding the circuit module (i.e., such as circuit module 31, 32; see for example fig. 10, para. [0120]- [0128]) and comprising an opening (i.e., such as opening 513B; see for example fig. 10, para. [0120]- [0128]).
Shimamura does not explicitly disclose wherein the electronic device has a Time Domain Reflectometry (TDR) characteristic, and wherein the TDR characteristic has a first turning point corresponding to a location of the opening with respect to the long side of the carrier.
Doyle discloses and IC chip apparatus (i.e., see for example figs. 3 and 11, para. [0038]- [0056]); wherein the electronic device (i.e., such as the electronic device 700; see for example figs. 3 and 11, para. [0038]- [0056]) has a Time Domain Reflectometry (TDR) characteristic (i.e., such as Time Domain Reflectometry (TDR) characteristic 702; see for example figs. 3 and 11, para. [0038]- [0056]), and wherein the TDR characteristic (i.e., such as Time Domain Reflectometry (TDR) characteristic 702; see for example figs. 3 and 11, para. [0038]- [0056]) has a first turning point (i.e., such as first turning point 80; see for example figs. 3 and 11, para. [0038]- [0056]) corresponding to a location (i.e., such as location 54; see for example figs. 3 and 11, para. [0038]- [0056]) of the opening (i.e., such as opening 20; see for example figs. 3 and 11, para. [0038]- [0056]) with respect to the long side (i.e., such as the long side of 12 in X-axis; see for example figs. 3 and 11, para. [0038]- [0056]) of the carrier (i.e., such as the carrier 12; see for example figs. 3 and 11, para. [0038]- [0056]).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the TDR device in Shimamura, as taught by Doyle, as it provides the advantage of optimizing the circuit design.
Allowable Subject Matter
Claims 19-21 and 23 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 19, Shimamura in view of Doyle teaches the invention set forth above. However, neither Shimamura nor Doyle particularly teaches wherein the circuit module comprises a first passive component exposed by the opening, and wherein the first turning point of the TDR characteristic represents a parasitic coupling among the first passive component, the shield, and an external environment.
Hence claim 19 will be deemed allowable if rewritten in an independent form.
Regarding claim 20, Shimamura in view of Doyle teaches the invention set forth above. However, neither Shimamura nor Doyle particularly teaches wherein the first turning point has a first impedance value that is higher than a second impedance value of a second turning point of a TDR characteristic of an external electronic device that is completely isolated from an external environment.
Hence claim 20 will be deemed allowable if rewritten in an independent form.
Regarding claim 21, Shimamura teaches the invention set forth above. However, Shimamura does not particularly teach wherein the first shield comprises a first portion and a second portion separated from the first portion by the first opening, the first portion has a first volume and the second portion has a second volume greater than the first volume, wherein the second portion physically and electromagnetically shields more components of the first circuit module than the first portion, wherein the first portion of the first shield has a plurality of first lateral surfaces and a first top surface, wherein the second portion of the first shield has a plurality of second lateral surfaces and a second top surface, and wherein the first lateral surfaces and the first top surface are substantially aligned with the second lateral surfaces and the second top surface, respectively.
Hence claim 21 will be deemed allowable if rewritten in an independent form.
Regarding claim 23, Shimamura in view of Doyle teaches the invention set forth above. However, neither Shimamura nor Doyle particularly teaches wherein the opening is configured to provide a near-end-cross-talk characteristic between adjacent terminals of the electronic device that is lower than that of an unshielded device and higher than that of a fully shield device to optimize signal sensitivity, and wherein the opening is further configured to increase transmission efficiency by maintaining the TDR characteristic with a reduced variation in impedance values along a transmission path, such that the first turning point exhibits a moderate impedance value relative to a parasitic inductance of an unshielded environment and a parasitic capacitance of a fully isolated environment, thereby reducing parasitic coupling.
Hence claim 23 will be deemed allowable if rewritten in an independent form.
Claims 6, 10 and 12 are cancelled.
Conclusion
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/MUAAMAR QAHTAN AL-TAWEEL/Examiner, Art Unit 2838
/THIENVU V TRAN/ Supervisory Patent Examiner, Art Unit 2838
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