Prosecution Insights
Last updated: October 23, 2026
Application No. 18/905,287

SEMICONDUCTOR DEVICE WITH SiC SEMICONDUCTOR LAYER AND RAISED PORTION GROUP

Non-Final OA §102§103§DOUBLEPATENT
Filed
Oct 03, 2024
Priority
Mar 30, 2018 — JP 2018-068567 +4 more
Examiner
WARD, ERIC A
Art Unit
2891
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Rohm Co., Ltd.
OA Round
1 (Non-Final)
78%
Grant Probability
Favorable
1-2
OA Rounds
5m
Est. Remaining
92%
With Interview

Examiner Intelligence

Grants 78% — above average
78%
Career Allowance Rate
594 granted / 759 resolved
+10.3% vs TC avg
Moderate +13% lift
Without
With
+13.3%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
28 currently pending
Career history
786
Total Applications
across all art units

Statute-Specific Performance

§101
0.7%
-39.3% vs TC avg
§103
58.1%
+18.1% vs TC avg
§102
21.2%
-18.8% vs TC avg
§112
15.6%
-24.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 759 resolved cases

Office Action

§102 §103 §DOUBLEPATENT
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Double Patenting The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. Claims 1-22 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-22 of U.S. Patent Number 11,489,051 in view of US 2018/0174840 A1 to Joshi et al., with anticipating limitations in italics below. This rejection cannot be held in abeyance, as per MPEP 804: “As filing a terminal disclaimer, or filing a showing that the claims subject to the rejection are patentably distinct from the reference application’s claims, is necessary for further consideration of the rejection of the claims, such a filing should not be held in abeyance.” Pending claims: Claim 1, A semiconductor device comprising: an SiC semiconductor layer which has a first main surface on one side and a second main surface on the other side; a semiconductor element which is formed in the first main surface; a raised portion group which includes a plurality of raised portions formed at intervals from each other at the second main surface and has a first portion in which some of the raised portions among the plurality of raised portions overlap each other in a first direction view as viewed from a first direction which is one of the plane directions of the second main surface; and an electrode which is formed on the second main surface and connected to the raised portion group, wherein the electrode has an unevenness surface. US Patent Number 11,489,051: Claim 1. A semiconductor device comprising: an SiC semiconductor layer which has a first main surface on one side and a second main surface on the other side; a semiconductor element which is formed in the first main surface; a raised portion group which includes a plurality of raised portions formed at intervals from each other at the second main surface and has a first portion in which some of the raised portions among the plurality of raised portions overlap each other in a first direction view as viewed from a first direction which is one of the plane directions of the second main surface; an Si amorphous layer formed in a surface layer portion of the second main surface inside the SiC semiconductor layer; and an electrode which is formed on the second main surface and connected to the raised portion group, wherein at least one of the plurality of raised portions is formed in a protruding shape having a curvature in a cross-sectional view. US Patent Number 11,489,051 in claim 1 fails to clearly claim wherein the electrode has an unevenness surface. Joshi teaches (e.g. FIG 8) wherein an electrode (drain “D” 302, ¶ [0095]-[0096]) has an unevenness surface (due to clusters or agglomerations 300, ¶ [0059]-[0060],[0062],[0067]). It would have been obvious to a person having ordinary skill in the art to have formed the device of U.S. Patent Number 11,489,051 claim 1 with the electrode having an unevenness surface as taught by Joshi in order to form a cost-competitive, reliable and easily applicable ohmic contact (Joshi ¶ [0002]) with a reliable and stable mechanical connection (Joshi ¶ [0067]). Pending claim 2 is anticipated by US Patent Number 11,489,051 claim 2. Pending claim 3 is anticipated by US Patent Number 11,489,051 claim 3. Pending claim 4 is anticipated by US Patent Number 11,489,051 claim 4. Pending claim 5 is anticipated by US Patent Number 11,489,051 claim 5. Pending claim 6 is anticipated by US Patent Number 11,489,051 claim 6. Pending claim 7 is anticipated by US Patent Number 11,489,051 claim 7. Pending claim 8 is anticipated by US Patent Number 11,489,051 claim 8. Pending claim 9 is anticipated by US Patent Number 11,489,051 claim 9. Pending claim 10 is anticipated by US Patent Number 11,489,051 claim 10. Pending claim 11 is anticipated by US Patent Number 11,489,051 claim 11. Pending claim 12 is anticipated by US Patent Number 11,489,051 claim 12. Pending claim 13 is anticipated by US Patent Number 11,489,051 claim 13. Pending claim 14 is anticipated by US Patent Number 11,489,051 claim 14. Pending claim 15 is anticipated by US Patent Number 11,489,051 claim 15. Pending claim 16 is anticipated by US Patent Number 11,489,051 claim 16. Pending claim 17 is anticipated by US Patent Number 11,489,051 claim 17. Pending claim 18 is anticipated by US Patent Number 11,489,051 claim 18. Pending claim 19 is anticipated by US Patent Number 11,489,051 claim 19. Pending claim 20 is anticipated by US Patent Number 11,489,051 claim 20. Pending claim 21 is anticipated by US Patent Number 11,489,051 claim 21. Pending claim 22 is anticipated by US Patent Number 11,489,051 claim 22. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1,21,22 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2015/0348783 A1 to Fukuda, “Fukuda”. Regarding claim 1, Fukuda discloses a semiconductor device comprising: an SiC semiconductor layer (1 and 2, ¶ [0041]-[0042]) which has a first main surface (upwards) on one side and a second main surface (downwards connected to electrode 9) on the other side; a semiconductor element (comprising 2, 5-1, 5-2, 6, 7, ¶ [0041]-[0042]) which is formed in the first main surface; a raised portion group (textured bottom surface in FIG. 4,5 due to treatments ¶ [0056]-[0061]) which includes a plurality of raised portions formed at intervals from each other at the second main surface and has a first portion in which some of the raised portions among the plurality of raised portions overlap each other in a first direction view as viewed from a first direction which is one of the plane directions of the second main surface; and an electrode (9, ¶ [0062]) which is formed on the second main surface and connected to the raised portion group, wherein the electrode (9) has an unevenness surface (as pictured surface between 9 and 1). PNG media_image1.png 495 782 media_image1.png Greyscale Examiner’s Note: the term “unevenness” or “unevenness surface” is not expressly defined in Applicant’s specification and is therefore interpreted under the doctrine of broadest reasonable interpretation (BRI), Phillips v. AWH Corp., 415 F.3d 1303, 1316, 75 USPQ2d 1321, 1329 (Fed. Cir. 2005), MPEP 2111, as for example not smooth or level, irregular, broken, or rugged1. Regarding claim 21, Fukuda discloses the semiconductor device according to Claim 1, and Fukuda further discloses wherein the semiconductor element includes a Schottky barrier diode (Schottky diode, ¶ [0067]). Regarding claim 22, Fukuda discloses the semiconductor device according to Claim 1, and Fukuda further discloses wherein the semiconductor element includes a field effect transistor (MOSFET or IGBT, ¶ [0067]). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claims 7-9 are rejected under 35 U.S.C. 103 as being unpatentable over US 2015/0348783 A1 to Fukuda, “Fukuda”. Although Fukuda discloses the semiconductor device according to claim 1, Fukuda fails to clearly anticipate in sufficient specificity for anticipation (MPEP 2131.03) wherein the raised portion group is formed in a range of not less than 10 microns and not more than 200 microns in terms of a direction orthogonal to the first direction on the second main surface, wherein the range is not less than 50 microns and not more than 150 microns, wherein the range is not less than 80 microns and not more than 120 microns. However, Fukuda teaches wherein the cross section of the laser beam which determines the range of the raised/textured portions is 50 microns (¶ [0059]) and up to the whole second main surface of the substrate. It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the device of Fukuda with the raised/textured surface having a range within the claimed ranges as suggested by Fukuda in order to tune the electrode area or overall dimensions of the device since it has been held that “where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955), In re Hoeschele, 406 F.2d 1403, 160 USPQ 809 (CCPA 1969), wherein in the instant case the raised/textured range determines the area of the electrode and/or area of the overall device making it a result effective variable, In re Antonie, 559 F.2d 618, 195 USPQ 6 (CCPA 1977), and MPEP 2144.05 Obviousness of Ranges II. OPTIMIZATION OF RANGES A. Optimization Within Prior Art Conditions or Through Routine Experimentation B. Only Result-Effective Variables Can Be Optimized. Examiner’s Note: the raised portions being formed within a range does not exclude areas outside of the range of also including the raised portions under the doctrine of broadest reasonable interpretation (BRI, MPEP 2111). Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over US 2015/0348783 A1 to Fukuda, “Fukuda”, in view of US 2012/0223335 A1 to Tsuchiya, “Tsuchiya”. Regarding claim 2, although Fukuda discloses the semiconductor device according to claim 1, Fukuda fails to clearly teach wherein the raised portion group has a second portion in which some of the raised portions among the plurality of raised portion are formed separate from the first portion in the first direction view and also overlap each other in the first direction view. Tsuchiya teaches (e.g. FIG. 1B) wherein a raised portion group (e.g. one of group 10) has a second portion (i.e. another of group 10) in which some of the raised portions among the plurality of raised portions are separate from the first portion in the first direction view and also overlap each other in the first direction view (e.g. see Examiner-annotated FIG. 1B below): PNG media_image2.png 656 530 media_image2.png Greyscale It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the device of Fukuda with separated yet overlapping raised groups as exemplified by Tsuchiya in order to desirably also add identifying markers to the SiC substrate thereby enhancing the functionality (by adding the function of wafer or device identification, Tsuchiya Abstract, ¶ [0005],[0015]) and desirably without generating excess particles (Tsuchiya ¶ [0010]-[0013]). Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over US 2015/0348783 A1 to Fukuda, “Fukuda”, in view of US 2014/0232004 A1 to Yoshiura et al., “Yoshiura”. Regarding claim 2, although Fukuda discloses the semiconductor device according to claim 1, Fukuda fails to clearly teach wherein the raised portion group has a second portion in which some of the raised portions among the plurality of raised portion are formed separate from the first portion in the first direction view and also overlap each other in the first direction view. Yoshiura teaches (e.g. FIG. 1) wherein a raised portion group has a second portion in which some of the raised portions among the plurality of raised portions are formed separated (see Examiner-annotated figure below) from the first portion in the first direction view and also overlap each other in the first direction view: PNG media_image3.png 404 579 media_image3.png Greyscale It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the device of Fukuda with the raised portions on the edges as taught by Yoshiura in order to desirably prevent peeling and/or enhance the bonding strength between the back electrode and the substrate (Yoshiura ¶ [0029],[0030]). Claims 3-6 are rejected under 35 U.S.C. 103 as being unpatentable over US 2015/0348783 A1 to Fukuda, “Fukuda”, in view of US 2015/0076518 A1 to Tanigawa et al., “Tanigawa”. Regarding claim 3, although Fukuda discloses the semiconductor device according to claim 1, Fukuda fails to clearly teach wherein the raised portion groups are formed in plurality at intervals along a second direction which is one of the plane directions of the first main surface and which intersects the first direction. Tanigawa teaches wherein raised portion groups (i.e. ridges and valleys formed by laser texturing) are formed along a plurality of intervals along a second direction (see Examiner-annotated figure below) which is one of the plane directions of the first main surface and which intersects with the first direction. PNG media_image4.png 685 738 media_image4.png Greyscale It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the device of Fukuda with the raised groups or textured surface having the surface layout as taught by Tanigawa in order to form a good ohmic contact with reduced Schottky resistance (Tanigawa Abstract). Regarding claim 4, Fukuda in view of Tanigawa yields the semiconductor device according to claim 3, and Tanigawa further teaches wherein a distance between the plurality of raised portion groups that are mutually adjacent is not more than 100 microns (700 nm or 0.7 micron, ¶ [0058]). Regarding claim 5, Fukuda in view of Tanigawa yields the semiconductor device according to claim 4, and Tanigawa further teaches wherein the distance is not more than 50 microns (700 nm or 0.7 micron, ¶ [0058]). Regarding claim 6, Fukuda in view of Tanigawa yields the semiconductor device according to claim 4, and Tanigawa further teaches wherein the distance is not more than 20 microns (700 nm or 0.7 micron, ¶ [0058]). Claims 10-14 are rejected under 35 U.S.C. 103 as being unpatentable over US 2015/0348783 A1 to Fukuda, “Fukuda”, in view of US 2016/0254357 A1 to Aketa, “Aketa `357”. Regarding claim 10, Fukuda discloses the semiconductor device according to claim 1, and Fukuda further discloses wherein the SiC semiconductor layer includes 4H-SiC (¶ [0057]). Fukuda fails to clearly teach wherein the first direction is a [11-20] direction of the 4H-SiC. Aketa `357 teaches a 4H-SiC substrate with a first direction of [11-20] (FIG. 4, i.e. the “a-face” direction is a direction along the planar face of the off-angle SiC substrate). It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the device of Fukuda with the off-angle 4H-SiC substrate of Aketa `357 in order to select a substrate having improvement in controllability in epitaxial growth (Aketa `357 ¶ [0007]) and/or a device with more effective improvement in breakdown voltage (Aketa `357 ¶ [0010]). Regarding claim 11, Fukuda discloses the semiconductor device according to claim 1, and Fukuda further discloses wherein the SiC semiconductor layer includes 4H-SiC (¶ [0057]). Fukuda fails to clearly teach wherein the first direction is a [1-100] direction of the 4H-SiC. Aketa `357 teaches a 4H-SiC substrate with a first direction of [1-100] (FIG. 5, i.e. the “m-face” direction is a direction along the planar face of the off-angle SiC substrate). It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the device of Fukuda with the off-angle 4H-SiC substrate of Aketa `357 in order to select a substrate having improvement in controllability in epitaxial growth (Aketa `357 ¶ [0007]) and/or a device with more effective improvement in breakdown voltage (Aketa `357 ¶ [0010]). Regarding claim 12, Fukuda in view of Aketa `357 yields the semiconductor device according to claim 10, and Aketa `357 further teaches wherein the SiC semiconductor layer has an off angle inclined at an angle of not more than 10 degrees from a (0001) plane of the 4H-SiC to an [11-20] direction (¶ [0006]). Regarding claim 13, Fukuda in view of Aketa `357 yields the semiconductor device according to Claim 12, and Aketa `357 further teaches wherein the off angle is not less than 0° and not more than 4° (¶ [0006],[0105],[0106],[0108]). Regarding claim 14, Fukuda in view of Aketa `357 yields the semiconductor device according to claim 12, and Aketa `357 further teaches wherein the off angle is greater than 0° and less than 4° (¶ [0006],[0105],[0106],[0108]). Claims 15-20 are rejected under 35 U.S.C. 103 as being unpatentable over US 2015/0348783 A1 to Fukuda, “Fukuda”, in view of US 2014/0225126 A1 to Aketa et al., “Aketa `126”. Regarding claim 15, although Fukuda discloses the semiconductor device according to claim 1, Fukuda fails to clearly teach wherein the electrode (9) includes at least one type of Ti, Ni, Au, and Ag. Aketa `126 teaches (e.g. FIG. 3) wherein an electrode (38) includes Ti or Ni (in silicide form, ¶ [0134]). It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the device of Fukuda with backside trenches and Ti or Ni as an electrode material as taught by Aketa `126 in order to form a SiC-IGBT with an improved ohmic collector contact (Aketa `126 contact 27, ¶ [0134], Fukuda ¶ [0008],[0030]), and since it has been held that the selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945), In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960), and MPEP 2144.07 Art Recognized Suitability for an Intended Purpose. Regarding claim 16, although Fukuda discloses the semiconductor device according to claim 1, Fukuda fails to clearly teach wherein the electrode (9) includes a Ti layer in contact with the raised portion group. Aketa `126 teaches (e.g. FIG. 3) wherein an electrode (38) includes Ti (in silicide form, ¶ [0134]) covering the entire bottom surface. It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the device of Fukuda with backside trenches and Ti as an electrode material as taught by Aketa `126 in order to form a SiC-IGBT with an improved ohmic collector contact (Aketa `126 contact 27, ¶ [0134], Fukuda ¶ [0008],[0030]), and since it has been held that the selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945), In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960), and MPEP 2144.07 Art Recognized Suitability for an Intended Purpose. Regarding claim 17, although Fukuda discloses the semiconductor device according to claim 1, Fukuda fails to clearly teach wherein the electrode includes an Ni layer in contact with the raised portion group. Aketa `126 teaches (e.g. FIG. 3) wherein an electrode (38) includes Ni (in silicide form, ¶ [0134]) covering the entire bottom surface. It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the device of Fukuda with backside trenches and Ni as an electrode material as taught by Aketa `126 in order to form a SiC-IGBT with an improved ohmic collector contact (Aketa `126 contact 27, ¶ [0134], Fukuda ¶ [0008],[0030]), and since it has been held that the selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945), In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960), and MPEP 2144.07 Art Recognized Suitability for an Intended Purpose. Regarding claim 18, although Fukuda discloses the semiconductor device according to claim 1, Fukuda fails to clearly teach a groove formed in the second main surface of the SiC semiconductor layer. Aketa `126 teaches (e.g. FIG. 3) a groove (36, ¶ [0131]) in a second main surface of a SiC semiconductor layer (33, ¶ [0129]). It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the device of Fukuda with backside trenches as taught by Aketa `126 in order to form a SiC-IGBT with an improved ohmic collector contact (Aketa `126 contact 27, ¶ [0134], Fukuda ¶ [0008],[0030]). Regarding claim 19, although Fukuda in view of Aketa `126 yields the semiconductor device according to Claim 18, Fukuda and Aketa `126 fail to individually anticipate wherein the groove includes a portion which intersects the raised portion group. However, Aketa `126 teaches wherein the grooves (36) are formed along the entire bottom surface (as pictured) and Fukuda teaches wherein the raised portions extend along the entire bottom surface (as pictured). Therefore, it would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the device of Fukuda with backside trenches intersecting the raised portion groups as suggested by Aketa `126 and Fukuda in the process of forming both covering the entire surface in order to form a SiC-IGBT with an improved ohmic collector contact (Aketa `126 contact 27, ¶ [0134], Fukuda ¶ [0008],[0030]). Regarding claim 20, although Fukuda in view of Aketa `126 yields the semiconductor device according to Claim 18, Fukuda and Aketa `126 fail to individually anticipate wherein the raised portion group includes a portion in which some of the raised portions among the plurality of raised portions are formed at intervals along the groove in a plan view as viewed in a normal direction of the second main surface. However, Aketa `126 teaches wherein the grooves (36) are formed along the entire bottom surface in a grid (i.e. intervals, ¶ [0131]) and Fukuda teaches wherein the raised portions extend along the entire bottom surface (as pictured). Therefore, it would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the device of Fukuda with backside trenches intersecting the raised portion groups as suggested by Aketa `126 and Fukuda in the process of forming both covering the entire surface in order to form a SiC-IGBT with an improved ohmic collector contact (Aketa `126 contact 27, ¶ [0134], Fukuda ¶ [0008],[0030]). Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: “Ohmic Contact Formation on Inductively Coupled Plasma Etched 4H-Silicon Carbide” by S.K.Lee et al. in Journal of ELECTRONIC MATERIALS, Vol. 31, No. 5, 2002 teaches the effect of forming a titanium-tungsten ohmic contact to a roughened 4H-SiC surface (Abstract). Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC A WARD whose telephone number is (571)270-3406. The examiner can normally be reached M-F 10-6 ET. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at (571)272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Eric A. Ward/ Primary Examiner, Art Unit 2891 09/29/2026 1 Oxford English Dictionary entry for “uneven”, entry 4.
Read full office action

Prosecution Timeline

Oct 03, 2024
Application Filed
Oct 02, 2026
Non-Final Rejection mailed — §102, §103, §DOUBLEPATENT (current)

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Prosecution Projections

1-2
Expected OA Rounds
78%
Grant Probability
92%
With Interview (+13.3%)
2y 6m (~5m remaining)
Median Time to Grant
Low
PTA Risk
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