Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Response to Amendment
The Amendment filed August 21, 2026 has been entered.
Claims 1-4 are rejected over the previously applied reference(s).
Claim Objections
Claims 10-11 are objected to because of the following informalities: “the level-shifting circuitry” in claim 10 and “the level-shifting” in claim 11 should each be changed to “the level-shifting circuit”.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
First 102 rejection
Claim 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 6,842,046 to Tzartzanis et al. (“Tzar”).
With respect to claim 1, Tzar discloses in Figs. 4 and 9 a circuit for level-shifting comprising:
a pulse-shaper circuit (e.g., 910, T10 and Inv4 in Fig. 9) comprising a first PMOS transistor (e.g., T10) and a first level-shifter configured by one or more NAND gates (e.g., 910 is a NAND gate according to Col. 7 ll. 6-7; the NAND gate level-shifts all 1/high inputs of the NAND gate to a 0/low output of the gate); and
a level-shifting circuit (e.g., T11 is a level shifter in that T11 converts a low input at the gate of T11 into a high output Vdd at the drain of T11), wherein:
the first PMOS transistor (e.g., T10 precharges X1 to Vdd in response to low PC level during Precharge period before the voltage at X1 can change in response to inputs 412-414 during the Evaluate period as shown in Fig. 5) is configured to precharge a node (e.g., X1) on a wordline generation path (e.g., the write circuit for word/bit lines for the Fig. 10 circuit includes the voltage conversion circuit in Fig. 4 (e.g.., Col. 3 ll. 23-31) of the level-shifting circuit.
Second 102 rejection
Claims 1 and 5 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 5,748,012 to Beakes et al. (“Beakes”).
With respect to claim 1, Beakes discloses in Fig. 1 a circuit for level-shifting comprising:
a pulse-shaper circuit (e.g., I22-I23 and OR) comprising a first PMOS transistor (e.g., OR) and a first level-shifter configured by one or more NAND gates (e.g., I22-I23); and
a level-shifting circuit (e.g., OS is a level shifter in that OS converts a low input at the gate of OS into a high output at the drain of OS), wherein:
the first PMOS transistor (e.g., OR precharges A to high in response to low R before EVALUATE PHASE in Fig. 2B for receiving INPUTS) is configured to precharge a node (e.g., A) on a wordline generation path (e.g., as discussed below). As to the feature that the the first PMOS transistor (e.g., OR precharges A to high in response to low R before EVALUATE PHASE in Fig. 2B for receiving INPUTS) is configured to precharge a node (e.g., A) on a wordline generation path, such a feature is considered to be a recitation of the intended use of the claimed invention: the claim invention does not recite a memory structure and bit/word lines associated with the memory structure. A recitation of the intended use of the claimed invention must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim. Here, the driver in Fig. 1 of Beakes is capable of the recited use (e.g., being used to drive a node on a wordline generation path for a memory).
With respect to claim 5, the one or more NAND gates (e.g., I22-I23) comprises two NAND gates.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
103 rejections based on Tzar
Claims 2-4 are rejected under 35 U.S.C. 103 as being unpatentable over Tzar.
With respect to claim 2, Tzar discloses the first PMOS transistor (e.g., T10) of the pulse-shaper circuit but fails to disclose that PMOS transistor T11 of the level-shifting circuit (e.g., T11) includes multiple PFETs in parallel. However, it was notoriously well-known in the art to a person of skill in the art before the effective filing date of the claimed invention that a transistor conducting a current can be implemented by parallel-connected transistors of smaller dimensions conducting smaller currents to save costs and/or conduct smaller currents through each MOSFET and thus reduce stress on the transistor. The foregoing common knowledge or well-known in the art statement is taken to be admitted prior art because applicant failed to timely traverse the examiner’s assertion of official notice. See MPEP 2144.03(C). Thus, it would have been obvious to a person of ordinary skill in the art to implement PMOS transistor T11 in Fig. 4 of Tzar using the notoriously well-known method of forming a switch with parallel-connected transistors of smaller dimensions because such a modification would reduce costs and/or enable smaller currents to flow through each MOSFET to reduce stress through the switch.
With respect to claim 3, the above discussion for claim 2 similarly applies. T10 is larger than T11 (e.g., Col. 5 ll. 52-54). After the above discussed modification to replace PMOS transistor T11 in Fig. 4 of Tzar with smaller dimensioned PFETs in parallel, T10 is even larger in dimension in comparison to the smaller dimensioned PFETs in parallel for T10.
With respect to claim 4, as to the feature that the first PMOS transistor of the pulse-shaper circuit is configured with a higher voltage-threshold (VT)-type in comparison to one or more PMOS transistors of the level-shifting circuit, T10 and T11’s thresholds may differ slightly in fabrication, however small, and further, such a specific parameter in output characteristic will not support the patentability of the subject matter encompassed by the prior art unless there is evidence indicating the parameters are critical. Absent any evidence demonstrating a patentable difference between the compositions and the criticality of the claimed amounts, the determination of the optimum or workable range(s) given the guidance of the prior art would have been generally prima facie obvious to the skilled artisan. Please see MPEP §2144.05 [R-2](II)(A) and In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) ("[W]here the general conditions of claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation."). It is noted that the specification contains no disclosure of either the critical nature of the instant parameters or any unexpected results arising thereof. Since applicant has not established the criticality of the specific parameters, it would have been obvious to one of ordinary skill in the art before the filing of the claimed invention to use this value in the Fig. 4 circuit of Tzar.
103 rejections based on Beakes
With respect to claim 10, Beakes discloses a node A in Fig. 1. As to the feature that the node (e.g., A) is configured to transmit a clock signal to a plurality of logic gates, such a feature is considered to be a recitation of the intended use of the claimed invention: the logic gates are not positively recited as elements of the claim. A recitation of the intended use of the claimed invention must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim. Here, the node A in Fig. 1 of Beakes is capable of the recited use (e.g., being used to output a clock signal to logic gates).
Further, the level-shifting circuitry (e.g., OS and I21) is arranged as a NAND gate (e.g., I21). As to the details of the NAND gate I21, it was notoriously well known to a person of ordinary skill in the art before the effective filing date of the claimed invention that a NAND gate may comprise two PMOS transistors coupled in parallel and two NMOS transistors coupled in series with a node coupled between the PMOS transistors and the NMOS transistors. The foregoing common knowledge or well-known in the art statement is taken to be admitted prior art because applicant failed to timely traverse the examiner’s assertion of official notice. See MPEP 2144.03(C). Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to implement NAND gate 910 in Fig. 9 of Tzar using the notoriously well-known NAND gate comprising two PMOS transistors coupled in parallel and two NMOS transistors coupled in series with a node coupled between the PMOS transistors and the NMOS transistors because NAND gate I21 in Fig. 1 of Beakes requires a specific implementation in fabrication and the notoriously well-known example provides a specific implementation.
With respect to claim 11, PMOS transistors (e.g., the above discussed smaller dimensioned PFETs in parallel replacing PMOS transistor for T11 in Fig. 4 of Tzar in claim 2 discussion similarly applies to OR in Fig. 1 of Beakes) are configured to maintain the precharge of the node (e.g., A), comprise a decreased size (e.g., as discussed above) in comparison to NMOS transistors, and are configured to increase (e.g., via latching by OS and 10) the speed of transition of the clock signal (e.g., A).
Response to Arguments
Applicant's arguments filed August 21, 2026 have not been found persuasive. For example, Applicant argues that Tzar does not disclose the added feature of claim 1. However, as stated above in the main body of the rejections, such a feature is disclosed in Tzar and also in Beakes.
Allowable Subject Matter
Claims 6-9 and 12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jung KIM whose telephone number is (571)270-7964. The examiner can normally be reached on M-F from 9AM to 5:30PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Regis BETSCH, can be reached at (571)270-7101. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JUNG KIM/
Primary Examiner, Art Unit 2836
