Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the response to this Office action, the Office respectfully requests that support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line numbers in the specification and/or drawing figure(s). This will assist the Office in prosecuting this application.
The Office has cited particular figures, elements, paragraphs and/or columns and line numbers in the references as applied to the claims for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant, in preparing the responses, to fully consider each of the cited references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage disclosed by the Office.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after allowance or after an Office action under Ex Parte Quayle, 25 USPQ 74, 453 O.G. 213 (Comm'r Pat. 1935). Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, prosecution in this application has been reopened pursuant to 37 CFR 1.114. Applicant's submission filed on June 2, 2026 has been entered.
Status of Claims
- Claim(s) 11-16, 20 is/are withdrawn as non-elected
- Claim(s) 1-20 is/are pending in the application.
- Claim(s) 1-10, 17-19 is/are examined on the merits
Indicated Allowability Withdrawn
The indicated allowability of claims 1-20 is withdrawn in view of the newly discovered reference(s) to Park et al, U.S. Patent Publication No. 20210049959. Rejections based on the newly cited reference(s) follow.
Election/Restrictions
Applicant’s election without traverse of Species A in the reply filed on October 17, 2025 is acknowledged.
Claims 11-16, 20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on April 14, 2023.
Applicant is reminded that upon the cancelation of claims to a non-elected invention, the inventorship must be corrected in compliance with 37 CFR 1.48(a) if one or more of the currently named inventors is no longer an inventor of at least one claim remaining in the application. A request to correct inventorship under 37 CFR 1.48(a) must be accompanied by an application data sheet in accordance with 37 CFR 1.76 that identifies each inventor by his or her legal name and by the processing fee required under 37 CFR 1.17(i).
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
The application has claimed priority based on prior filed U.S. Application Serial No. 17583005 (now U.S. Patent No. 12142209) filed on January 24, 2022.
Lexicographic
After careful review of the original specification, the Examiner notes that paragraph 0074 includes a lexicographic definition for “set” and “element” - A "set" may include zero, one, or more items/elements. An "element" may mean "element set" that includes one or more analogous elements. See MPEP §2111.01 IV.
Examiner further notes that Applicant’s specification does not appear to specifically define “floating node”. However, it appears that “floating node” is described as a node between a two transistors connected in series (see Applicant’s original specification paragraph 0102-0104, 0178, 0200, 0217, 0226, 0279 where data initialization switching element T4 disposed between the driving switching element and the initialization voltage terminal is a single transistor instead of two transistors, and the compensation switching element TA is connected to the data initialization switching element T4 in series, so that the data initialization switching element T4 may not include a floating node between two transistors).
Terminal Disclaimer
The terminal disclaimer filed on January 8, 2026 disclaiming the terminal portion of any patent granted on this application which would extend beyond the expiration date of U.S. Patent Publication No. 12142209 has been reviewed and is accepted. The terminal disclaimer has been recorded.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-5, 8-10, 17-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park et al, U.S. Patent Publication No. 20210049959 in view of Kobashi U.S. Patent Publication No. 20200410933.
Consider claim 1, Park teaches a pixel comprising: a light emitting element (see Park figure 2, element OLED);
a driving switching element configured to provide a driving current to the light emitting element (see Park figure 2, element DT);
an initialization voltage terminal (see Park figure 2, element VINT);
a data initialization switching element set (see Park figure 2, element IT1);
an adjustment switching element electrically connected to the data initialization switching element set in series (see Park figure 2, element IT2),
wherein the data initialization switching element set and the adjustment switching element control an electrical connection between the control electrode of the driving switching element and the initialization voltage terminal (see Park paragraph 0065 where pixel circuit 100 may have a structure in which the first initialization transistor IT1 and the second initialization transistor IT2 are connected in series between the gate terminal of the driving transistor DT (i.e., the first node N1) and an initialization voltage line transferring the initialization voltage VINT, where one terminal of the first initialization transistor IT1 is connected to the gate terminal of the driving transistor DT and one terminal of the second initialization transistor IT2 is connected to the initialization voltage line transferring the initialization voltage VINT), and
a light emitting element initialization switching element configured to initialize an anode electrode of the light emitting element at an initialization voltage (see Park figure 2, element BT)
Park is silent regarding wherein a control electrode of the adjustment switching element is electrically connected to an input electrode of the adjustment switching element; and a light emitting element initialization switching element configured to initialize an anode electrode of the light emitting element at an initialization voltage that equals a sum of a threshold voltage of the light emitting element and a second power voltage applied to a cathode electrode of the light emitting element.
In the same field of endeavor, Kobayashi teaches a control electrode of the adjustment switching element is electrically connected to an input electrode of the adjustment switching element (see Kobayashi figure 4A, element M18 corresponding to Park’s IT2); and a light emitting element initialization switching element (see Kobayashi figure 4A, element M17 corresponding to Park’s BT) configured to initialize an anode electrode of the light emitting element at an initialization voltage that equals a sum of a threshold voltage of the light emitting element and a second power voltage applied to a cathode electrode of the light emitting element (see Kobayashi figure 4A where cathode voltage = -4V; voltage applied by M17 at anode = -5; since an OLED can only conduct current from its anode to its cathode when the anode voltage is more positive than the cathode voltage (VA > VC) by at least its threshold forward voltage drop, the voltage potential across the OLED is calculated as Voled= -5-(-4)= -1 as indicated in Kobayashi’s figure 4A) so as to initialize an OLED prior to turning on an OLED to suppress both the bright spots and the black floating using known techniques with predictable results.
Consider claim 2, Park as modified by Kobashi teaches all the limitations of claim 1 and further teaches further comprising: a writing switching element configured to provide a data voltage to an input electrode of the driving switching element (see Park figure 2, element ST, DT, DS and paragraph 0055 where switching transistor ST may include a gate terminal that receives a first gate signal GW1, a first terminal that is connected to the data line that transfers a data signal DS in response to the gate signal causing the switching transistor ST to turn on, and a second terminal that is connected to the second node N2 corresponding to input electrode of DT).
Consider claim 3, Park as modified by Kobashi teaches all the limitations of claim 2 and further teaches wherein a timing of an active period of a first gate signal provided to a control electrode of the data initialization switching element set (see Park figure 2, element IT1, GI1), a timing of an active period of a second gate signal provided to a control electrode of the writing switching element (see Park figure 2, element ST, GW1), and a timing of an active period of a third gate signal provided to a control electrode of the light emitting element initialization switching element (see Park figure 2, element BT, BI) are different from one another (see Park figures 8-11 where for example figure 8 illustrates GI1 and GW1 as having different active on timing and paragraph 0058 indicates that BI may be the same as the second initialization signal GI2 that controls the second initialization transistor IT2 which is illustrated in figure 8 as having a different active timing from both GI1 and GW1).
Consider claim 4, Park as modified by Kobashi teaches all the limitations of claim 2 and further teaches wherein a timing of an active period of a first gate signal provided to a control electrode of the data initialization switching element set (see Park figure 2, element IT1, GI1) is different (see Park figure 8 where GI1 and GW1 are active at different times) from a timing of an active period of a second gate signal provided to a control electrode of the writing switching element (see Park figure 2, element ST, GW1), and
wherein the active period of the second gate signal (see Park figure 2, element ST, GW1) coincides (see Park paragraph 0058 where bypass signal BI that controls the bypass transistor BT may be the same as the first initialization signal GI1 that controls the first initialization transistor IT1 and paragraph 0061 where According to some example embodiments, the first initialization signal GI1 and the second initialization signal GI2 may be replaced by the first gate signal GW1 and/or the second gate signal GW2) with an active period of a third gate signal provided to a control electrode of the light emitting element initialization switching element (see Park figure 2, element BT, BI).
Consider claim 5, Park as modified by Kobashi teaches all the limitations of claim 2 and further teaches wherein a timing of an active period of a first gate signal provided to a control electrode of the data initialization switching element set (see Park figure 2, element IT1, GI1) is different (see Park figure 8 where GI1 and GW1 are active at different times) from a timing of an active period of a second gate signal provided to a control electrode of the writing switching element (see Park figure 2, element ST, GW1), and
wherein the active period of the first gate signal (see Park figure 2, element IT1, GI1) coincides (see Park paragraph 0058 where bypass signal BI that controls the bypass transistor BT may be the same as the first initialization signal GI1 that controls the first initialization transistor IT1) with an active period of a third gate signal provided to a control electrode of the light emitting element initialization switching element (see Park figure 2, element BT, BI).
Consider claim 8, Park as modified by Kobashi teaches all the limitations of claim 1 and further teaches further comprising: a first node electrically connected to the control electrode of the driving switching element (see Park figure 2, N1, DT);
a second node electrically connected to an input electrode of the driving switching element (see Park figure 2, element N2, DT);
a third node electrically connected to an output electrode of the driving switching element (see Park figure 2, element N3, DT);
a writing switching element including a control electrode configured to receive a data write gate signal, an input electrode configured to receive a data voltage, and an output electrode electrically connected to the second node (see Park figure 2, element ST, GW1, DS, N2);
a first intermediary switching element including a control electrode configured to receive a first instance of an adjustment gate signal, an input electrode electrically connected to the first node, and an output electrode electrically connected to a first floating node (see Park figure 2, element CT1, GW1, N1, N4);
a second intermediary switching element including a control electrode configured to receive a second instance of the adjustment gate signal, an input electrode electrically connected to the first floating node, and an output electrode electrically connected to the third node (see Park figure 2, element CT2, GW2, N4, N3);
a first emission control switching element including a control electrode configured to receive a first instance of an emission signal, an input electrode configured to receive a first power voltage, and an output electrode electrically connected to the second node (see Park figure 2, element ET1, EM1, ELVDD, N2);
a second emission control switching element including a control electrode configured to receive a second instance of the emission signal, an input electrode electrically connected to the third node, and an output electrode connected to the anode electrode of the light emitting element (see Park figure 2, element ET2, EM2, N3, node between BT and OLED);
the light emitting element initialization switching element including a control electrode configured to receive a light emitting element initialization gate signal, an input electrode connected to the initialization voltage terminal, and an output electrode electrically connected to the anode electrode of the light emitting element (see Park figure 2, element BT, BI, VINT, node between BT and OLED); and
a fourth node (see Park figure 2, element N5),
wherein the cathode electrode of the light emitting element is configured to receive the second power voltage (see Park figure 2, element OLED, ELVSS),
wherein the data initialization switching element set includes a control electrode configured to receive a data initialization gate signal, an input electrode electrically connected to the fourth node, and an output electrode electrically connected to the first node (see Park figure 2, element IT1, GI1, N5, N1),
wherein the input electrode of the adjustment switching element is electrically connected to the initialization voltage terminal (see Park figure 2, element IT2, VINT), and
wherein an output electrode of the adjustment switching element is electrically connected to the fourth node (see Park figure 2, element IT2, N5).
Consider claim 9, Park as modified by Kobashi teaches all the limitations of claim 1 and further teaches further comprising: a first node electrically connected to the control electrode of the driving switching element (see Park figure 2, N1, DT);
a second node electrically connected to an input electrode of the driving switching element (see Park figure 2, element N2, DT);
a third node electrically connected to an output electrode of the driving switching element (see Park figure 2, element N3, DT);
a writing switching element including a control electrode configured to receive a data write gate signal, an input electrode configured to receive a data voltage, and an output electrode electrically connected to the second node (see Park figure 2, element ST, GW1, DS, N2);
an intermediary pixel switching element including a control electrode configured to receive an adjustment gate signal, an input electrode electrically connected to the first node, and an output electrode electrically connected to the third node (see Park figure 13, element CT, GW, N1, N3);
a first emission control switching element including a control electrode configured to receive a first instance of an emission signal, an input electrode configured to receive a first power voltage, and an output electrode electrically connected to the second node (see Park figure 2, element ET1, EM1, ELVDD, N2);
a second emission control switching element including a control electrode configured to receive a second instance of the emission signal, an input electrode electrically connected to the third node, and an output electrode connected to the anode electrode of the light emitting element (see Park figure 2, element ET2, EM2, N3, node between BT and OLED);
the light emitting element initialization switching element including a control electrode configured to receive a light emitting element initialization gate signal, an input electrode connected to the initialization voltage terminal, and an output electrode electrically connected to the anode electrode of the light emitting element (see Park figure 2, element BT, BI, VINT, node between BT and OLED); and
a fourth node (see Park figure 2, element N5),
wherein the cathode electrode of the light emitting element is configured to receive the second power voltage (see Park figure 2, element OLED, ELVSS),
wherein the data initialization switching element set includes a control electrode configured to receive a data initialization gate signal, an input electrode electrically connected to the fourth node, and an output electrode electrically connected to the first node (see Park figure 2, element IT1, GI1, N5, N1),
wherein the input electrode of the adjustment switching element is electrically connected to the initialization voltage terminal (see Park figure 2, element IT2, VINT), and
wherein an output electrode of the adjustment switching element is electrically connected to the fourth node (see Park figure 2, element IT2, N5).
Consider claim 10, Park as modified by Kobashi teaches all the limitations of claim 9. Park is silent regarding wherein at least one of the intermediary pixel switching element, the data initialization switching element set, and the light emitting element initialization switching element is an N-type transistor.
Kobayashi teaches a pixel circuit including an N-channel transistor may also be used instead of the pixel circuit including the P-channel transistor (see Kobayashi paragraph 0039 where A pixel circuit including an N-channel transistor may also be used instead of the pixel circuit 15 including the P-channel transistor. In a case of configuring the pixel circuit using the N-channel transistor, the polarity of the signal and the power supply voltage supplied to the pixel circuit may be reversed).
One of ordinary skill would have been motivated to have modified Park to have at least one of any transistor of a pixel circuit as an N-type transistor as a functional equivalent transistor as disclosed by Kobashi.
Consider claim 17, Park teaches a display apparatus comprising: a display panel including a pixel (see Park figure 15, element 500, 510, 511);
a gate driver configured to output a gate signal to the pixel (see Park figure 15, element 520 and paragraph 0093 where display panel driving circuit 520 may include a first gate signal generating circuit, a second gate signal generating circuit, a first initialization signal generating circuit, a second initialization signal generating circuit, a data signal generating circuit, an emission control signal generating circuit, a bypass signal generating circuit, a timing control circuit, etc. The first gate signal generating circuit may generate the first gate signal GW1 having the driving frequency of N Hz. The second gate signal generating circuit may generate the second gate signal GW2 having the driving frequency of M Hz. The first initialization signal generating circuit may generate the first initialization signal GI1 having the driving frequency of N Hz. The second initialization signal generating circuit may generate the second initialization signal GI2 having the driving frequency of M Hz. The data signal generating circuit may generate the data signal DS. The emission control signal generating circuit may generate the first emission control signal EM1 and the second emission control signal EM2.);
a data driver configured to output a data voltage to the pixel (see Park figure 15, element 520 and paragraph 0093 where display panel driving circuit 520 may include a first gate signal generating circuit, a second gate signal generating circuit, a first initialization signal generating circuit, a second initialization signal generating circuit, a data signal generating circuit, an emission control signal generating circuit, a bypass signal generating circuit, a timing control circuit, etc. The first gate signal generating circuit may generate the first gate signal GW1 having the driving frequency of N Hz. The second gate signal generating circuit may generate the second gate signal GW2 having the driving frequency of M Hz. The first initialization signal generating circuit may generate the first initialization signal GI1 having the driving frequency of N Hz. The second initialization signal generating circuit may generate the second initialization signal GI2 having the driving frequency of M Hz. The data signal generating circuit may generate the data signal DS. The emission control signal generating circuit may generate the first emission control signal EM1 and the second emission control signal EM2.); and
an emission driver configured to output an emission signal to the pixel (see Park figure 15, element 520 and paragraph 0093 where display panel driving circuit 520 may include a first gate signal generating circuit, a second gate signal generating circuit, a first initialization signal generating circuit, a second initialization signal generating circuit, a data signal generating circuit, an emission control signal generating circuit, a bypass signal generating circuit, a timing control circuit, etc. The first gate signal generating circuit may generate the first gate signal GW1 having the driving frequency of N Hz. The second gate signal generating circuit may generate the second gate signal GW2 having the driving frequency of M Hz. The first initialization signal generating circuit may generate the first initialization signal GI1 having the driving frequency of N Hz. The second initialization signal generating circuit may generate the second initialization signal GI2 having the driving frequency of M Hz. The data signal generating circuit may generate the data signal DS. The emission control signal generating circuit may generate the first emission control signal EM1 and the second emission control signal EM2.),
wherein the pixel comprises: a light emitting element (see Park figure 2, element OLED);
a driving switching element configured to provide a driving current to the light emitting element (see Park figure 2, element DT);
an initialization voltage terminal (see Park figure 2, element VINT);
a data initialization switching element set (see Park figure 2, element IT1);
an adjustment switching element electrically connected to the data initialization switching element in series (see Park figure 2, element IT2),
wherein the data initialization switching element set and the adjustment switching element control an electrical connection between the control electrode of the driving switching element and the initialization voltage terminal (see Park paragraph 0065 where pixel circuit 100 may have a structure in which the first initialization transistor IT1 and the second initialization transistor IT2 are connected in series between the gate terminal of the driving transistor DT (i.e., the first node N1) and an initialization voltage line transferring the initialization voltage VINT, where one terminal of the first initialization transistor IT1 is connected to the gate terminal of the driving transistor DT and one terminal of the second initialization transistor IT2 is connected to the initialization voltage line transferring the initialization voltage VINT), and
a light emitting element initialization switching element configured to initialize an anode electrode of the light emitting element at an initialization voltage (see Park figure 2, element BT)
Park is silent regarding wherein a control electrode of the adjustment switching element is electrically connected to an input electrode of the adjustment switching element; and a light emitting element initialization switching element configured to initialize an anode electrode of the light emitting element at an initialization voltage that equals a sum of a threshold voltage of the light emitting element and a second power voltage applied to a cathode electrode of the light emitting element.
In the same field of endeavor, Kobayashi teaches a control electrode of the adjustment switching element is electrically connected to an input electrode of the adjustment switching element (see Kobayashi figure 4A, element M18 corresponding to Park’s IT2); and a light emitting element initialization switching element (see Kobayashi figure 4A, element M17 corresponding to Park’s BT) configured to initialize an anode electrode of the light emitting element at an initialization voltage that equals a sum of a threshold voltage of the light emitting element and a second power voltage applied to a cathode electrode of the light emitting element (see Kobayashi figure 4A where cathode voltage = -4V; voltage applied by M17 at anode = -5; since an OLED can only conduct current from its anode to its cathode when the anode voltage is more positive than the cathode voltage (VA > VC) by at least its threshold forward voltage drop, the voltage potential across the OLED is calculated as Voled= -5-(-4)= -1 as indicated in Kobayashi’s figure 4A) so as to initialize an OLED prior to turning on an OLED to suppress both the bright spots and the black floating using known techniques with predictable results.
One of ordinary skill would have been motivated to have modified Park with the teachings of Kobashi so as to initialize an OLED prior to turning on an OLED to suppress both the bright spots and the black floating using known techniques with predictable results.
Consider claim 18, Park as modified by Kobashi teaches all the limitations of claim 17 and further teaches wherein the data initialization switching element set (see Park figure 2, element IT1) controls an electrical connection between the control electrode of the driving switching element (see Park figure 2, element N1, DT) and an output electrode of the adjustment switching element (see Park figure 2, element IT2), and
wherein the adjustment switching element controls an electrical connection between an input electrode of the data initialization switching element set and the initialization voltage terminal (see Park figure 2, element IT2, N5, IT1, VINT).
Claim(s) 6-7, 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park et al, U.S. Patent Publication No. 20210049959 and Kobashi U.S. Patent Publication No. 20200410933 in view of Chai et al, U.S. Patent Publication No. 20180158407.
Consider claim 6, Park as modified by Kobashi teaches all the limitations of claim 1 and further teaches further comprising: a first node electrically connected to the control electrode of the driving switching element (see Park figure 2, N1, DT);
a second node electrically connected to an input electrode of the driving switching element (see Park figure 2, element N2, DT);
a third node electrically connected to an output electrode of the driving switching element (see Park figure 2, element N3, DT);
a writing switching element including a control electrode configured to receive a data write gate signal, an input electrode configured to receive a data voltage, and an output electrode electrically connected to the second node (see Park figure 2, element ST, GW1, DS, N2);
a first intermediary switching element including a control electrode configured to receive a first instance of an adjustment gate signal, an input electrode electrically connected to the first node, and an output electrode electrically connected to a first floating node (see Park figure 2, element CT1, GW1, N1, N4);
a second intermediary switching element including a control electrode configured to receive a second instance of the adjustment gate signal, an input electrode electrically connected to the first floating node, and an output electrode electrically connected to the third node (see Park figure 2, element CT2, GW2, N4, N3);
a first emission control switching element including a control electrode configured to receive a first instance of an emission signal, an input electrode configured to receive a first power voltage, and an output electrode electrically connected to the second node (see Park figure 2, element ET1, EM1, ELVDD, N2);
a second emission control switching element including a control electrode configured to receive a second instance of the emission signal, an input electrode electrically connected to the third node, and an output electrode connected to the anode electrode of the light emitting element (see Park figure 2, element ET2, EM2, N3, node between BT and OLED);
the light emitting element initialization switching element including a control electrode configured to receive a light emitting element initialization gate signal, an input electrode connected to the initialization voltage terminal, and an output electrode electrically connected to the anode electrode of the light emitting element (see Park figure 2, element BT, BI, VINT, node between BT and OLED); and
a fourth node (see Park figure 2, element N5),
wherein the cathode electrode of the light emitting element is configured to receive the second power voltage (see Park figure 2, element OLED, ELVSS),
wherein the data initialization switching element set includes a first data initialization switching element (see Park figure 2, element IT1)
wherein the first data initialization switching element includes a control electrode configured to receive a first instance of a data initialization gate signal,
wherein the input electrode of the adjustment switching element is electrically connected to the initialization voltage terminal, and wherein an output electrode of the adjustment switching element is electrically connected to the fourth node (see Park figure 2, element IT2, VINT, N5).
Park is silent regarding a second data initialization switching element.
In a related field of endeavor, Chai teaches a transistor on a current path between a second node and a first power source Vint so as to stabilize operation (see Chai figures 11A-11B, element MS2, M4, S2I, VC and paragraph 0138).
One of ordinary skill would have been motivated to have further modified Park with the teachings of Chai to incorporate a transistor on a current path between a node and a first power source Vint so as to stabilize operation resulting in wherein the data initialization switching element set includes a first data initialization switching element (see Park figure 2, element IT1) and a second data initialization switching element (see Chai figure 11A, element MS2),
wherein the first data initialization switching element includes a control electrode configured to receive a first instance of a data initialization gate signal, an input electrode electrically connected to a second floating node (see Chai figure 11A, node between M4, MS2 where M4 corresponds to Park’s IT1), and an output electrode electrically connected to the first node (see Park figure 2, element IT1, GI1, N1),
wherein the second data initialization switching element includes a control electrode configured to receive a second instance of the data initialization gate signal, an input electrode electrically connected to the fourth node, and an output electrode connected to the second floating node (see Chai figure 11A, element MS2, S2i, node between MS2, M4).
Consider claim 7, Park as modified by Kobashi and Chai teaches all the limitations of claim 6 and further teaches further comprising: a storage capacitor including a first electrode configured to receive the first power voltage and a second electrode electrically connected to the first node (see Park figure 2, element CST, ELVDD, N1).
Consider claim 19, Park as modified by Kobashi teaches all the limitations of claim 18 and further teaches wherein the data initialization switching element set includes a first data initialization switching element (see Park figure 2, element IT1, GI1, N1)
Park is silent regarding a second data initialization switching element.
In a related field of endeavor, Chai teaches a transistor on a current path between a second node and a first power source Vint so as to stabilize operation (see Chai figures 11A-11B, element MS2, M4, S2I, VC and paragraph 0138).
One of ordinary skill would have been motivated to have further modified Park with the teachings of Chai to incorporate a transistor on a current path between a node and a first power source Vint so as to stabilize operation resulting in the data initialization switching element set includes a first data initialization switching element (see Park figure 2, element IT1, GI1, N1) and a second data initialization switching element that are electrically connected to each other in series (see Chai figures 11A-11B, element MS2, M4, S2I, VC and paragraph 0138 where M4 corresponds to Park’s IT1).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Jang et al, U.S. Patent Publication No. 20210201827 (figure 13), Choi, U.S. Patent Publication No. 20170110049 (figure 10).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Dorothy H Harris whose telephone number is (571)270-7539. The examiner can normally be reached Monday - Friday 8am - 4pm.
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/Dorothy Harris/Primary Examiner, Art Unit 2625
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