DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1, 4, 11, 14, 18, and 19 have been amended.
Claims 1-20 have been examined.
The specification and drawing objections in the previous Office Action have been addressed and are withdrawn.
The double patenting rejections in the previous Office Action are maintained.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-4, 6, 7, 11-15, 18, and 19 are rejected on the ground of nonstatutory double patenting as being unpatentable over corresponding claims of US Patent 12,147,836 (reference patent), granted from Application No. 17/520,281 in view of US Publication 2022/0083500 by Tsai et al. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of the reference patent include all of the claimed features but for the dot product limitation. However, as evidenced by Tsai (as discussed below) it is well known to perform dot product operations using circuitry such as that claimed.
claims 1, 11, and 18 of the instant application are rendered obvious by claim 1 of the reference patent in view of Tsai;
claims 2 and 12 of the instant application are rendered obvious by claim 4 of the reference patent in view of Tsai;
claims 3 and 13 of the instant application are rendered obvious by claim 1 of the reference patent in view of Tsai;
claim 4, 14, and 19 of the instant application are rendered obvious by claim 7 of the reference patent in view of Tsai;
claim 6 of the instant application is rendered obvious by claim 10 of the reference patent in view of Tsai; and
claims 7 and 15 of the instant application are rendered obvious by claim 9 of the reference patent in view of Tsai.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 1 recites “the processing element group.” There is insufficient antecedent basis for this limitation in the claim. Claims 5 and 6 include similar language and are similarly rejected.
Claims 2-10 are rejected as depending from rejected base claims and failing to cure the indefiniteness of those base claims.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over US Publication No. 2019/0303103 by Hah et al. (hereinafter referred to as “Hah”) in view of US Publication No. 2020/0134417 by Mohapatra et al. (hereinafter referred to as “Mohapatra”) in view of US Publication No. 2022/0083500 by Tsai et al. (hereinafter referred to as “Tsai”).
Regarding claims 1 and 11, taking claim 1 as representative, Hah discloses:
an apparatus comprising: a plurality of processing elements (Hah discloses, at Figure 2 and related description, an array of logic array blocks, which discloses a plurality of processing elements.);
a plurality of levels of accumulation elements, the plurality of levels comprising: a first level comprising accumulation elements and storage elements, each accumulation element in the first level coupled with a respective storage element in the first level and two or more …[inputs] (Hah discloses, at Figure 11 and related description, an adder tree with registers at each stage, which discloses an apparatus with a plurality of levels of accumulation elements, the plurality of levels comprising: a first level comprising accumulation elements and storage elements, each accumulation element in the first level coupled with a respective storage element in the first level and two or more …[inputs].); and
a second level comprising one or more accumulation elements and one or more second storage elements, each accumulation element in the second level coupled with a respective storage element in the second level and two or more accumulation elements in the first level (Hah discloses, at Figure 11 and related description, an adder tree with registers at each stage, which discloses a second level comprising one or more accumulation elements and one or more second storage elements, each accumulation element in the second level coupled with a respective storage element in the second level and two or more accumulation elements in the first level.),
wherein a level is selected from the plurality of levels… and wherein a final output of the apparatus is read from a storage element in the selected level (Hah discloses, at Figure 11 and related description, an adder tree that produces a usable output at each level, which discloses wherein a level is selected from the plurality of levels… and a storage element in the selected level stores an output of the apparatus, which discloses a final output.).
Hah does not explicitly disclose the aforementioned accumulation element is coupled to processing elements of the plurality of processing elements, the aforementioned selection is based on a factor indicating a distribution of input channels of a neural network operation to one or more processing elements in the processing element group, and wherein the aforementioned final output is a dot product of a plurality of matrices.
However, in the same field of endeavor (e.g., processing) Mohapatra discloses:
processing elements in a processing element group (Mohapatra discloses, at Figure 1 and related description, groups of processing elements (PEs).); and
a factor indicating a distribution of input channels of a neural network operation to one or more processing elements in the processing element group (Mohapatra discloses, at ¶ [0042], a partitioning factor that indicates which PEs work on with inputs.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Hah to include the PEs and partitioning disclosed by Mohapatra in order to facilitate improved flexibility and efficiency by supporting runtime reconfigurability. See Mohapatra, ¶ [0023].
Also, in the same field of endeavor (e.g., processing) Tsai discloses:
dot products of matrices (Tsai discloses, at Figure 4A and related description, producing a dot product.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Hah to include producing dot products, as disclosed by Tsai, because dot products are ubiquitously used in neural networks, which are themselves becoming more and more common.
Regarding claims 2 and 12, taking claim 1 as representative, Hah, as modified, discloses the elements of claim 1, as discussed above. Hah does not explicitly disclose the factor indicates a number of processing elements used for performing the neural network operation.
However, in the same field of endeavor (e.g., processing) Mohapatra discloses:
the factor indicates a number of processing elements used for performing the neural network operation (Mohapatra discloses, at ¶ [0042], a partitioning factor that indicates which PEs work on with inputs.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Hah to include the PEs and partitioning disclosed by Mohapatra in order to facilitate improved efficiency. See Mohapatra, ¶ [0023].
Regarding claims 3 and 13, taking claim 3 as representative, Hah, as modified, discloses the elements of claim 1, as discussed above. Hah also discloses:
a storage element in the first level or second level is a register (Hah discloses, at Figure 11 and related description, an adder tree with registers at each stage, which discloses a storage element in the first level or second level is a register.).
Regarding claims 4 and 14, taking claim 4 as representative, Hah, as modified, discloses the elements of claim 1, as discussed above. Hah also discloses:
the apparatus is …configured to extract the final output of the apparatus from the storage element in the selected level (Hah discloses, at Figure 11 and related description, an adder tree that produces a usable output at each level, which discloses the apparatus is …configured to extract the output of the apparatus from the storage element in the selected level.).
Hah does not explicitly disclose the aforementioned apparatus is coupled with a finite state machine.
However, in the same field of endeavor (e.g., processing) Mohapatra discloses:
a finite state machine (Mohapatra discloses, at Figure 1 and related description, a finite state machine (FSM) that controls operations.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Hah to include the FSM disclosed by Mohapatra because FSMs provide clear and predictable execution flow.
Regarding claim 5, Hah, as modified, discloses the elements of claim 1, as discussed above. Hah does not explicitly disclose processing elements in the processing element group are arranged in an array comprising one or more rows or one or more columns.
However, in the same field of endeavor (e.g., processing) Mohapatra discloses:
processing elements in the processing element group are arranged in an array comprising one or more rows or one or more columns (Mohapatra discloses, at Figure 1 and related description, an array of PEs, which discloses processing elements in the processing element group are arranged in an array comprising one or more rows or one or more columns.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Hah to include the array arrangement disclosed by Mohapatra because arrays provide simple organization and utilization of circuit resources.
Regarding claim 6, Hah, as modified, discloses the elements of claim 1, as discussed above. Hah does not explicitly disclose a processing element in the processing element group is configured to perform a multiply-accumulate operation in the neural network operation.
However, in the same field of endeavor (e.g., processing) Mohapatra discloses:
a processing element in the processing element group is configured to perform a multiply-accumulate operation in the neural network operation (Mohapatra discloses, at Figure 1 and related description, PEs include MAC units, which discloses a processing element in the processing element group is configured to perform a multiply-accumulate operation in the neural network operation.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Hah to include the MAC units disclosed by Mohapatra because MAC operations are efficient calculations for neural networking tasks.
Regarding claims 7, 15, and 18, taking claim 7 as representative, Hah, as modified, discloses the elements of claim 1, as discussed above. Hah does not explicitly disclose the apparatus is coupled with a post processing engine for performing a computation on the output of the apparatus to compute an output of the neural network operation.
However, in the same field of endeavor (e.g., processing) Mohapatra discloses:
a post processing engine for performing a computation on the output of the apparatus to compute an output of the neural network operation (Mohapatra discloses, at ¶ [0042], performing pruning, truncation, ReLU, and the like, which discloses a post processing engine for performing a computation on the output of the apparatus to compute an output of the neural network operation.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Hah to include the post processing engine disclosed by Mohapatra in order to improve performance when performing neural network operations.
Regarding claims 8 and 16, taking claim 8 as representative, Hah, as modified, discloses the elements of claim 1, as discussed above. Hah also discloses:
an accumulation element in the first level or second level comprises a first adder for accumulating data elements of a first data precision and a second adder… (Hah discloses, at Figure 11 and related description, an adder tree, which discloses an accumulation element in the first level or second level comprises a first adder for accumulating data elements of a first data precision and a second adder.).
Hah does not explicitly disclose the aforementioned level accumulating data elements of a second data precision, and the second data precision is different from the first data precision.
However, Hah discloses, e.g., at ¶ [0044] et seq., operating on inputs having different precision. It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention include multiple precisions in a given level to improve performance by allowing increased flexibility.
Regarding claims 9 and 17, taking claim 1 as representative, Hah, as modified, discloses the elements of claim 1, as discussed above. Hah also discloses:
an accumulation element in the first level or second level comprises (Hah discloses, at Figure 11 and related description, an adder tree, which discloses an accumulation element in the first level or second level.).
Hah does not explicitly disclose a first comparator configured for a first data precision and a second comparator configured for a second data precision, and the second data precision is different from the first data precision.
However, Hah discloses, e.g., at ¶ [0044] et seq., operating on inputs having different precision. It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention include multiple precisions in a given level to improve performance by allowing increased flexibility.
Also, in the same field of endeavor (e.g., processing) Mohapatra discloses:
comparators for performing comparisons (Mohapatra discloses, at ¶ [0057] et seq., using comparators to perform comparisons.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Hah to include the comparators, as disclosed by Mohapatra, in order improve performance by increasing flexibility by supporting additional computation types for neural networking tasks.
Regarding claim 10, Hah, as modified, discloses the elements of claim 1, as discussed above. Hah also discloses:
the plurality of levels are in a sequence (Hah discloses, at Figure 11 and related description, an adder tree, which discloses the plurality of levels are in a sequence.).
Hah does not explicitly disclose one or more levels subsequent to the selected level are unused for performing the neural network operation.
However, Hah discloses, e.g., at ¶ [0059], circuits may be idle. It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Hah to include idle levels in order to improve performance by allowing flexibility in the processing operations performed.
Regarding claim 19, Hah, as modified, discloses the elements of claim 18, as discussed above. Hah also discloses:
the apparatus is …configured to extract the final output of the apparatus from the storage element in the selected level (Hah discloses, at Figure 11 and related description, an adder tree that produces a usable output at each level, which discloses the apparatus is …configured to extract the output of the apparatus from the storage element in the selected level.).
Hah does not explicitly disclose the aforementioned apparatus is coupled with a finite state machine.
However, in the same field of endeavor (e.g., processing) Mohapatra discloses:
a finite state machine (Mohapatra discloses, at Figure 1 and related description, a finite state machine (FSM) that controls operations.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Hah to include the FSM disclosed by Mohapatra because FSMs provide clear and predictable execution flow.
Regarding claim 20, Hah, as modified, discloses the elements of claim 18, as discussed above. Hah also discloses:
an accumulation element in the first level or second level comprises components configured for … data precisions (Hah discloses, at Figure 11 and related description, an adder tree, which discloses an accumulation element in the first level or second level comprises a first adder for accumulating data elements of a first data precision and a second adder.).
Hah does not explicitly disclose the different data precisions.
However, Hah discloses, e.g., at ¶ [0044] et seq., operating on inputs having different precision. It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention include multiple precisions in a given level to improve performance by allowing increased flexibility.
Response to Arguments
On page 9 of the response filed March 16, 2026 (“response”), the Applicant argues, “Claims 1-4, 6, 7, 11-15, 18, and 19 were rejected on the ground of alleged non-statutory obviousness-type double patenting in view of corresponding claims of U.S. Patent No. 12,147,836. Applicant respectfully requests to hold the double-patent rejection in abeyance until the claims are otherwise found to be allowable.”
The request to hold the double patenting rejection in abeyance is improper. MPEP § 804.1(B)(1) states, “A complete response to a nonstatutory double patenting (NSDP) rejection is either a reply by applicant showing that the claims subject to the rejection are patentably distinct from the reference claims, or the filing of a terminal disclaimer in accordance…. Such a response is required even when the nonstatutory double patenting rejection is provisional. As filing a terminal disclaimer, or filing a showing that the claims subject to the rejection are patentably distinct from the reference application’s claims, is necessary for further consideration of the rejection of the claims, such a filing should not be held in abeyance. Only compliance with objections or requirements as to form not necessary for further consideration of the claims may be held in abeyance until allowable subject matter is indicated. Replies with an omission should be treated as provided in MPEP § 714.03. Therefore, an application must not be allowed unless the required compliant terminal disclaimer(s) is/are filed and/or the withdrawal of the nonstatutory double patenting rejection(s) is made of record by the examiner.” In the interest of compact prosecution, the Examiner will consider the Applicant’s reply as adequate, rather than requiring a complete reply at this point.
On pages 9-10 of the response the Applicant argues, “Claim 1 is amended to "a plurality of processing elements; and a plurality of levels of accumulation elements, the plurality of levels comprising: a first level comprising accumulation elements and storage elements, each accumulation element in the first level coupled with a respective storage element in the first level and two or more processing elements of the plurality of processing elements ... wherein a final output of the apparatus is read from a storage element in the selected level, and wherein the final output of the apparatus is a dot product of a plurality of matrices." The combination of the cited references fails to show or render obvious amended claim 1. For instance, the references are silent regarding "wherein a final output of the apparatus is read from a storage element in the selected level, and wherein the final output of the apparatus is a dot product of a plurality of matrices."
These remarks have been fully considered and, in light of the claim amendments presented in the response, are deemed persuasive, in part. Please see above for new grounds of rejection of the amended claims. Tsai discloses computing dot products using circuitry such as that claimed. It would have been obvious to include computing dot products, as disclosed by Tsai, because dot products are fundamental operations in machine learning.
Regarding reading the output from the selected level, the Examiner respectfully disagrees. Reading the output encompasses selecting the level at which the output is read. Accordingly, these arguments are deemed unpersuasive.
Conclusion
The following prior art made of record and not relied upon is considered pertinent to Applicant’s disclosure.
US 20200234099 by Wang discloses a dot product using an adder tree.
US 20220405559 by Abdelaziz discloses a dot product using an adder tree.
US 20200026494 by Langhammer discloses a dot product using an adder tree.
US 20220147826 by Xiao discloses dot products, PEs, an adder tree.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAWN DOMAN whose telephone number is (571)270-5677. The examiner can normally be reached on Monday through Friday 8:30am-6pm Eastern Time.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta can be reached on 571-270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHAWN DOMAN/
Primary Examiner, Art Unit 2183