Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 7 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 7 is rejected under 35 U.S.C. 112(b) as being indefinite because the limitation “the (100) crystallographic plane” lacks proper antecedent basis. Claim 1 recites only “a specified crystallographic plane” and does not identify the specified crystallographic plane as the (100) crystallographic plane.
Claims 8-9 are rejected under 35 U.S.C. 112(b) as being indefinite because they depend from indefinite claim 7.
Although claim 7 is rejected under 35 U.S.C. 112(b), for purposes of examination and compact prosecution, claim 7 is interpreted as requiring the silicon process wafer frontside and backside to be oriented along the (100) crystallographic plane.
Claim Rejections - 35 USC § 103
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 2, 5-7, 12, 13, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. (US 2022/0037192 A1) in view of Moslehi et al. (US 2013/0141833 A1).
Regarding claim 1, Yu teaches providing a first substrate having a planar frontside and a planar backside, the first substrate comprising a crystalline semiconductor material on the planar frontside (substrate 50 is a semiconductor substrate including fins 66 and nanostructures 55 formed thereon; paragraph 0011).
Yu also teaches producing a device layer on the planar frontside of the first substrate, the device layer comprising, in a first area, a plurality of semiconductor devices (nano-FET transistor structures are formed on substrate 50; paragraphs 0011 and 0078).
Yu further teaches producing, in the first area, before producing the device layer, a plurality of cavities from the planar frontside of the first substrate and into the crystalline semiconductor material of the first substrate (trenches are formed in substrate 50 and recessed to form STI regions 68 before later transistor/backside processing; paragraph 0026).
Yu continues to teach at least partially filling the plurality of cavities with a dielectric material (STI regions 68 are formed by recessing insulation material in the trenches; paragraph 0026).
Yu teaches forming an additional dielectric layer over the plurality of semiconductor devices located in the first area (front-side interconnect structure 120 is formed over transistor structures 109 and bonding layers are formed thereon; paragraphs 0075-0076).
Yu also teaches producing an additional layer on top of the device layer, ending with a planar top surface (front-side interconnect structure 120 and bonding layers 182A/182B are provided for bonding to carrier substrate 180; paragraphs 0075-0077).
Yu further teaches bonding the first substrate to a second substrate by bonding the planar top surface to a bonding surface of the second substrate (carrier substrate 180 is bonded to the top surface of front-side interconnect structure 120 using bonding layers 182A and 182B; paragraphs 0075-0077).
Yu teaches subsequent to bonding the first substrate to the second substrate, thinning the first substrate from the planar backside (after carrier substrate 180 is bonded, the device is flipped and a thinning process is applied to the backside of substrate 50; paragraphs 0078-0079).
Yu also teaches thinning the first substrate from the planar backside such that a uniform layer of the crystalline semiconductor material remains above the plurality of cavities (after thinning, a portion of substrate 50 remains over the gate structures and nanostructures, and backside surfaces of substrate 50, STI regions 68, and fins 66 are level with one another; paragraph 0079).
Yu further teaches subjecting the crystalline semiconductor material to an anisotropic etch process (remaining portions of fins 66 and substrate 50 may be etched using an anisotropic etching process; paragraph 0080).
Yu teaches that the anisotropic etch process stops at the dielectric material in at least one of the plurality of cavities and the additional dielectric layer (the etching process is selective to the material of fins 66 and substrate 50 relative to STI regions 68, gate dielectric layers 100, epitaxial source/drain regions 92, and first epitaxial materials 91, thereby exposing surfaces of STI regions 68 and gate dielectric layers 100 after etching; paragraph 0080).
Yu teaches wherein in-plane dimensions of a plurality of regions located between the plurality of cavities and depths of the plurality of cavities are configured such that the anisotropic etch process does not reach the plurality of semiconductor devices (the backside etch removes remaining fins 66 and substrate 50 while being selective to STI regions 68, gate dielectric layers 100, epitaxial source/drain regions 92, and first epitaxial materials 91, thereby exposing these structures without substantially etching them; paragraph 0080).
Yu does not expressly teach that the anisotropic etch process stops at a specified crystallographic plane of the crystalline semiconductor material.
Moslehi teaches an anisotropic silicon etching process, such as KOH or NaOH, used to etch frontside silicon trenches and backside silicon trenches, wherein the trench sidewall tapering has an angle of 54.7 degrees defined by (100) and (111) silicon crystallographic planes, the silicon etching is self-terminated at a buried/underlying silicon dioxide layer, and the trench sidewalls are (111) crystallographic silicon planes (paragraph 0071).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Yu’s backside anisotropic etching process to use Moslehi’s crystallographic-plane-controlled anisotropic silicon etching because Moslehi teaches that such etching forms smooth (111) crystallographic silicon sidewalls and self-terminates at an underlying silicon dioxide layer. Yu similarly removes backside semiconductor material while relying on selectivity to dielectric/isolation structures. Therefore, applying Moslehi’s known anisotropic silicon etching technique to Yu’s backside semiconductor removal process would have predictably provided controlled silicon removal terminating at dielectric/isolation structures and crystallographic silicon planes. See MPEP § 2141, rationale III(D).
Regarding claim 2, the modified method of Yu teaches the limitations of claim 1 above. Yu further teaches after the anisotropic etch process, depositing a further dielectric material on a thinned backside of the first substrate and planarizing the further dielectric material and remaining portions of the crystalline semiconductor material to a common planarized surface (second dielectric layer 125 is deposited on the backside in recesses formed by removing fins 66 and substrate 50, and CMP is used so that top surfaces of second dielectric layer 125 are level with top surfaces of STI regions 68 and first epitaxial materials 91; paragraph 0081).
Regarding claim 5, the modified method of Yu teaches the limitations of claim 1 above. Yu further teaches wherein the plurality of cavities in the first area define shallow trench isolation (STI) regions (STI regions 68 are disposed between adjacent fins 66 and are formed from recessed insulation material in trenches; paragraphs 0011 and 0026).
Regarding claim 6, the modified method of Yu teaches the limitations of claim 1 above. Yu further teaches wherein the crystalline semiconductor material is a crystalline silicon (substrate 50 may be a wafer, such as a silicon wafer, and the semiconductor material of substrate 50 may include silicon; paragraph 0016).
Regarding claim 7, the modified method of Yu in view of Moslehi teaches the limitations of claim 6 above. Yu teaches the first substrate is a silicon process wafer (substrate 50 may be a wafer, such as a silicon wafer; paragraph 0016).
Yu does not expressly teach the silicon process wafer having the planar frontside and the planar backside oriented along the (100) crystallographic plane of the crystalline silicon. Moslehi teaches anisotropic silicon etching in which sidewall tapering has an angle of 54.7 degrees defined by (100) and (111) silicon crystallographic planes, and the trench sidewalls are (111) crystallographic silicon planes (paragraph 0071).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use a silicon wafer having a (100) crystallographic orientation in the modified method of Yu to obtain the predictable (111)-plane anisotropic etch profile taught by Moslehi.
Regarding claim 12, the modified method of Yu teaches the limitations of claim 1 above. Moslehi further teaches wherein the in-plane dimensions of the plurality of regions located between the plurality of cavities and the depths of the plurality of cavities are configured such that the anisotropic etch process stops on crystallographic planes of the crystalline semiconductor material (anisotropic silicon etching forms trench sidewall tapering at 54.7 degrees defined by (100) and (111) silicon crystallographic planes, and the trench sidewalls are (111) crystallographic silicon planes; paragraph 0071).
Regarding claim 13, the modified method of Yu in view of Moslehi teaches the limitations of claim 1 above. Yu teaches wherein the anisotropic etch process stops on the dielectric material in at least one of the plurality of cavities (the etching process is selective to fins 66 and substrate 50 relative to STI regions 68 and exposes surfaces of STI regions 68 after removing substrate/fins from the backside; paragraph 0080).
To the extent Yu does not expressly teach the anisotropic etch process stops on the dielectric material in at least one of the plurality of cavities based on crystallographic-plane-controlled anisotropic silicon etching,
Moslehi teaches silicon etching self-terminated at a buried/underlying silicon dioxide layer (paragraph 0071).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Moslehi’s self-terminating silicon etch in the modified method of Yu because Yu teaches backside silicon removal selective to STI/dielectric structures, and Moslehi teaches a known anisotropic silicon etch that self-terminates at silicon dioxide. Therefore, the modification would have predictably provided controlled silicon removal stopping at dielectric material.
Regarding claim 20, the modified method of Yu teaches the limitations of claim 1 above. Yu further teaches wherein the first substrate is bonded to the second substrate at a bonding layer comprising SiO2 (carrier substrate 180 is bonded to front-side interconnect structure 120 using bonding layers 182A/182B, and the bonding layers may comprise silicon oxide; paragraphs 0075-0076).
Claims 3, 8-10 are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. in view of Moslehi et al., as applied to claims 1 and 7 above where applicable, and further in view of Hirabayashi (US 5,614,445).
Regarding claim 3, the modified method of Yu in view of Moslehi teaches the limitations of claim 1 above. Modified Yu does not expressly teach further comprising producing a second plurality of cavities in a second area of the first substrate, wherein producing the device layer does not include producing any semiconductor devices in the second area.
Hirabayashi teaches producing a second plurality of cavities in a second area of the first substrate, wherein producing the device layer does not include producing any semiconductor devices in the second area (dummy etched grooves 6 are formed in areas of the wafer not containing elements, such as the scribe line zone; column 6, lines 25-43; dummy etching sections may be formed outside element formation zones; column 6, lines 57-65).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify the method of Yu in view of Moslehi to include Hirabayashi’s dummy etched grooves outside the element formation zones because Hirabayashi teaches that forming dummy etched grooves outside the element formation zones increases the etched area, reduces side etching, and improves etching uniformity without affecting the element formation zones. See MPEP § 2141, rationale III(D).
Regarding claim 8, the modified method of Yu in view of Moslehi teaches the limitations of claim 7 above. Modified Yu does not expressly teach wherein a plurality of scribe lines divides a plurality of die areas of the silicon process wafer.
Hirabayashi teaches wherein a plurality of scribe lines divides a plurality of die areas of a silicon wafer (scribe line zone 5 is arranged in a grid so as to divide the wafer into chips upon which semiconductor devices or integrated circuits are formed; column 5, lines 23-30; semiconductor devices are isolated from one another via scribe line zones 36 used for cleaving/cutting/dividing the silicon wafer; column 1, lines 57-63).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify the method of Yu in view of Moslehi to include Hirabayashi’s grid-arranged scribe line zones because Hirabayashi teaches scribe line zones as known wafer regions used to divide a silicon wafer into chips having semiconductor devices. Therefore, using Hirabayashi’s scribe line arrangement in the modified method would have predictably provided die separation regions on the silicon wafer. See MPEP § 2141, rationale III(D).
Regarding claim 9, the modified method of Yu in view of Moslehi and Hirabayashi teaches the limitations of claim 8 above. Hirabayashi further teaches wherein at least one cavity of the plurality of cavities is formed in one of the plurality of scribe lines between an adjacent pair of the plurality of die areas (dummy etched grooves 6 are formed as microminiature linear grooves in scribe line zone 5, wherein the scribe line zone is arranged in a grid to divide the wafer into chips; column 5, lines 23-40).
Regarding claim 10, the modified method of Yu in view of Moslehi teaches the limitations of claim 1 above. Modified Yu does not expressly teach wherein a plurality of scribe lines divides a plurality of die areas of the first substrate, and at least one cavity of the plurality of cavities is formed in one of the plurality of scribe lines between an adjacent pair of the plurality of die areas.
Hirabayashi teaches wherein a plurality of scribe lines divides a plurality of die areas of the first substrate, and at least one cavity is formed in one of the plurality of scribe lines between adjacent die areas (scribe line zone 5 is arranged in a grid so as to divide the wafer into chips upon which semiconductor devices or integrated circuits are formed, and dummy etched grooves 6 are formed as microminiature linear grooves in the scribe line zone; column 5, lines 23-40).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify the method of Yu in view of Moslehi to include Hirabayashi’s dummy etched grooves in scribe line zones because Hirabayashi teaches forming dummy etched grooves in scribe line zones to improve dry etching uniformity while using existing wafer division regions. Therefore, applying Hirabayashi’s known scribe-line groove arrangement to the modified method would have predictably provided cavities in wafer scribe-line regions between die areas. See MPEP § 2141, rationale III(D).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. in view of Moslehi et al., as applied to claim 1 above, and further in view of Brennan et al. (US 7,214,568 B2).
The modified method of Yu in view of Moslehi teaches the limitations of claim 1 above. Modified Yu does not expressly teach wherein the in-plane dimensions of the plurality of regions located between the plurality of cavities and the depths of the plurality of cavities are configured such that the anisotropic etch process stops when a V-shaped groove is formed in the crystalline semiconductor material of the first substrate.
Brennan teaches forming V-shaped grooves in a semiconductor wafer by anisotropic etching (anisotropic etching is used to form a pattern of V-grooves 404 in separation streets defining die dimensions on the wafer; column 5, lines 36-62). Brennan further teaches that due to the nature of the anisotropic etch, the V-groove angle dimensions can be precisely controlled and are highly repeatable (column 5, lines 15-35).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify the method of Yu in view of Moslehi to configure the anisotropic etch to form V-shaped grooves, as taught by Brennan, because Brennan teaches that anisotropic etching provides precisely controlled and repeatable V-groove geometry in a semiconductor wafer. Therefore, applying Brennan’s known V-groove anisotropic etching technique to the modified method of Yu would have predictably provided controlled groove formation during semiconductor substrate etching. See MPEP § 2141, rationale III(D).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. in view of Moslehi et al., as applied to claim 1 above, and further in view of Huang et al. (US 2021/0407999 A1).
The modified method of Yu in view of Moslehi teaches the limitations of claim 1 above. Modified Yu does not expressly teach wherein the in-plane dimensions of the plurality of regions located between the plurality of cavities and the depths of the plurality of cavities are configured such that the anisotropic etch process stops on the additional dielectric layer.
Huang teaches backside removal/etching of semiconductor material stopping on an intervening dielectric layer (exposure of the intervening layer is detected during backside removal, and the removal process may be selective to the carrier layer relative to the intervening layer; paragraphs [0073]-[0076]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify the method of Yu in view of Moslehi so that the backside semiconductor etch stops on an additional dielectric/intervening layer, as taught by Huang, because Huang teaches using an intervening layer as a detectable/selective stop during backside semiconductor removal. Therefore, applying Huang’s known backside stop-layer arrangement to the modified method of Yu would have predictably provided controlled backside semiconductor removal terminating on a dielectric layer. See MPEP § 2141, rationale III(D).
Claims 15, 18, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. (US 2022/0037192 A1) in view of Moslehi et al. (US 2013/0141833 A1), as applied to claim 2 above, and further in view of Yu et al. (US 2022/0336287 A1, hereinafter “Yu ’287”).
Regarding claim 15, the modified method of Yu in view of Moslehi teaches the limitations of claim 2 above. Modified Yu does not expressly teach wherein the further dielectric material is deposited after the plurality of cavities are filled at least partially with the dielectric material, to form a second layer of dielectric material.
Yu ’287 teaches forming STI features by filling trenches with dielectric material (active regions 106 are formed by patterning Si/SiGe films to form trenches, filling the trenches with dielectric material such as silicon oxide, and performing CMP, wherein the dielectric material in the trenches forms STI features 104; paragraph 0018). Yu ’287 further teaches, after backside thinning and etching, depositing dielectric material layer 134 to refill backside trenches and cover the backside, followed by CMP planarization (paragraph 0029; see also paragraphs 0043, 0052, 0062).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify the method of Yu in view of Moslehi to deposit the further dielectric material after the STI/cavity dielectric fill, as taught by Yu ’287, because Yu ’287 teaches a known backside-processing sequence in which STI trenches are first filled with dielectric material and later backside trenches are refilled with dielectric material after backside thinning and etching. Therefore, applying Yu ’287’s known backside dielectric refill sequence to the modified method of Yu would have predictably provided a second dielectric material layer on the backside after the initial cavity/STI dielectric fill. See MPEP § 2141, rationale III(D).
Regarding claim 18, the modified method of Yu in view of Moslehi and Yu ’287 teaches the limitations of claim 15 above. Yu ’287 further teaches wherein an interconnect via and a conductor are produced in the second layer of dielectric material (backside via feature/VB feature 120 is formed landing on source feature 108, and backside metal line 118 is formed landing on VB feature 120 and electrically connected to source feature 108 through VB feature 120; paragraphs 0046 and 0055; see also paragraph 0038).
Regarding claim 19, the modified method of Yu in view of Moslehi and Yu ’287 teaches the limitations of claim 18 above. Yu ’287 further teaches wherein the interconnect via and the conductor are produced in the second layer of dielectric material by a technique comprising at least one of a single or double damascene process (operation to form backside metal line 118 may include a damascene process, wherein a backside ILD layer is formed on the backside of the workpiece, trenches are formed in the backside ILD layer by lithography and etching, conductive material is deposited into the trenches, and CMP is applied to remove excess metal; paragraph 0038).
Claims 16 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. in view of Moslehi et al. and in further view of Yu ’287, as applied to claim 15 above, in further view of Hiblot et al. (EP 3591696 B1).
Regarding claim 16, the modified method of Yu in view of Moslehi and Yu ’287 teaches the limitations of claim 15 above. Modified Yu does not expressly teach wherein the further dielectric material is a pre-metal dielectric (PMD).
Hiblot teaches wherein the further dielectric material is a pre-metal dielectric (PMD) (on top of STI oxide is a further dielectric layer 16 which may be referred to as a pre-metal dielectric (PMD); paragraph 0023).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify the method of Yu in view of Moslehi and Yu ’287 to use Hiblot’s pre-metal dielectric as the further dielectric material because Hiblot teaches PMD as a known dielectric layer formed over STI oxide and below metallization in semiconductor device fabrication. Therefore, using Hiblot’s known PMD dielectric in the modified method would have predictably provided a conventional dielectric layer compatible with subsequent conductor/interconnect formation. See MPEP § 2141, rationale III(D).
Regarding claim 17, the modified method of Yu in view of Moslehi, Yu ’287, and Hiblot teaches the limitations of claim 16 above. Yu ’287 further teaches wherein the further dielectric material is at least one of SiO2 or a low-K material (the backside ILD layer includes one or more dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric material, other suitable dielectric material, or a combination thereof; paragraph 0038).
Allowable Subject Matter
Claim 4 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
As to claim 4, the prior art of record fails to teach or suggest, alone or in combination with other prior art, “wherein a spacing between two adjacent cavities of the second plurality of cavities is configured so that the anisotropic etch process does not reach the planar front side of the first substrate between the two adjacent cavities of the second plurality of cavities,” in combination with the remaining limitations of claims 1 and 3.
Conclusion
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/JONATHAN L CARTER/Examiner, Art Unit 1713
/ERIN F BERGNER/Primary Examiner, Art Unit 1713
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