DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is a NON-FINAL OFFICE ACTION in response to the PRELIMINARY AMENDMENT filed 12/16/2024. Claims 2, 5, 6, and 8-20 are cancelled. Claims 21-28 are new.
Claims 1, 3, 4, 7, and 21-28 are pending in the Application, of which Claims 1, 21, and 25 are independent.
Continuity/priority Information
The present Application 18907092 filed 10/04/2024 is a Continuation of 17095530, filed 11/11/2020, now U.S. Patent No. 12,147,302 and Claims Priority from Provisional Application 62935773, filed 11/15/2019.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 10/04/2024 and 12/12/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the IDS has been considered by the examiner.
Claim Objections
Claims 3, 4, 7 and 25-28 are objected to because of the following informalities:
Claims 3, 4, and 7, line 1, “The graphics multiprocessor” change to “The apparatus” due to lack of antecedent basis.
Claims 25-28, line 1, “computer-readable medium” change to “non-transitory computer-readable storage medium” for compliance with the specification. Appropriate correction is required.
Specification
The disclosure is objected to because of the following informalities:
In the specification, the words “correctible” and “uncorrectible” where applicable, should be changed to “correctable” and “uncorrectable”, because the words according to Merriam-Webster are not in the dictionary. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 3, 4, 22, 23, 26 and 27 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 3, 22, 26, “whether the parity information indicates an error condition or not” is indefinite, because the term “not” describes the normal memory operation and no further action is necessary, thus failing to further narrow the limitation.
Claims 4, 23, 27, “whether the data associated with the parity information is clean based on being modified in cache or a local memory and also modified in main memory when the parity information indicates an error condition” is indefinite. It is not clear how the parity information indicates an error condition based on data modifications in different types of memories. Normally, an error occurs due to bad data in a memory. An error is not related to data being modified.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3, 4, 7, and 21-28 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Somasekhar et al. (Pub. No. US 20110161783).
Regarding independent Claims 1, 21, and 25, Somasekhar discloses an apparatus and method for directly matching coded tags encoded with error correction codes (ECCs), comprising:
processing circuitry to perform a tag read for data to check error detection correction information comprising parity information. [0015] FIG. 1 illustrates an embodiment of a processor including multiple cores. Processor 100, in one embodiment, includes one or more caches capable of directly matching encoded tags--encoded with error correction information--without first decoding error correcting information in a stored, coded tag.
FIG. 3 illustrates a cache memory capable of directly matching incoming tags with stored, coded tags. [0035] Therefore, in one embodiment tag address 308a is encoded with error correction codes 308b to form coded tag 308. Here, an error detection/correction algorithm is utilized to generate check values/bits, which are included in tag entry 308 in some manner, such as being appended to tag address 308a. Examples of common algorithms for generating check values include: a parity algorithm, a checksum algorithm, a cyclic redundancy check (CRC) algorithm, and a hash algorithm.
Regarding Claims 3, 22, 26, Somasekhar discloses whether the parity information indicates an error condition or not. [0046] Turning to FIG. 4, As an example, ECCs include check values/bits that are generated by an algorithm based on the values/bits of tag address 308a. In this example, ECC logic 405, in one embodiment, is capable of detecting k+1 bit errors and correcting k bit errors in tag address 308a.
Regarding Claims 4, 23, 27, Somasekhar discloses wherein if the data associated with the parity information is not clean, a fatal error condition is reported. [0053] Based on the m-bit difference, hit/miss logic 415 is to determine a result from the tag comparison. As discussed above in reference to FIG. 3, different thresholds may be utilized to determine the result, such as a hit, miss, fault, etc. For example, the hit-miss logic is to determine a hit in response to the m-bit difference being less than or equal to a hit threshold.
FIG. 6 [0059] In flow 645, if the m-bit difference is not greater than a miss threshold--2-bits (k+1)--then the only possible m-bit error left is a 2-bit or k+1 bit error. This determination results in a fault or machine check as an “uncorrectable error” corresponding to fatal error condition.
Regarding Claims 7, 24, 28, Somasekhar discloses wherein the cache or the local memory comprises an embedded dynamic random-access memory (DRAM), FIG. 3 illustrates an embodiment of a cache memory capable of directly matching coded tags. Claim 14. wherein the memory is to be selected from a group consisting of a Dynamic Random Access Memory (DRAM), Double Data Rate (DDR) RAM, and a Static Random Access Memory (SRAM).
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1, 3, 4, 7, and 21-28 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No.12,147,302. Although the claims at issue are not identical, they are not patentably distinct from each other because the Claims of the instant Application are broader in scope than the Claims recited in the U.S. Patent No. 12,147,302, and thus anticipate the Claims of the instant Application. Claims of the instant application therefore are not patently distinct from the earlier patent claims and as such are unpatentable over obvious-type double patenting. A later patent/application claim is not patentably distinct from an earlier claim if the later claim is anticipated by the earlier claim.
“A later patent claim is not patentably distinct from an earlier patent claim if the later claim is obvious over, or anticipated by, the earlier claim. In re Longi, 759 F.2d at 896,225 USPQ at 651 (affirming a holding of obviousness-type double patenting because the claims at issue were obvious over claims in four prior art patents); In re Berg, 140 F.3d at 1437, 46 USPQ2d at 1233 (Fed. Cir. 1998) (affirming a holding of bviousness- type double patenting where a patent application claim to a genus is anticipated by a patent claim to a species within that genus).“ ELI LILLY AND COMPANY v BARR LABORATORIES, INC., United States Court of Appeals for the Federal Circuit, ON PETITION FOR REHEARING EN BANC (DECIDED: May 30, 2001.
18907092 Double Patenting Table, Claims comparison
Instant Application Claims
(U.S. Patent No. 12,147,302) Claims
Independent Claims 1, 21, 25,
perform a tag read for data to check error detection correction information comprising parity information.
Independent Claims 1, 9, 13, A graphics multiprocessor, comprising: memory of the graphics multiprocessor for storing data, wherein the memory is cache or local memory; and error detection correction circuitry having error registers and integrated with the memory of the graphics multiprocessor,
the error detection correction circuitry is configured to perform a tag read of the memory to determine whether error detection correction information of error detection and correction logic indicates an error condition or not, and
to report the error condition to the error registers to log a source of a correctable error when a correctable error occurs or to report the error condition to the error registers to report an uncorrectable error when an uncorrectable error occurs, wherein the error detection correction circuitry is located on chip or on die with the graphics multiprocessor.
Claim 2. The graphics multiprocessor of claim 1, wherein the error detection correction information comprises parity information or a single-error-detecting code.
Claims 3, 22, 26, wherein the processing circuitry is further to determine whether the parity information indicates an error condition or not.
Claims 3, 9. The graphics multiprocessor of claim 2, wherein the error detection correction circuitry is further configured to determine whether the parity information or the single-error-detecting code indicates an error condition or not.
Claims 4, 23, 27, wherein the processing circuitry is further to determine whether the data associated with the parity information is clean based on being modified in cache or a local memory and also modified in main memory when the parity information indicates an error condition,
wherein if the data associated with the parity information is not clean, a fatal error condition is reported.
Claims 4, 10. The graphics multiprocessor of claim 3, wherein the error detection correction circuitry is further configured to determine whether data of the cache or shared memory that is associated with the parity information is clean based on being modified in the cache or shared memory and also modified in main memory when the parity information indicates an error condition.
Claim 5, 11. The graphics multiprocessor of claim 4, wherein if the data that is associated with the parity information is not clean, then a fatal error condition is reported.
Claims 7, 24, 28, wherein the cache or the local memory comprises an embedded dynamic
Claim 7. The graphics multiprocessor of claim 1, wherein the cache or local memory comprises an embedded dynamic random access memory (DRAM).
Claim 8. The graphics multiprocessor of claim 1, wherein the memory comprises a first level cache or a second level cache having the error detection correction circuitry that is located on chip or on die with the graphics multiprocessor.
Prior Art References Cited
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See References Cited on PTO-892 form.
SZAPIRO et al. (US 20140189473) see Abstract. A method is described that includes reading a cache tag and the cache tag's corresponding ECC from storage circuitry of a cache. The method also includes generating an ECC for a search tag. The method also includes calculating a hamming distance between a) the cache tag and its corresponding ECC and b) the search tag and its corresponding ECC. The method also includes determining if the cache tag matches the search tag by determining if said hamming distance is two or less.
Jacob (US 20080163008) see Abstract. A cache tag comparison unit in a cache controller evaluates tag data and error correction codes to determine if there is a cache hit or miss. The cache tag comparison unit speculatively compares the tag data with the request tag without regard to error correction. The error correction code verifies whether this initial comparison is correct and provides a confirmed cache hit or miss signal. The tag data is compared with the request tag to determine a provisional cache hit or miss, and in parallel, the error correction code is evaluated.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAMES C KERVEROS whose telephone number is (571)272-3824. The examiner can normally be reached 9-5.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, MARK FEATHERSTONE can be reached at (571) 270-3750. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JAMES C KERVEROS/Primary Examiner, Art Unit 2111
Date: January 12, 2026
Non-Final Rejection 20260109
JAMES C. KERVEROS
Primary Examiner, Art Unit 2111
James.Kerveros@USPTO.GOV