DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is a FINAL OFFICE ACTION in response to the Amendment/ Remarks filed 04/23/2026. Claims 2, 5, 6, and 8-20 are cancelled. Claims 1, 3, 4, 7, and 21-28 are pending in the Application, of which Claims 1, 21, and 25 are independent.
Continuity/priority Information
The present Application 18907092 filed 10/04/2024 is a Continuation of 17095530, filed 11/11/2020, now U.S. Patent No. 12,147,302 and Claims Priority from Provisional Application 62935773, filed 11/15/2019.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 01/30/2026 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the IDS has been considered by the examiner.
Response to Arguments
Applicant’s arguments, see Amendment/ Remarks, filed 04/23/2026, with respect to the rejection(s) of claim(s) 1, 3, 4, 7, and 21-28 under 35 U.S.C. 102(a)(1) as being anticipated by Somasekhar et al. (Pub. No. US 20110161783), have been fully considered and are persuasive. Therefore, the rejection has been withdrawn.
However, upon further consideration, a new ground(s) of rejection is made in view of Moyer et al. (Pub. No. US 20100064206) Pub. Date: 2010-03-11, as set forth in the present office action.
Claims objections for minor informalities and rejections under 35 USC 112b is withdrawn due to Applicant’s amendment to the Claims.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3, 4, 7, and 21-28 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Moyer et al. (Pub. No. US 20100064206).
Regarding independent Claims 1, 21, and 25, Moyer discloses error detection schemes for a cache data in data processing systems, comprising:
processing circuitry coupled to a memory to perform a tag read for data at the memory to check error detection correction information comprising parity information. [0021] FIG. 2 Cache control circuitry 38 “processing circuitry” is coupled to cache circuitry 21 “memory” by way of conductors or signals 36 and 39. Error control circuitry 40 “check error detection correction” is coupled to cache circuitry 21 and output select logic 37. Error control circuitry 66 may also provide one or more error indicators to bus 24. Output select logic is coupled to receive information from cache circuitry 21 and error control circuitry 40, and provides information to bus 24. Cache control circuitry 38 is also coupled to receive information from bus 24.
[0025] Depending on the embodiment, the protection bits may either be check bits for use with an EDC/ECC scheme (multiple bit error detection/correction scheme) or parity bits “parity information” for use with a parity scheme (single bit error detection scheme). Error control circuitry 40 performs the appropriate error detection/correction (EDC/ECC or parity) on the received cache data using the received protection information.
Regarding Claims 3, 22, 26, Moyer discloses whether the parity information indicates an error condition or not. [0025] Error control circuitry 40 performs the appropriate error detection/correction (EDC/ECC or parity) on the received cache data using the received protection information. The cache data can then be provided to bus 24 via output select logic which, using HIT_WAY[0:7] 34, selects the output of the corresponding way which resulted in the cache hit (from, e.g., conductors 39). Also, note that an error indicator can also be provided to bus 24 via output select logic 37 to indicate whether or not an error has occurred “error condition or not”.
Regarding Claims 4, 23, 27, Moyer discloses wherein if the data associated with the parity information is not clean, a fatal error condition is reported. [0012] Note that EDC/ECC algorithms use check bits to detect errors where EDC/ECC is able to detect multiple bit errors in the data being checked, and for ECC, to correct a subset of detected errors. In some embodiments, both EDC and ECC are used in order to both detect and then correct the data being checked. However, in other embodiments, only EDC is used in which multiple bit errors can be detected but are not corrected “uncorrectable” corresponding to “a fatal error condition”.
Regarding Claims 7, 24, 28, Moyer discloses wherein the cache is located on a chip or on a die with the processing circuitry having graphics processing circuitry. [0017] FIG. 1 illustrates a data processing system 10 that includes a data cache 26, an instruction cache 27, a memory 28, and processing logic 30. Processing logic 30 implements data processing operations. In one embodiment, processing logic 30 may be a central processing unit (CPU) of processor 12. Each of data cache 26, instruction cache 27, memory 28, and processing logic 30 are coupled to the internal bus via respective bidirectional conductors. Data cache 26 stores data type information, as described above, and instruction cache 27 stores instruction type information, as described above. Note that memory 28 and memory 16 can be any type of memory, and peripherals 18 and 20 can each be any type of peripheral or device.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1, 3, 4, 7, and 21-28 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No.12,147,302. Although the claims at issue are not identical, they are not patentably distinct from each other because the Claims of the instant Application are broader in scope than the Claims recited in the U.S. Patent No. 12,147,302, and thus anticipate the Claims of the instant Application. Claims of the instant application therefore are not patently distinct from the earlier patent claims and as such are unpatentable over obvious-type double patenting. A later patent/application claim is not patentably distinct from an earlier claim if the later claim is anticipated by the earlier claim.
“A later patent claim is not patentably distinct from an earlier patent claim if the later claim is obvious over, or anticipated by, the earlier claim. In re Longi, 759 F.2d at 896,225 USPQ at 651 (affirming a holding of obviousness-type double patenting because the claims at issue were obvious over claims in four prior art patents); In re Berg, 140 F.3d at 1437, 46 USPQ2d at 1233 (Fed. Cir. 1998) (affirming a holding of bviousness- type double patenting where a patent application claim to a genus is anticipated by a patent claim to a species within that genus).“ ELI LILLY AND COMPANY v BARR LABORATORIES, INC., United States Court of Appeals for the Federal Circuit, ON PETITION FOR REHEARING EN BANC (DECIDED: May 30, 2001.
18907092 Double Patenting Table, Claims comparison
Instant Application Claims
(U.S. Patent No. 12,147,302) Claims
Independent Claims 1, 21, 25,
processing circuitry coupled to a memory to perform a tag read for data at the memory to check error detection correction information comprising parity information.
Independent Claims 1, 9, 13, A graphics multiprocessor, comprising: memory of the graphics multiprocessor for storing data, wherein the memory is cache or local memory; and error detection correction circuitry having error registers and integrated with the memory of the graphics multiprocessor,
the error detection correction circuitry is configured to perform a tag read of the memory to determine whether error detection correction information of error detection and correction logic indicates an error condition or not, and
to report the error condition to the error registers to log a source of a correctable error when a correctable error occurs or to report the error condition to the error registers to report an uncorrectable error when an uncorrectable error occurs, wherein the error detection correction circuitry is located on chip or on die with the graphics multiprocessor.
Claim 2. The graphics multiprocessor of claim 1, wherein the error detection correction information comprises parity information or a single-error-detecting code.
Claims 3, 22, 26, wherein the processing circuitry is further to determine whether the parity information indicates an error condition or not.
Claims 3, 9. The graphics multiprocessor of claim 2, wherein the error detection correction circuitry is further configured to determine whether the parity information or the single-error-detecting code indicates an error condition or not.
Claims 4, 23, 27, wherein the processing circuitry is further to determine whether the data associated with the parity information is clean based on being modified in cache or a local memory and also modified in main memory when the parity information indicates an error condition,
wherein if the data associated with the parity information is not clean, a fatal error condition is reported.
Claims 4, 10. The graphics multiprocessor of claim 3, wherein the error detection correction circuitry is further configured to determine whether data of the cache or shared memory that is associated with the parity information is clean based on being modified in the cache or shared memory and also modified in main memory when the parity information indicates an error condition.
Claim 5, 11. The graphics multiprocessor of claim 4, wherein if the data that is associated with the parity information is not clean, then a fatal error condition is reported.
Claims 7, 24, 28, wherein the cache or the local memory comprises an embedded dynamic
Claim 7. The graphics multiprocessor of claim 1, wherein the cache or local memory comprises an embedded dynamic random access memory (DRAM).
Claim 8. The graphics multiprocessor of claim 1, wherein the memory comprises a first level cache or a second level cache having the error detection correction circuitry that is located on chip or on die with the graphics multiprocessor.
Prior Art References Cited
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See References Cited on PTO-892 form.
Subramanian et al. 20200218605 [0024] FIG. 1. Error correction circuitry 141 may represent a subset of circuitry in process circuitry 145 devoted to managing processes related to error correction of one or more storage media (160-1 to 160-N) of storage device 120.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAMES C KERVEROS whose telephone number is (571)272-3824. The examiner can normally be reached 9-5.
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/JAMES C KERVEROS/Primary Examiner, Art Unit 2111
Date: May 11, 2026
Final Rejection 20260511
JAMES C. KERVEROS
Primary Examiner, Art Unit 2111
James.Kerveros@USPTO.GOV
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