Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
Claim(s) 21, 26-33, 35, 37, and 39-40 are rejected under 35 U.S.C. 103 as being unpatentable over Wang (PGPub No. 20160071818) in further view of Uzoh (PGPub No. 20180308819).
Regarding claim 21, Wang teaches a device comprising: at least three chips (Fig. 2A; 110F.1 – 110F.3), each comprising an interconnect area, each interconnect area neighboring interconnect areas of the other two of the at least three chips (Id.; 210A); and an interconnect device disposed over and overlapping only a portion of each of the at least three chips, the portions respectively comprising the interconnect areas (Fig. 2B; 110N); and each of the at least three chips is in electrical communication with a neighboring one of the at least three chips through a plurality of interconnections between the interconnect areas and the respective portions of the interconnect device disposed thereover ([0020]).
Wang fails to teach wherein: each of the interconnect areas is hybrid direct bonded to a respective portion of the interconnect device without an intervening adhesive.
Uzoh teaches wherein: each of the interconnect areas is hybrid direct bonded to a respective portion of the interconnect device without an intervening adhesive ([0069]). Thus, it would have been obvious to a person of ordinary skill in the art (POSITA) prior to the filing date of the claimed invention to combine the teachings of Wang and Uzoh, such that each of the interconnect areas is hybrid direct bonded to a respective portion of the interconnect device without an intervening adhesive in order to reduce the costs and complexity of fabrication and processing.
Regarding claim 26, Wang teaches wherein the device comprises at least four chips (Fig. 2A; 110F.1 – 110F.4), each comprising an interconnect area neighboring an interconnect area of one or more of the other chips (Id.; 210A).
Regarding claim 27, Wang teaches wherein the interconnect device is incorporated in a structure (Fig. 3A-2; MCM 204), the structure comprises pass-through interconnects in regions not overlapping by the interconnect device (Id.; 350), and each of the chips comprises a plurality of second pads coupled with the pass-through interconnects (Id.; 210B).
Regarding claim 28, Wang teaches wherein the device has a footprint area that is larger than a reticle used to form one or more of the chips (Fig. 3A-2).
Regarding claim 29, Wang teaches wherein the at least three chips are disposed in a first plane, and the interconnect device is disposed in a different second plane (Figs. 2B and 3A-2; 110F.1 – 110F.4, 110N).
Regarding claim 30, Wang teaches wherein the interconnect device has a surface area that is less than a collective surface area of the at least three chips (Fig. 2B; 110N).
Regarding claim 31, Wang teaches wherein a surface area of the interconnect device is less than a surface area of each of the at least three chips (Fig. 2C and [0045] point to various plain chips 110F (at least three chips) comprising different sizes. It is thus considered obvious that one of ordinary skill in the art would form each of the chips 110F to have a surface area that is larger than the super chip 110N (interconnect device) in order to create space(s) in which additional IOs 210B may be formed, allowing for further direct connections between the chips 110F and the wiring board WB.).
Regarding claim 32, Wang teaches a device comprising: at least three chips (Fig. 2A; 110F.1 – 110F.3), each comprising an interconnect area, each interconnect area neighboring interconnect areas of the other two of the at least three chips (Id.; 210A); and an interconnect device disposed over and bonded to a chip layer containing a portion of each of the at least three chips, the portions respectively comprising the interconnect areas (Fig. 2B; 110N); and each of the at least three chips is in electrical communication with a neighboring one of the at least three chips through a plurality of interconnections between the interconnect areas and the respective portions of the interconnect device disposed thereover ([0020]).
Wang fails to teach wherein: each of the interconnect areas is coupled through a hybrid direct bond to a respective portion of the interconnect device without an intervening adhesive.
Uzoh teaches wherein: each of the interconnect areas is hybrid direct bonded to a respective portion of the interconnect device without an intervening adhesive ([0069]). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Wang and Uzoh, such that each of the interconnect areas is hybrid direct bonded to a respective portion of the interconnect device without an intervening adhesive in order to reduce the costs and complexity of fabrication and processing.
Regarding claim 33, Wang teaches wherein: the at least three chips comprise a first chip, a second chip, and a third chip; the first chip is positioned at a first orientation (Fig. 2A; 110F.1); the second chip is positioned at a second orientation that is rotated relative to the first chip such that the interconnect area of the first chip is adjacent to the interconnect area of the second chip (Id.; 110F.2); and the third chip is positioned at a third orientation that is rotated relative to the first chip such that the interconnect area of the first chip is adjacent to the interconnect area of the third chip (Id.; 110F.3).
Regarding claim 35, Wang in combination with Uzoh teaches a method of forming a device comprising at least three chips, each having a portion comprising an interconnect area, and an interconnect device electrically connected to each of the at least three chips, the method comprising: positioning the at least three chips such that the interconnect area of each portion is neighboring interconnect areas of the other two of the at least three chips (Fig. 2A of Wang; 110F); and hybrid direct bonding each of the interconnect areas to a respective portion of the interconnect device without an intervening adhesive ([0069] of Uzoh) to form electrical connections between the interconnect areas and the interconnect device ([0020] of Wang). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Wang and Uzoh, such that each of the interconnect areas is hybrid direct bonded to a respective portion of the interconnect device without an intervening adhesive in order to reduce the costs and complexity of fabrication and processing.
Regarding claim 37, Wang teaches wherein the interconnect areas are each disposed proximate to an edge of their respective chip (Fig. 2A; 210A, 212).
Regarding claim 39, Wang teaches wherein the interconnect device is incorporated within a structure (Fig. 3A-2; MCM 204), the structure comprises pass-through interconnects in regions not overlapping the interconnect device (Id.; 350), and the method further comprises coupling the second pads with the pass-through interconnects (Id.; 210B).
Regarding claim 40, Wang teaches forming vias in the structure (Fig. 3A-2; 350) that extend through at least one semiconductor or dielectric region (Id.; 360).
Claim(s) 22-25, 34, 36, and 38 are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. in further view of Liff (PGPub No. 20200227377).
Regarding claim 22, Liff teaches wherein each of the interconnect areas has an interconnect pitch of less than twenty microns (Fig. 3 and [0050]; 130/124. In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Wang et al. and Liff, such that each of the interconnect areas has an interconnect pitch of less than twenty microns in order to provide high density interconnect routing in a localized area.
Regarding claim 23, Liff teaches wherein: the interconnect areas are first interconnect areas; the first interconnect areas have pads of a first size and a first pitch (Fig. 3; 124/130); each of the chips further comprises a second interconnect area that has pads of a second size and a second pitch; the second size is larger than the first size (Id.; 122/150); and the second pitch is greater than the first pitch ([0050]). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Wang et al. and Liff, such that each of the chips comprises pads of two different sizes and pitches in order to create a mixed-pitch die/chip that combines physical stability and/or simplicity in fabrication found in larger-pitch interconnects with the high density routing found in smaller-pitch interconnects.
Regarding claim 24, Wang teaches wherein the interconnect device is incorporated in a structure (Fig. 3A-2; MCM 204) comprising pass-through interconnects in regions not overlapping the interconnect device (Id.; 350), and the pads of the second size are coupled with the pass-through interconnects (Id.; 210B).
Regarding claim 25, Wang teaches wherein the structure comprises at least one semiconductor or dielectric region (Fig. 3A-2; 360), and the pass-through interconnects comprise vias that extend through the at least one semiconductor or dielectric region (Id.; 350).
Regarding claim 34, Liff teaches wherein: the interconnect areas are first interconnect areas; the first interconnect areas have pads of a first size and a first pitch (Fig. 3; 124/130); each of the chips further comprises a second interconnect area that has pads of a second size and a second pitch; the second size is larger than the first size (Id.; 122/150); and the second pitch is greater than the first pitch ([0050]). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Wang et al. and Liff, such that each of the chips comprises pads of two different sizes and pitches in order to create a mixed-pitch die/chip that combines physical stability and/or simplicity in fabrication found in larger-pitch interconnects with the high density routing found in smaller-pitch interconnects.
Regarding claim 36, wherein the interconnect areas of the at least three chips each comprise a plurality of electrical pads having a pitch less than twenty microns (Fig. 3 and [0050]; 130/124. In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Wang et al. and Liff, such that each of the interconnect areas has an interconnect pitch of less than twenty microns in order to provide high density interconnect routing in a localized area.
Regarding claim 38, wherein: each of the chips comprises first pads of a first size and a first pitch disposed in the interconnect area (Fig. 3; 124/130) and second pads of a second size and a second pitch disposed outside of the interconnect area, the second pads are larger than the first pads (Id.; 122/150), and the second pitch is greater than the first pitch ([0050]). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Wang et al. and Liff, such that each of the chips comprises pads of two different sizes and pitches in order to create a mixed-pitch die/chip that combines physical stability and/or simplicity in fabrication found in larger-pitch interconnects with the high density routing found in smaller-pitch interconnects.
Conclusion
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/PATRICK CULLEN/ Assistant Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
