Technology areas: Computing & Software • Semiconductors, Circuits & Optics
7 pending office actions • 7 art units • 7 examiners • 0 of 7 (0%) have an AI response strategy ready • 12 patents granted in the last 365 days
Adeia Semiconductor Technologies LLC is currently managing 8 pending office actions in the Semiconductors, Circuits & Optics technology area. The prosecution landscape is fragmented, as these 8 actions are distributed across 8 distinct examiners. This ratio of 8 actions to 8 examiners means that the company must navigate eight different sets of examiner preferences and styles simultaneously.
Furthermore, the company's applications are spread across 8 distinct art units, reflecting a broad technical footprint within the semiconductor and optics sectors. Jason Crawford is the busiest examiner for the portfolio, though he is responsible for only 1 pending office action. This high level of dispersion across 8 examiners and 8 art units requires a versatile legal strategy to manage the varied requirements of multiple USPTO technical divisions. Because Jason Crawford holds only 1 pending office action, the workload is balanced across the 8 distinct examiners.
Based on the USPTO statutory response window for each pending office action. 1 of the docket's apps have a known mailing date; the rest are excluded from the tile counts.
Difficulty is derived from the rejection statutes on the most recent pending office action. §101-driven and multi-statute cases are graded Hard; §112-only and obviousness-type double-patenting cases are graded Easy; everything else is Medium. "Unknown" means we have not yet parsed a statute for that office action.
| Bucket | Cases |
|---|---|
| §103 only | 3 (43%) |
| §102 only | 1 (14%) |
| Multi-statute (no §101) | 2 (29%) |
| No statute on record | 1 (14%) |
How the docket's pending cases split across USPTO tech-center bands.
Manual office-action response work runs about 10 hours per case. The time-saved bands below show what IP Author's prosecution pipeline typically delivers — a conservative 20% on the low end, 35% in the middle, 50% on the high end.
| Examiner | Apps on this docket | Allow rate | Interview lift |
|---|---|---|---|
| CRAWFORD, JASON | 1 | 84.9% | +9.3% |
| CULLEN, PATRICK LAWRENCE | 1 | 85.7% | +25.0% |
| YEN, PAUL JUEI-FU | 1 | 77.0% | +24.6% |
| GAMINO, CARLOS J | 1 | 35.3% | +45.7% |
| RAHMAN, ARIFUR | 1 | — | — |
| GHEYAS, SYED I | 1 | 82.8% | +3.7% |
| LEWIS-TAYLOR, DAYTON A. | 1 | 81.1% | +2.8% |
Cases in front of an examiner with an allow rate of 80%+ where the difficulty is Easy or Medium. The top 2 ordered by deadline are shown.
| App # | Title | Examiner | Due in |
|---|---|---|---|
| 19084097 | Symbiotic Network On Layers | CRAWFORD, JASON | — |
| 18907369 | CONNECTING MULTIPLE CHIPS USING AN INTERCONNECT DEVICE | CULLEN, PATRICK LAWRENCE | — |
Multi-statute / §101-driven matters, or cases in front of an examiner with an allow rate under 30%. The top 2 ordered by deadline are shown.
| App # | Title | Examiner | Due in |
|---|---|---|---|
| 18467481 | MULTI-CHIP MODULES FORMED USING WAFER-LEVEL PROCESSING OF A RECONSTITUTED WAFER | GHEYAS, SYED I | 13d |
| 17577944 | Network On Layer Enabled Architectures | LEWIS-TAYLOR, DAYTON A. | — |
Cases in front of an examiner whose interview lift is 10 percentage points or more — i.e. interviewed cases historically resolve more favorably than non-interviewed ones. The top 3 ordered by deadline are shown.
| App # | Title | Examiner | Due in |
|---|---|---|---|
| 18907369 | CONNECTING MULTIPLE CHIPS USING AN INTERCONNECT DEVICE | CULLEN, PATRICK LAWRENCE | — |
| 18890672 | METHOD OF DYNAMICALLY BALANCING VOLTAGE AND FREQUENCY WITH PERFORMANCE IN PROCESSING UNITS AND PROCESSING UNITS ADAPTED FOR SAME | YEN, PAUL JUEI-FU | — |
| 18601402 | Advanced Device Assembly Structures And Methods | GAMINO, CARLOS J | — |
| Art Unit | Apps |
|---|---|
| 2845 | 1 |
| 2899 | 1 |
| 2175 | 1 |
| 1735 | 1 |
| 2800 | 1 |
| 2893 | 1 |
| 2181 | 1 |
| App # | Title | Examiner | Art Unit | Statutes | Status | Due in | AI | Filed |
|---|---|---|---|---|---|---|---|---|
| 19084097 | Symbiotic Network On Layers | CRAWFORD, JASON | 2845 | §102 | Non-Final OA | — | Pending | Mar 19, 2025 |
| 18907369 | CONNECTING MULTIPLE CHIPS USING AN INTERCONNECT DEVICE | CULLEN, PATRICK LAWRENCE | 2899 | §103 | Non-Final OA | — | Pending | Oct 04, 2024 |
| 18890672 | METHOD OF DYNAMICALLY BALANCING VOLTAGE AND FREQUENCY WITH PERFORMANCE IN PROCESSING UNITS AND PROCESSING UNITS ADAPTED FOR SAME | YEN, PAUL JUEI-FU | 2175 | — | Non-Final OA | — | Pending | Sep 19, 2024 |
| 18601402 | Advanced Device Assembly Structures And Methods | GAMINO, CARLOS J | 1735 | §103 | Non-Final OA | — | Pending | Mar 11, 2024 |
| 18372947 | ACTIVE BRIDGING APPARATUS | RAHMAN, ARIFUR | 2800 | §103 | Final Rejection | — | Pending | Sep 26, 2023 |
| 18467481 | MULTI-CHIP MODULES FORMED USING WAFER-LEVEL PROCESSING OF A RECONSTITUTED WAFER | GHEYAS, SYED I | 2893 | §102§103 | Final Rejection | 13d | Pending | Sep 14, 2023 |
| 17577944 | Network On Layer Enabled Architectures | LEWIS-TAYLOR, DAYTON A. | 2181 | §102§103 | Non-Final OA | — | Pending | Jan 18, 2022 |
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Start Free TrialAdeia Semiconductor Technologies LLC has 7 pending office actions as of October 2026, spread across 7 art units and 7 examiners.
Jason Crawford has the most, with 1 of Adeia Semiconductor Technologies LLC's pending office actions.
Mostly Semiconductors, Circuits & Optics (USPTO Tech Center 2800), based on where its pending office actions are examined.
