Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
2. Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Election/Restrictions
3. Applicant’s election without traverse of Invention I, claims 1-12 in the reply filed on 9/1/2026 is acknowledged. Claims 13-24 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 9/1/2026.
Information Disclosure Statement
4. The information disclosure statement (IDS) submitted on 10/7/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
5. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
6. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
7. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
8. Claim(s) 1-2 and 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over the US Patent US 6,703,895 by Khemka et al., (Khemka hereafter) in view of the US Patent US 2010/0244947 by Massie et al., (Massie hereafter).
Regarding claim 1, Khemka teaches in Figure 2, a transistor arrangement, comprising:
a first transistor device (231) and a second transistor device (221) each comprising a load path (path extending between the source and drain of each respective transistor) and a control node (gate of each respective transistor), and each at least partially integrated in a semiconductor body (semiconductor device on which the transistors are mounted/formed), wherein the load path of the first transistor device and the load path of the second transistor device are connected in parallel (as shown in Figure 3);
a first control terminal (310) connected to the control node of the first transistor device through a first resistor (351); and
a second control terminal (320) connected to the control node of the second transistor device and connected to the first control pad through a second resistor (352).
Khemka substantially teaches all of the elements disclosed above, except for explicitly mentioning the use of “pads” as the terminals (310 and 320).
However, the use of contact pads is well known in the art. For example, Massie teaches in figure 2, a semiconductor arrangement including transistors connected to a terminal (12). Massie further teaches the use of pads (29) connected to said terminals in order to provide the ability for an external element (such as a probe) to connect to the transistor arrangement and/or the terminal. It would have been obvious to a person having ordinary skill in the art before the invention was effectively filed, to apply the teaching of contact pads as taught by Massie, and include contact pads connected to the first and second control terminals, or replace the terminals with said pads, in the device/system/method of Khemka, in order to gain the ability to connect an external device (such as a tester) to the arrangement of transistors, thus allowing the system to be tested for performance.
Regarding claim 2, Khemka teaches in Figure 3, the transistor arrangement of claim 1,
wherein the load path of the first transistor device (231) is a circuit path between a first load electrode (330) and a second load electrode (electrode “A” see annotated Fig. 3 below), and
wherein the load path of the second transistor device (221) is a circuit path between the first load electrode (330) and the second load electrode (electrode “A” see annotated Fig. I below).
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Annotated Fig. I
Khemka substantially teaches all of the elements disclosed above, except for explicitly mentioning that the first electrode is arranged above a first surface of the semiconductor body, or that the second load electrode is arranged above a second surface opposite the first surface of the semiconductor body.
However, it would have been obvious to a person having ordinary skill in the art before the invention was effectively filed, to locate/position the first and/or second electrode a preferred position within the semiconductor device, including the upper and/or lower surfaces of the semiconductor body. Shifting/relocating the position of the electrodes would not have modified the functionality of the apparatus as claimed. The particular placement of the electrodes (as long as their electrical connection to other elements in Khemka’s device remain the same) would be an obvious matter of design choice. In re Kuhle, 526 F.2d 553, 188 USPQ 7 (CCPA 1975) (the particular placement of a contact in a conductivity measuring device was held to be an obvious matter of design choice).
Regarding claim 5, Khemka substantially teaches all of the elements disclosed above, except for explicitly mentioning that the first control pad and the second control pad are “formed” above a first surface of the semiconductor body.
However, it would have been obvious to a person having ordinary skill in the art before the invention was effectively filed, to locate/position the first and/or second control pad to a preferred position within the semiconductor device, including above a first surface of the semiconductor body. Shifting/relocating the position of the control pad would not have modified the functionality of the apparatus as claimed. The particular placement of the control pad (as long as their electrical connection to other elements in Khemka’s device remain the same) would be an obvious matter of design choice. In re Kuhle, 526 F.2d 553, 188 USPQ 7 (CCPA 1975) (the particular placement of a contact in a conductivity measuring device was held to be an obvious matter of design choice).
Regarding claim 12, Khemka teaches each of the first and second transistor devices is a MOSFET (see for example, col. 6, lines 29-36 and col. 10, lines 33-35).
9. Claim(s) 1, 3-4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Khemka in view of Massie.
Regarding claims 1 and 3, Khemka teaches in Figure 2, a transistor arrangement, comprising:
a first transistor device (221+210) and a second transistor device (231+241) each comprising a load path (path extending between the source and drain of each respective transistor) and a control node (node “B” is the control node for the first transistor device, while node “C” is the control node for the second transistor device) in annotated Figure II below), and each at least partially integrated in a semiconductor body (semiconductor device on which the transistors are mounted/formed), wherein the load path of the first transistor device and the load path of the second transistor device are connected in parallel (as shown in Figure 3);
a first control terminal (320) connected to the control node of the first transistor device through a first resistor (354); and
a second control terminal (310) connected to the control node of the second transistor device and connected to the first control pad through a second resistor (351 or 352);
wherein the first transistor device comprises a plurality of first transistor cells (210 and 221) that each include a control electrode (conductive line connecting the gate of each of transistors 210 and 221 to node “B”, see annotated Figure II below),
wherein the second transistor device comprises a plurality of second transistor cells (231 and 241) that each include a control electrode (conductive line connecting the gate of each of transistors 231 and 241 to node “C”, see annotated Figure II below),
wherein the control node of the first transistor device is formed by the control electrodes of the first transistor cells (as illustrated in Figure 3), and
wherein the control node of the second transistor device is formed by the control electrodes of the second transistor cells (as illustrated in Figure 3).
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Annotated Fig. II
Khemka substantially teaches all of the elements disclosed above, except for explicitly mentioning the use of “pads” as the terminals (310 and 320).
However, the use of contact pads is well known in the art. For example, Massie teaches in figure 2, a semiconductor arrangement including transistors connected to a terminal (12). Massie further teaches the use of pads (29) connected to said terminals in order to provide the ability for an external element (such as a probe) to connect to the transistor arrangement and/or the terminal. It would have been obvious to a person having ordinary skill in the art before the invention was effectively filed, to apply the teaching of contact pads as taught by Massie, and include contact pads connected to the first and second control terminals, or replace the terminals with said pads, in the device/system/method of Khemka, in order to gain the ability to connect an external device (such as a tester) to the arrangement of transistors, thus allowing the system to be tested for performance.
Regarding claim 4, Khemka shows in Figure 3, the control electrodes of the first transistor cells are connected to an electrically conducting gate runner (conductive line connecting point “B” to pad 320) formed above the first surface of the semiconductor body, and
wherein the gate runner (conductive line connecting point “B” to pad 320) is connected to the first control pad (320) through the first resistor (354).
Khemka substantially teaches all of the elements disclosed above, except for explicitly mentioning that the conductive gate runner is arranged above a first surface of the semiconductor body.
However, it would have been obvious to a person having ordinary skill in the art before the invention was effectively filed, to locate/position the gate runner to a preferred position within the semiconductor device, including the upper and/or lower surfaces of the semiconductor body. Shifting/relocating the position of the electrodes would not have modified the functionality of the apparatus as claimed. The particular placement of the electrodes (as long as their electrical connection to other elements in Khemka’s device remain the same) would be an obvious matter of design choice. In re Kuhle, 526 F.2d 553, 188 USPQ 7 (CCPA 1975) (the particular placement of a contact in a conductivity measuring device was held to be an obvious matter of design choice).
Allowable Subject Matter
10. Claims 6-11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 6, the prior art of record doesn’t teach alone or in combination the transistor arrangement as recited in claim 5, wherein the first resistor is formed in an insulating layer formed above the first surface of the semiconductor body, in combination with all other elements recited.
As to claims 7, the claims is objected as they further limit claim 6 above.
Regarding claim 8 , the prior art of record doesn’t teach alone or in combination the transistor arrangement of claim 5, wherein the second resistor is formed in an insulating layer formed above the first surface of the semiconductor body, in combination with all other elements recited.
As to claim 9, the claims are objected as they further limit claim 8 above.
Regarding claim 10, the prior art of record doesn’t teach alone or in combination a transistor arrangement of claim 1, wherein a ratio between a resistance of the second resistor and the first resistor at least approximately equals a ratio between a size of the first transistor device and a size of the second transistor device, in combination with all other elements recited.
Regarding claim 11, the prior art of record doesn’t teach alone or in combination the transistor arrangement of claim 1, wherein a ratio between a size of the first transistor device and a size of the second transistor device is at least 100, at least 1000, or at least 10000, in combination with all other elements recited.
Conclusion
11. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
- The US Patent US 10,153,762 by Ladurner et al., directed to methods for controlling semiconductor components including an arrangement of transistors connected in parallel.
- The US Patent US 7,573,287 by Rabenstein et al., directed to devices using transistors connected in parallel.
- The US Patent US 11,362,504 by Santillan et al., directed to overcurrent sensing arrangements.
- The US Patent US 9,590,617 by Komiya et al., directed to power conversion devices including arrangements of transistors connected in parallel.
- The US Patent US 10,935,592 by Botti et al., directed to current sensing methods.
12. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Richard Isla whose telephone number is (571)272-5056. The examiner can normally be reached Monday-Friday 9a - 5:30p.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Huy Phan can be reached at 571 272-7924. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/RICHARD ISLA/
Primary Patent Examiner, Art Unit 2858
September 14, 2026
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