Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is in response to communications filed on 7/15/26.
Claims 1-30 are pending.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 7-8, 30 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by NA et al (US Patent Application Publication 2017/0263188).
For claim 7, NA et al teach the following limitations: A display device (Fig 1 – Fig 6) comprising: pixels connected to scan lines, emission control lines, and data lines ([0027]-[0028] – pixel rows connected to data lines, emission control lines and gate lines (or, scan lines)); a scan driver configured to supply a scan signal to the scan lines (scan driver 500 includes gate driver to generate gate signals [0028][0032]-[0034]; gate lines are the scan lines – see applicant’s specification [0068]-[0069] Fig 1); an emission driver configured to supply an emission control signal to the emission control lines ([0034] emission driver generates emission control signals; [0028] emission control lines Fig 1 Fig 2 Fig 3; EMn-1 shown in Fig 4 is the emission control signal); and a clock controller (Fig 4; 500 includes clock controller) configured to receive at least one clock signal to drive the scan driver (Fig 4 shows the reception of clock signal via CT inputs and drives the scan driver to generate the output Gn; Fig 5 shows the partial circuitry, where the clock controller receives the clock signals to drive the gate lines; [0094] mentions OT1 may output the voltage of second clock signal CK2 for gate signal Gn; thus the scan driver 650 shown in Fig 5 is driven by the clock controller), and configured to determine whether to supply the clock signal to the scan driver (the clock controller includes the various transistors and other circuits in 610, 650 and 630 of Fig 5 and determines whether to supply the clock CK2 to scan driver 650; Fig 6 shows how Gn follows the CK2) in response to the emission control signal (Fig 6 shows that EMn-1 is provided during periods a -f; Fig 5 shows EMn-1 is an input to transistor to T3-3; for proper operation of the circuitry, EMn-1 signal must be provided (may be either low or high); thus the 650 operates in response to emission control signal EMn-1; without EMn-1 connection circuit will be floating and non-working).
For claim 8, NA teaches wherein the clock controller is configured to sequentially receive the emission control signal in a horizontal line unit (Fig 4 shows the circuitry; each CS is one horizontal line unit; EMn-1 is received in CSn in a sequence), and configured to output the clock signal in the horizontal line unit (the clock signal CK2 is output to OT1 as mentioned in [0094]) in response to the emission control signal (EMn-1 is shown as input in 650; the circuitry works when the EMn-1 is provided with a signal).
For claim 30, NA teaches the following limitations A method of driving a display device (Fig 1 – Fig 6) comprising a scan driver (scan driver 500 includes gate driver to generate gate signals [0028][0032]-[0034]; gate lines are the scan lines – see applicant’s specification [0068]-[0069] Fig 1) and a clock controller (Fig 4; 500 includes clock controller; Fig 5 shows various clock signals and transistors driven by the clock signals; thus clock controller is integrated with the scan driver), the method comprising: sequentially supplying an emission control signal to pixels ([0027]-[0028] – pixel rows connected to data lines, emission control lines; Fig 4 shows the circuitry; each CS is one horizontal line unit; EMn-1 is received in CSn; Fig 1 sequentially supplied); outputting a clock signal (the clock signal CK2 is output to OT1 as mentioned in [0094]; Fig 4 shows that the clock signal is output in the horizontal line unit) when the emission control signal is input (Fig 6 shows that EMn-1 is provided during periods a -f; Fig 5 shows EMn-1 is an input to transistor to T3-3; for proper operation of the circuitry, EMn-1 signal must be provided (may be either low or high); thus the 650 operates in response to emission control signal EMn-1; without EMn-1 connection circuit will be floating and non-working); and sequentially supplying a scan signal in response to a clock signal input (Fig 4 shows the reception of clock signal via CT inputs and drives the scan driver to generate the output Gn; Fig 5 shows the partial circuitry, where the clock controller receives the clock signals to drive the gate lines; [0094] mentions OT1 may output the voltage of second clock signal CK2 for gate signal Gn; thus the scan signal Gn is sequentially supplied in response to CK2 input in horizontal line unit through CSn as shown in Fig 4 – Fig 6); wherein the clock controller comprises a plurality of clock selection circuits (clock controller circuit is integrated with scan driver; Fig 5 shows various transistors to select the clocks; [0091][0094][0097] the transistor T1-8 is turned on to select CK2 based on voltage on control node Q1; Fig 5 shown CSn; the other CS circuitries have similar clock selection circuit; thus, there are plural clock selection circuits in the scan driver 500), and the scan driver comprises a plurality of stage circuits ([0049] scan driver includes plurality of circuit stages CS1 to CSn+2 which includes claimed stage circuits) and wherein an i-th clock selection circuit at an i-th horizontal line is configured to supply the clock signal to an ith stage circuit ([0091][0094][0097] mention that the transistor T1-8 is turned on to supply the clock signal CK2 to terminal OT1 and OT1 may output the voltage of CK2 as the voltage of gate signal Gn; [0011] the transistor to output gate signal synchronized with second clock sugnal) at the ith horizontal line (Fig 4 shows the stages for each horizontal line; CSn is the ith horizontal line; [0033]) when the emission control signal is supplied to the i-th emission control line (EMn-1 signal is provided CSn as shown in Fig 4; IN3 in CSn shown in Fig 4 is the ith emission control line; the emission control signal EMn-1 is supplied to i-th emission control line IN3 of CSn)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over NA et al (US Patent Application Publication 2017/0263188), in view of Kim et al (US Patent Application Publication 11462152).
For claim 17, NA et al teaches plural scan lines (Gate lines Gn-1, Gn, Gn1 in Fig 4) but does not explicitly mention first scan driver and second scan driver. Kim et al mention plural scan drivers driving plurality of scan lines respectively (Fig 2; lines 59-67 of col 8). It would have been obvious for one ordinary skill in the art before the effective filing date of the invention to provide multiple scan drivers because using separate driver instead of one centralized driver provides better control in the system.
Allowable Subject Matter
Claims 1-6, 25-29 are allowed.
Claims 9-16, 18-24 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant's arguments have been fully considered but they are not persuasive.
Applicant argues that cited art Na does not teach or suggest “a clock controller configured to receive at least one clock signal to drive the scan driver and configured to determine whether to supply the clock signal to the scan driver in response to the emission control signal.” According to the applicant, Na’s nth circuit stage CSn of a scan driver 500 outputs the nth emission control signal EMn and nth compensation control signal GRn, but does not disclose scan driver 500 to determine whether to supply the clock signal to the scan driver in response to the emission control signal.
Examiner disagrees. The scan driver 500 includes the clock controller (i.e., the circuitries are integrated as explained in [0034]) when it drives various clock signals CK1, CK2, CK3 and CK4 through various transistors. The clock controller at least includes transistor T1-8 in 610 that receives clock signal CK2 and the transistor T1-8 of the clock controller is not always turned on to supply the clock signal CK2 to terminal OT1 ([0091][0094][0097]). As mentioned in [0091][0094] and [0097], the transistor T1-8 is turned on based on the voltage of node Q1 and then the terminal OT1 receives the high/low signal of CK2 as a gate signal Gn. Q1 is charged based on CK1 and other inputs. Without proper voltage inputs and proper voltage in Q1, transistor T1-8 is not configured to supply the clock signal CK2 to output terminal OT1 to drive the scan driver. Therefore, the clock controller is configured to determine whether to supply the clock signal CK2 to terminal OT1 based on the appropriate voltage on node Q1. According to [0011] of Na:
a first T1 transistor to apply an (n−1)-th gate signal to a first control node based on a first clock signal, a second T1 transistor to output an n-th gate signal synchronized with the second clock signal based on a voltage of the first control node
Thus, the clock controller is configured to determine whether to supply the clock signal to the scan driver based on the node voltage.
For the limitations, “in response to the emission control signal”, the BRI only requires the “in response to the presence/existence of the emission control signal.” Fig 5 shows EMn-1 exists as an input in IN2. Fig 6 shows that EMn-1 is applied to the circuitries of Fig 5. Claim only requires existence of the emission control signal; however, does not require emission control signal to control the clock controller. Additionally, it is understood that presence of EMn-1 in Fig 5 is necessary to drive the circuitry and without the supply of EMn-1, the output terminal OT1 would not receive the appropriate signals. The floating input terminals will preclude the proper operation of the circuit.
Applicant further argues that Na does not teach the limitations wherein the clock controller comprises a plurality of clock selection circuits, and the scan driver comprises a plurality of stage circuits, and wherein an i-th (i is a natural number) clock selection circuit at an i-th horizontal line is configured to supply the clock signal to an i-th stage circuit at the i-th horizontal line when the emission control signal is supplied to i-th emission control line.
Examiner disagrees. Fig 4 shows the plural stage circuits and 500 in Fig 4 and Fig 5 provide the integrated scan driver and clock driver. Fig 4 shows that the each stage CS corresponds to a horizontal line. Fig 4 CSn has scan driver to drive the gate signal Gn. Fig 5 shows that the clock selection circuit includes various transistors to supply the clock signal so that the scan driver can drive the gate signal. The full claim mapping is reproduced below: wherein the clock controller comprises a plurality of clock selection circuits (clock controller circuit is integrated with scan driver; Fig 5 shows various transistors to select the clocks; [0091][0094][0097] the transistor T1-8 is turned on to select CK2 based on voltage on control node Q1; Fig 5 shown CSn; the other CS circuitries have similar clock selection circuit; thus, there are plural clock selection circuits in the scan driver 500), and the scan driver comprises a plurality of stage circuits ([0049] scan driver includes plurality of circuit stages CS1 to CSn+2 which includes claimed stage circuits) and wherein an i-th clock selection circuit at an i-th horizontal line is configured to supply the clock signal to an ith stage circuit ([0091][0094][0097] mention that the transistor T1-8 is turned on to supply the clock signal CK2 to terminal OT1 and OT1 may output the voltage of CK2 as the voltage of gate signal Gn; [0011] the transistor to output gate signal synchronized with second clock sugnal) at the ith horizontal line (Fig 4 shows the stages for each horizontal line; CSn is the ith horizontal line; [0033]) when the emission control signal is supplied to the i-th emission control line (EMn-1 signal is provided CSn as shown in Fig 4; IN3 in CSn shown in Fig 4 is the ith emission control line; the emission control signal EMn-1 is supplied to i-th emission control line IN3 of CSn)
Therefore, Na teaches the claim limitations sufficiently.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FAHMIDA RAHMAN whose telephone number is (571)272-8159. The examiner can normally be reached Monday - Friday 10 AM - 7 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrew Jung can be reached at 571-270-3779. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/FAHMIDA RAHMAN/Primary Examiner, Art Unit 2175
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