DETAILED ACTION
This office action is in response to the application filed on 10/7/2024. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Acknowledgement
The present office action is made with all the suggested amendments being fully considered. Accordingly, claims 1-20 are pending in this application.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 10/7/2024 is being considered by the examiner.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-7 and 10-20 are rejected under 35 U.S.C. 103 as being unpatentable over Seo (US 2022/0013418) in view of Cho (KR 20060120062A) and in further view of Tsukiyama (US 2021/0233781)
With respect to Claim 1, Seo shows (Fig. 5) most aspects of the current invention including a semiconductor package, comprising:
a package substrate (S) including substrate pads (par 72 and 74; pads on surface to connect to devices stacked on the substrate)
a plurality of semiconductor chips (300A-300D) stacked on an upper surface of the package substrate;
bonding wirings (340A-340D) electrically connecting the plurality of semiconductor chips and the substrate pads of the package substrate to each other;
wherein each of the plurality of semiconductor chips comprises:
a semiconductor substrate (body) including first and second edges (301A-D,302A-D) facing each other, the first and second edges extending in a first direction,
chip pad patterns (312A-D) on a portion of a semiconductor chip region of the semiconductor substrate that is adjacent to the first edge, the chip pad patterns being along the first edge,
However, Seo does not show a sealing member on the upper surface of the package substrate and covering the plurality of semiconductor chips and a moat structure including a plurality of moat structures, the plurality of moat structures including a first moat structure and a second moat structure, the first moat structure being on a first scribe lane region of the semiconductor substrate that is adjacent to the chip pad patterns and the second moat structure being on a second scribe lane region of the semiconductor substrate that is adjacent to the second edge, and wherein the first moat structure extends along the first edge, and the second moat structure extends along the second edge.
On the other hand, and in the same field of endeavor, Cho teaches (Fig. 4c,6) a semiconductor package, comprising a plurality of semiconductor chips (510,520) stacked on an upper surface of a package substrate, wherein each of the plurality of semiconductor chips comprises a semiconductor substrate (body) including first and second edges facing each other, chip pad patterns (414) on a portion of a semiconductor chip region of the semiconductor substrate that is adjacent to the first edge, and a moat structure including a plurality of moat structures (462,464), the plurality of moat structures including a first moat structure (462a,464a) and a second moat structure (462b,464b), the first moat structure being on a first scribe lane region (420) of the semiconductor substrate that is adjacent to the chip pad patterns and the second moat structure being on a second scribe lane region (420) of the semiconductor substrate that is adjacent to the second edge, and wherein the first moat structure extends along the first edge, and the second moat structure extends along the second edge. Cho teaches this arrangement allows the stacked semiconductor chips to be stacked in close contact with each other regardless of contact with the bonding wire, which is advantageous in reducing the thickness of the stacked package.
Therefore, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to have the arrangement of the a plurality of moat structures, the plurality of moat structures including a first moat structure and a second moat structure, the first moat structure being on a first scribe lane region of the semiconductor substrate that is adjacent to the chip pad patterns and the second moat structure being on a second scribe lane region of the semiconductor substrate that is adjacent to the second edge, and wherein the first moat structure extends along the first edge, and the second moat structure extends along the second edge in the device of Seo, as taught by Cho to allow the stacked semiconductor chips to be stacked in close contact with each other regardless of contact with the bonding wire, which is advantageous in reducing the thickness of the stacked package.
However, the combination of references do not show a sealing member on the upper surface of the package substrate and covering the plurality of semiconductor chips.
On the other hand, and in the same field of endeavor, Tsukiyama teaches (Fig. 1) a semiconductor package, comprising a plurality of semiconductor chips (CH1) stacked on an upper surface of a package substrate (11), and a sealing member (23) on the upper surface of the package substrate and covering the plurality of semiconductor chips. Tsukiyama teaches the sealing member protects the semiconductor chips, the adhesive layers, and the bonding wires from an external impact or outside air (par 34)
Therefore, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to have the arrangement of a sealing member on the upper surface of the package substrate and covering the plurality of semiconductor chips in the device of Seo and Cho, as taught by Tsukiyama because the sealing member protects the semiconductor chips, the adhesive layers, and the bonding wires from an external impact or outside air.
With respect to Claim 2, Seo shows (Fig. 5) further comprising: a test element group pattern (322A-322D) on another scribe lane region. Additionally, Cho teaches (Fig. 4c,6) wherein the first moat structure being on a first scribe lane region (420) of the semiconductor substrate that is adjacent to the chip pad patterns and the second moat structure being on a second scribe lane region (420) of the semiconductor substrate that is adjacent to the second edge.
Therefore, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to have the arrangement of a test element group pattern on another scribe lane region between the plurality of moat structures, in each of the semiconductor chips, as it has been held by the court that a prima facie case of obviousness exists in the case where all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination yielded nothing more than predictable results to one of ordinary skill in the art. See in re KSR Int’l Co. v. Teleflex Inc, 550 U.S. at 416, 82 USPQ2d at 1395.
With respect to Claim 3, Seo shows (Fig. 5) wherein the semiconductor chip region includes a third edge and a fourth edge extending in a second direction perpendicular to the first direction and facing each other, and the test element group pattern is on a third scribe lane region adjacent to the third edge and on a fourth scribe lane region adjacent to the fourth edge.
With respect to Claim 4, Cho teaches (Fig. 4c,6) wherein a group of the plurality of moat structures included in at least one of the semiconductor chips are symmetrical to each other.
With respect to Claim 5, Cho teaches (Fig. 3e) wherein the first moat structure is spaced apart from the first edge, and continuously extends along an entirety of the first edge, and wherein the second moat structure is spaced apart from the second edge, and continuously extends along an entirety of the second edge
With respect to Claim 6, Cho teaches (Fig. 4c,6) wherein the first moat structure extends continuously within the first scribe lane region, and the second moat structure extends continuously within the second scribe lane region
With respect to Claim 7, Cho teaches (Fig. 3c-3e) wherein each of the plurality of moat structures has a structure in which a protective insulation structure (460) is filled in a trench of a lower structure on a corresponding one of the first scribe lane region and the second scribe lane region
With respect to Claim 10, Cho teaches (Fig. 3c-3e) wherein each of the plurality of moat structures has a predetermined width. However, the combination of references do not show wherein a width of each of the plurality of moat structures is in a range of 8 µm to 10 µm. However, it is noted that the specification fails to provide teachings about the criticality of having a width of each of the plurality of moat structures is in a range of 8 µm to 10 µm, as claimed in the instant application.
Regarding claim 10, the courts have held, differences in widths will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such widths are critical. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
Since the applicant has not established the criticality of having a width of each of the plurality of moat structures is in a range of 8 µm to 10 µm as claimed by the applicant, and similar arrangements are known in the art (see Cho), it would have been obvious to one of the ordinary skill in the art to modify the arrangement in the device of Seo in view of Cho and Tsukiyama.
Criticality: The specification contains no disclosure of either the critical nature of the claimed arrangement of widths or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ 2d 1934, 1936 (Fed Cir. 1990).
With respect to Claim 11, Seo shows (Fig. 5) wherein edges in a second direction, which is perpendicular to the first direction, of adjacent semiconductor chips from among the plurality of semiconductor chips, are offset from each other.
With respect to Claim 12, Seo shows (Fig. 5) wherein some sidewalls of adjacent semiconductor chips from among the plurality of semiconductor chips laterally protrude and define an overhang region
With respect to Claim 13, Seo shows (Fig. 5) most aspects of the current invention including a semiconductor package, comprising:
a package substrate (S) including substrate pads (par 72 and 74; pads on surface to connect to devices stacked on the substrate)
a plurality of semiconductor chips (300A-300D) stacked on an upper surface of the package substrate, and including chip pad patterns (312A-D) and test element group patterns (322A-322D)
bonding wirings (340A-340D) electrically connecting the plurality of semiconductor chips and the substrate pads of the package substrate to each other;
wherein each of the plurality of semiconductor chips includes a semiconductor chip region (body) and a scribe lane region (outer region) surrounding the semiconductor chip region, the semiconductor chip region including a first edge, a second edge, a third edge, and a fourth edge, the first and second edges extending in a first direction and facing each other, the third and fourth edges extending in a second direction perpendicular to the first direction and facing each other,
wherein the chip pad patterns are on a portion of the semiconductor chip region that is adjacent to the first edge, and the chip pad patterns are spaced apart from each other in the first direction, wherein the scribe lane region includes a first scribe lane region adjacent to the chip pad patterns and a second scribe lane region adjacent to the second edge of the semiconductor chip region
wherein the test element group patterns are on one or more scribe lane regions other than the first scribe lane region and the second scribe lane region
However, Seo does not show a sealing member on the upper surface of the package substrate and covering the plurality of semiconductor chips and wherein the moat structures include a first moat structure and a second moat structure, the first moat structure being on the first scribe lane region, the second moat structure being on the second scribe lane region, and each of the moat structures extending in the first direction.
On the other hand, and in the same field of endeavor, Cho teaches (Fig. 4c,6) a semiconductor package, comprising a plurality of semiconductor chips (510,520) stacked on an upper surface of a package substrate, wherein each of the plurality of semiconductor chips comprises chip pad patterns (414) and moat structures (462a,464a), and wherein the moat structures include a first moat structure (462a,464a) and a second moat structure (462b,464b), the first moat structure and the second moat structure (462b,464b), the first moat structure being on the first scribe lane region (420), the second moat structure being on the second scribe lane region (420), and each of the moat structures extending in the first direction. Cho teaches this arrangement allows the stacked semiconductor chips to be stacked in close contact with each other regardless of contact with the bonding wire, which is advantageous in reducing the thickness of the stacked package.
Therefore, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to have the arrangement of wherein the moat structures include a first moat structure and a second moat structure, the first moat structure being on the first scribe lane region, the second moat structure being on the second scribe lane region, and each of the moat structures extending in the first direction in the device of Seo, as taught by Cho to allow the stacked semiconductor chips to be stacked in close contact with each other regardless of contact with the bonding wire, which is advantageous in reducing the thickness of the stacked package.
However, the combination of references do not show a sealing member on the upper surface of the package substrate and covering the plurality of semiconductor chips.
On the other hand, and in the same field of endeavor, Tsukiyama teaches (Fig. 1) a semiconductor package, comprising a plurality of semiconductor chips (CH1) stacked on an upper surface of a package substrate (11), and a sealing member (23) on the upper surface of the package substrate and covering the plurality of semiconductor chips. Tsukiyama teaches the sealing member protects the semiconductor chips, the adhesive layers, and the bonding wires from an external impact or outside air (par 34)
Therefore, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to have the arrangement of a sealing member on the upper surface of the package substrate and covering the plurality of semiconductor chips in the device of Seo and Cho, as taught by Tsukiyama because the sealing member protects the semiconductor chips, the adhesive layers, and the bonding wires from an external impact or outside air.
With respect to Claim 14, Seo shows (Fig. 5) wherein edges in the second direction of adjacent semiconductor chips from among the plurality of semiconductor chips are offset from each other.
With respect to Claim 15, Cho teaches (Fig. 4c,6) wherein the first moat structure is spaced apart from the first edge and continuously extends along an entirety of the first edge, and the second moat structure is spaced apart from and continuously extends along an entire of the second edge.
With respect to Claim 16, Seo shows (Fig. 5) wherein the scribe lane region further includes a third scribe lane region adjacent to the third edge and a fourth scribe lane region adjacent to the fourth edge, the test element group patterns are on at least one of the third scribe lane region or the fourth scribe lane region
With respect to Claim 17, Cho teaches (Fig. 3e) wherein the first moat structure extends along an entirety of the first scribe lane region and portions of the third and fourth scribe lane regions, and the second moat structure extends along an entirety of the second scribe lane region and portions of the third and fourth scribe lane region.
With respect to Claim 18, Cho teaches (Fig. 3c-3e) wherein each of the plurality of moat structures has a structure in which a protective insulation structure (460) is filled in a trench of a lower structure on the scribe lane region
With respect to Claim 19, Cho teaches (Fig. 4c,6) wherein a group of the moat structures included in at least one of the semiconductor chips are symmetrical to each other.
With respect to Claim 20, Seo shows (Fig. 5) most aspects of the current invention including a semiconductor package, comprising:
a package substrate (S) including substrate pads (par 72 and 74; pads on surface to connect to devices stacked on the substrate)
a plurality of semiconductor chips (300A-300D) stacked on an upper surface of the package substrate, some edges of adjacent semiconductor chips from among the plurality of semiconductor chips are offset from each other
bonding wirings (340A-340D) electrically connecting the plurality of semiconductor chips and the substrate pads of the package substrate to each other;
wherein at least one of the plurality of semiconductor chips comprises:
chip pad patterns (312A-D) along a first edge of a semiconductor chip region
a test element group patterns (322A-322D) on a third scribe lane region
However, Seo does not show a sealing member on the upper surface of the package substrate and covering the plurality of semiconductor chips and moat structures on a first scribe lane region adjacent to the chip pad patterns and a second scribe lane region adjacent to a second edge facing the first edge of the semiconductor chip region.
On the other hand, and in the same field of endeavor, Cho teaches (Fig. 4c,6) a semiconductor package, comprising a plurality of semiconductor chips (510,520) stacked on an upper surface of a package substrate, wherein the plurality of semiconductor chips comprises chip pad patterns (414) on a first edge of a semiconductor chip region, and moat structures (462,464) on a first scribe lane region adjacent to the chip pad patterns and a second scribe lane region adjacent to a second edge facing the first edge of the semiconductor chip region. Cho teaches this arrangement allows the stacked semiconductor chips to be stacked in close contact with each other regardless of contact with the bonding wire, which is advantageous in reducing the thickness of the stacked package.
Therefore, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to have the arrangement of moat structures on a first scribe lane region adjacent to the chip pad patterns and a second scribe lane region adjacent to a second edge facing the first edge of the semiconductor chip region in the device of Seo, as taught by Cho to allow the stacked semiconductor chips to be stacked in close contact with each other regardless of contact with the bonding wire, which is advantageous in reducing the thickness of the stacked package.
However, the combination of references do not show a sealing member on the upper surface of the package substrate and covering the plurality of semiconductor chips.
On the other hand, and in the same field of endeavor, Tsukiyama teaches (Fig. 1) a semiconductor package, comprising a plurality of semiconductor chips (CH1) stacked on an upper surface of a package substrate (11), and a sealing member (23) on the upper surface of the package substrate and covering the plurality of semiconductor chips. Tsukiyama teaches the sealing member protects the semiconductor chips, the adhesive layers, and the bonding wires from an external impact or outside air (par 34)
Therefore, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to have the arrangement of a sealing member on the upper surface of the package substrate and covering the plurality of semiconductor chips in the device of Seo and Cho, as taught by Tsukiyama because the sealing member protects the semiconductor chips, the adhesive layers, and the bonding wires from an external impact or outside air.
Claims 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Seo (US 2022/0013418) in view of Cho (KR 20060120062A) and in further view of Tsukiyama (US 2021/0233781) and Han (US 10,665,557)
With respect to Claim 8, Seo in view of Cho and Tsukiyama shows most aspects of the current invention. However, the combination of references do not show wherein the protective insulation structure includes a metal barrier pattern, a capping insulation layer, and an upper protective layer.
On the other hand, and in the same field of endeavor, Han teaches (Fig. 1-2,6C) a semiconductor package, comprising a plurality of chips regions (10) stacked on an upper surface of a package substrate, and scribe lines (10) surrounding the chips regions, and further a moat structure including a plurality of moat structures (OP), the plurality of moat structures including a first moat structure and a second moat structure, the first moat structure being on a first scribe lane region of the semiconductor substrate and second moat structure being on a second scribe lane region of the semiconductor substrate that is adjacent to the second edge, wherein each of the plurality of moat structures has a protective insulation structure, wherein the protective insulation structure includes a metal barrier pattern (145), a capping insulation layer (151), and an upper protective layer (153). Han teaches the protective insulation structure is used to provide protection to components in the device.
Therefore, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to have wherein the protective insulation structure includes a metal barrier pattern, a capping insulation layer, and an upper protective layer in the device of Seo in view of Cho and Tsukiyama, as taught by Han to provide protection to components in the device
With respect to Claim 9, Han teaches (Fig. 1-2,6C) wherein the upper protective layer (153) includes photosensitive polyimide (PSPI).
Conclusion
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/Q. B./
Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814
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