DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Amendment filed March 17, 206 has been entered. Claims 1-4, 8-17, and 19 remain pending in the application. Claims 5-7, 18, and 20-22 have been cancelled. Applicant’s response to the rejection (Remarks page 10, paragraph 1) stating on the record that claimed limitation “a controller” is a physical device avoids the 35 U.S.C. 112(f) interpretation because doing so presents a sufficient showing that the claim limitation recites sufficient structure to perform the claimed functions. The response also overcomes corresponding 35 U.S.C. 112(a) and 35 U.S.C. 112(b) rejections of claims. The response (Remarks page 10) overcomes the 35 U.S.C. 112(b) rejection of claim 15. Applicant's amendments to the claims have overcome objections, the 35 U.S.C. 112(d) rejections, and the 35 U.S.C. 102(a)(2) rejections previously set forth in the Non-Final Office Action mailed December 17, 2025.
Claim Objections
Claim 1 is objected to because of the following informalities: the claim recites “wherein the controller is configured to internally measure condition features of the non- volatile memory…and wherein the prediction buffer is configured to select said one of the N sets based on condition features of the non-volatile memory.” The claim should recite “wherein the prediction buffer is configured to select said one of the N sets based on the condition features of the non-volatile memory.” Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Amended claim 1 recites “wherein the controller is configured to internally measure condition features of the non- volatile memory or operation features of the non-volatile memory.” The instant specification does not support the amended claim limitation. Applicant points to Figure 1 and paragraphs [0031]-[0032], [0035], [0047], and [0053]-[0054] as providing support for the amendment. However, there is no discussion in the cited paragraphs, or in the remaining paragraphs of the specification, of a controller internally measuring condition features, operation features or any other type of feature. Additionally, paragraph [0031] discloses “the feature collection block 112 may receive as inputs (A) condition features of the non-volatile memory 120, for example, from the non-volatile memory 120, (B) operation features of the non-volatile memory 120, for example, from the control engine 116.” Paragraph [0038] further discloses “the control engine 116 may receive as inputs…(B) the condition features of the non-volatile memory 120 from non-volatile memory 120. In an embodiment, the control engine 116 may provide as outputs…(B) the operation features of the non-volatile memory 120 to the feature collection block 112.” A search of the specification did not reveal any instances of the word “measure” or its variations. Therefore the claim limitation is determined to be new matter. Claim 17 recites “measuring, using the controller internally, condition features of the non-volatile memory or operation features of the non-volatile memory” and rejected under the same rationale. Claims 2-4, 8-16, and 19 are rejected based on their dependency from claims 1 and 17.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 8-17, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Kachare et al. (US 2019/0317901) and Yoon et al. (US 2022/0199185).
Regarding claim 1, Kachare et al. disclose:
A controller, configured to generate M configuration parameters using an artificial neural network, M being a positive integer (FIG. 2 Output Layer 221; [0032] Examples of the prediction outputs 172 that are fed to the FTL 112 include, but are not limited to, an LBA, an LBA cluster, a type of a host access (e.g., host commands, read/write/flush etc.), an imminent idle gap, an imminent access volume (e.g., b/w, size etc.), and other information regarding the DNN module 161), and configured to use the M configuration parameters in interacting with a non-volatile memory ([0036] prediction output 172 from the DNN module 161 of the next chunk number to be accessed may be fed to the FTL 112 to schedule prefetching, garbage collection, and other operations on the corresponding chunk and the erase block),
wherein at least one of the M configuration parameters is not a threshold voltage for reading the non-volatile memory ([0032]), and
wherein the controller (FIG. 1 SSD controller 110; [0019] a deep neural network (DNN)-based approach) is configured to implement the artificial neural network (FIG. 1 DNN(s) 161);
wherein the controller further comprises a prediction buffer ([0029] results of the DNN predictions may be stored in a prediction table 162 that associates one or more past host I/O request and a current host I/O request to a predicted host I/O request that may follow the current host I/O request. The format of the prediction table 162 may vary depending on the system configuration and the target application(s); [0053] one or more DNN modules may include a prediction table that stores a plurality of prediction outputs based on the current I/O request) configured to:
(A) store N sets of configuration parameters generated by the artificial neural network, N being an integer greater than 1 ([0060] The one or more prediction outputs may include one or more of an LBA, an LBA cluster, a type of a host access, an imminent idle gap, an imminent access volume), and
(B) select one the N sets as the M configuration parameters ([0032] Examples of the prediction outputs 172 that are fed to the FTL 112 include, but are not limited to, an LBA, an LBA cluster, a type of a host access (e.g., host commands, read/write/flush etc.), an imminent idle gap, an imminent access volume (e.g., b/w, size etc.), and other information regarding the DNN module 161);
wherein the controller (FIG. 1 DNN module 161 of controller 110) is configured to internally measure condition features of the non-volatile memory or operation features of the non-volatile memory ([0031] The DNN module 161 may detect the host access patterns using not only the current input vector but also a plurality of input vectors that are received prior to the current input vector as the host access patterns may be identified over the plurality of input vectors); and
wherein the prediction buffer is configured to select said one of the N sets based on condition features of the non-volatile memory ([0031] The input vector 171 may include various inputs regarding the host accesses that can be used to identify access patterns to the flash media 151. The DNN module 161 may detect the host access patterns using not only the current input vector but also a plurality of input vectors that are received prior to the current input vector as the host access patterns may be identified over the plurality of input vectors. Examples of entries included in the input vector 171 are, but not limited to, an LBA, a range of LBA(es), a length of a host access (read/write), a number of a host access (read/write), a namespace ID, a host ID (e.g., a host NVMe qualified name (NQN)), a command opcode (OPC), an I/O type as indicated by the command opcode (e.g., read/write/flush etc.), a stream ID, an NVM set ID, a time delta and/or a time stamp, and other relevant storage parameters) or based on (A) the operation features of the non-volatile memory ([0031])…
Kachare et al. do not appear to explicitly teach “(B) decoding status features of a decoder of the controller.” However, Yoon et al. disclose:
(B) decoding status features of a decoder of the controller (FIG. 20 IDAT ECC decoding information; [0034] the ECC decoding information may be generated corresponding to the plurality of read operations. For example, two or more ECC decoding information may be generated corresponding to each of the plurality of read operations when two or more read operations are performed; [0108] The ECC engine 450 for error correction may perform an ECC encoding and an ECC decoding by or using a coded modulation).
Kachare et al. and Yoon et al. are analogous art because Kachare et al. teach optimizing performance of solid-state drives using neural networks and Yoon et al. teach predicting remaining lifetime of nonvolatile memory.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Kachare et al. and Yoon et al. before him/her, to modify the teachings of Kachare et al. with the Yoon et al. teachings of ECC decoding. Including ECC decoding status features as a basis for selecting configuration would provide an indicator remaining lifetime of the non-volatile memory.
Regarding claim 2, Kachare et al. further disclose:
The controller of claim 1, wherein the non-volatile memory is a flash memory (FIG. 1 flash 151).
Regarding claim 3, Kachare et al. further disclose:
The controller of claim 1, wherein the artificial neural network is a feed-forward neural network, a reinforcement learning network, a long short-term memory network ([0023] a deep neural network (DNN)-based scheme such as a long short term memory (LSTM) network), a recurrent neural network ([0034] the present system and method can operate a long short term memory (LSTM) network. The LSTM network includes a plurality of LSTM units (or blocks) to form layers of a recurrent neural network (RNN).), or any combinations thereof.
Regarding claim 8, Kachare et al. further disclose:
The controller of claim 1, wherein the condition features of the non-volatile memory are selected from a group consisting of WE (write erase) count, data retention condition, data-read temperature, data-write temperature, block status, plane index, block index, wordline index, page index, and any combinations thereof ([0031] The input vector 171 may include various inputs regarding the host accesses that can be used to identify access patterns to the flash media 151. The DNN module 161 may detect the host access patterns using not only the current input vector but also a plurality of input vectors that are received prior to the current input vector as the host access patterns may be identified over the plurality of input vectors. Examples of entries included in the input vector 171 are, but not limited to, an LBA, a range of LBA(es), a length of a host access (read/write), a number of a host access (read/write), a namespace ID, a host ID (e.g., a host NVMe qualified name (NQN)), a command opcode (OPC), an I/O type as indicated by the command opcode (e.g., read/write/flush etc.), a stream ID, an NVM set ID, a time delta and/or a time stamp, and other relevant storage parameters; It would be obvious to one skilled in the art before the effective filing date of the claimed invention that other relevant storage parameters would include the claimed elements).
Regarding claim 9, Kachare et al. further disclose:
The controller of claim 1, wherein the operation features of the non-volatile memory are selected from a group consisting of read time of a page, program time of a page, erase time of a block, 1s count of raw data of a page, and any combinations thereof ([0031] The input vector 171 may include various inputs regarding the host accesses that can be used to identify access patterns to the flash media 151. The DNN module 161 may detect the host access patterns using not only the current input vector but also a plurality of input vectors that are received prior to the current input vector as the host access patterns may be identified over the plurality of input vectors. Examples of entries included in the input vector 171 are, but not limited to, an LBA, a range of LBA(es), a length of a host access (read/write), a number of a host access (read/write), a namespace ID, a host ID (e.g., a host NVMe qualified name (NQN)), a command opcode (OPC), an I/O type as indicated by the command opcode (e.g., read/write/flush etc.), a stream ID, an NVM set ID, a time delta and/or a time stamp, and other relevant storage parameters; It would be obvious to one skilled in the art before the effective filing date of the claimed invention that other relevant storage parameters would include the claimed elements).
Regarding claim 10, Yoon et al. further disclose:
The controller of claim 1, wherein the decoding status features are selected from a group consisting of page decoding status vector, 1 to 0 error number array, 0 to 1 error number array, iteration number array, and any combinations thereof ([0141] the ECC decoding information may include the number of error bits that is calculated as a result of performing an ECC decoding on the read data; [0161] Input data (e.g., vector input data) IDAT whose length is i may be input to the input nodes).
Regarding claim 11, Kachare et al. further disclose:
The controller of claim 1, wherein inputs to the artificial neural network are selected from a group consisting of condition features of the non-volatile memory ([0031]), operation features of the non-volatile memory ([0031]), decoding status features of a decoder of the controller, and any combinations thereof.
Kachare et al. do not appear to explicitly teach “decoding status features of a decoder of the controller, and any combinations thereof.” However, Yoon et al. further disclose:
decoding status features of a decoder of the controller (FIG. 20 IDAT ECC decoding information; [0034] the ECC decoding information may be generated corresponding to the plurality of read operations. For example, two or more ECC decoding information may be generated corresponding to each of the plurality of read operations when two or more read operations are performed; [0108] The ECC engine 450 for error correction may perform an ECC encoding and an ECC decoding by or using a coded modulation),
Regarding claim 12, Kachare et al. further disclose:
The controller of claim 11, wherein the condition features of the non-volatile memory are selected from a group consisting of WE (write erase) count, data retention condition, data-read temperature, data-write temperature, block status, plane index, block index, wordline index, page index, and any combinations thereof ([0031] The input vector 171 may include various inputs regarding the host accesses that can be used to identify access patterns to the flash media 151. The DNN module 161 may detect the host access patterns using not only the current input vector but also a plurality of input vectors that are received prior to the current input vector as the host access patterns may be identified over the plurality of input vectors. Examples of entries included in the input vector 171 are, but not limited to, an LBA, a range of LBA(es), a length of a host access (read/write), a number of a host access (read/write), a namespace ID, a host ID (e.g., a host NVMe qualified name (NQN)), a command opcode (OPC), an I/O type as indicated by the command opcode (e.g., read/write/flush etc.), a stream ID, an NVM set ID, a time delta and/or a time stamp, and other relevant storage parameters; It would be obvious to one skilled in the art before the effective filing date of the claimed invention that other relevant storage parameters would include the claimed elements).
Regarding claim 13, Kachare et al. further disclose:
The controller of claim 11, wherein the operation features of the non-volatile memory are selected from a group consisting of read time of a page, program time of a page, erase time of a block, 1s count of raw data of a page, and any combinations thereof ([0031] The input vector 171 may include various inputs regarding the host accesses that can be used to identify access patterns to the flash media 151. The DNN module 161 may detect the host access patterns using not only the current input vector but also a plurality of input vectors that are received prior to the current input vector as the host access patterns may be identified over the plurality of input vectors. Examples of entries included in the input vector 171 are, but not limited to, an LBA, a range of LBA(es), a length of a host access (read/write), a number of a host access (read/write), a namespace ID, a host ID (e.g., a host NVMe qualified name (NQN)), a command opcode (OPC), an I/O type as indicated by the command opcode (e.g., read/write/flush etc.), a stream ID, an NVM set ID, a time delta and/or a time stamp, and other relevant storage parameters; It would be obvious to one skilled in the art before the effective filing date of the claimed invention that other relevant storage parameters would include the claimed elements).
Regarding claim 14, Yoon et al. further disclose:
The controller of claim 11, wherein the decoding status features are selected from a group consisting of page decoding status vector, 1 to 0 error number array, 0 to 1 error number array, iteration number array, and any combinations thereof ([0141] the ECC decoding information may include the number of error bits that is calculated as a result of performing an ECC decoding on the read data; [0161] Input data (e.g., vector input data) IDAT whose length is i may be input to the input nodes).
Regarding claim 16, Kachare et al. further disclose:
A system, comprising the controller of claim 1, wherein the system is a solid-state drive (SSD) ([0019] a solid-state drive (SSD)), a flash drive, a mother board, a processor, a computer, a server, a gaming device, or a mobile device.
Regarding claim 17, Kachare et al. disclose:
A method of using a controller, comprising:
generating with an artificial neural network implemented in the controller, M configuration parameters, M being a positive integer (FIG. 2 Output Layer 221; [0032] Examples of the prediction outputs 172 that are fed to the FTL 112 include, but are not limited to, an LBA, an LBA cluster, a type of a host access (e.g., host commands, read/write/flush etc.), an imminent idle gap, an imminent access volume (e.g., b/w, size etc.), and other information regarding the DNN module 161), and configured to use the M configuration parameters in interacting with a non-volatile memory ([0036] prediction output 172 from the DNN module 161 of the next chunk number to be accessed may be fed to the FTL 112 to schedule prefetching, garbage collection, and other operations on the corresponding chunk and the erase block), wherein at least one of the M configuration parameters is not a threshold voltage for reading a non-volatile memory ([0032]); and then
using, with the controller (FIG. 1 SSD controller 110; [0019] a deep neural network (DNN)-based approach), the M configuration parameters in interacting with the non-volatile memory ([0036] prediction output 172 from the DNN module 161 of the next chunk number to be accessed may be fed to the FTL 112 to schedule prefetching, garbage collection, and other operations on the corresponding chunk and the erase block);
wherein said generating the M configuration parameters comprises:
measuring, using the controller (FIG. 1 DNN module 161 of controller 110) internally, condition features of the non-volatile memory or operation features of the non-volatile memory ([0031] The DNN module 161 may detect the host access patterns using not only the current input vector but also a plurality of input vectors that are received prior to the current input vector as the host access patterns may be identified over the plurality of input vectors);
storing, in a prediction buffer of the controller, N sets of configuration parameters generated by the artificial neural network, with N being an integer greater than 1 ([0029]; [0060] The one or more prediction outputs may include one or more of an LBA, an LBA cluster, a type of a host access, an imminent idle gap, an imminent access volume); and
selecting, with the prediction buffer, one of the N sets as the M configuration parameters ([0032] Examples of the prediction outputs 172 that are fed to the FTL 112 include, but are not limited to, an LBA, an LBA cluster, a type of a host access (e.g., host commands, read/write/flush etc.), an imminent idle gap, an imminent access volume (e.g., b/w, size etc.), and other information regarding the DNN module 161);
wherein said selecting is based on the condition features of the non-volatile memory ([0031] The input vector 171 may include various inputs regarding the host accesses that can be used to identify access patterns to the flash media 151. The DNN module 161 may detect the host access patterns using not only the current input vector but also a plurality of input vectors that are received prior to the current input vector as the host access patterns may be identified over the plurality of input vectors. Examples of entries included in the input vector 171 are, but not limited to, an LBA, a range of LBA(es), a length of a host access (read/write), a number of a host access (read/write), a namespace ID, a host ID (e.g., a host NVMe qualified name (NQN)), a command opcode (OPC), an I/O type as indicated by the command opcode (e.g., read/write/flush etc.), a stream ID, an NVM set ID, a time delta and/or a time stamp, and other relevant storage parameters) or based on (A) the operation features of the non-volatile memory ([0031])…
Kachare et al. do not appear to explicitly teach “(B) decoding status features of a decoder of the controller.” However, Yoon et al. disclose:
(B) decoding status features of a decoder of the controller (FIG. 20 IDAT ECC decoding information; [0034] the ECC decoding information may be generated corresponding to the plurality of read operations. For example, two or more ECC decoding information may be generated corresponding to each of the plurality of read operations when two or more read operations are performed; [0108] The ECC engine 450 for error correction may perform an ECC encoding and an ECC decoding by or using a coded modulation).
The motivation for combining is based on the same rational presented for rejection of independent claim 1.
Regarding claim 19, Kachare et al. further disclose:
The method of claim 17, wherein the non-volatile memory is a flash memory (FIG. 1 flash 151).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Kachare et al. and Yoon et al. as applied to claim 1 above, and further in view of Zheng et al. (US 2023/0110401).
Regarding claim 4, Kachare et al. and Yoon et al. do not appear to explicitly teach while Zheng et al. disclose:
The controller of claim 1, wherein the controller is on a single semiconductor die ([0006] a System-on-Chip (SoC) is described that includes a media interface to access storage media of a storage system, a host interface to communicate with a host system, and a machine learning controller that is configured to implement a neural network).
Kachare et al., Yoon et al., and Zheng et al. are analogous art because Kachare et al. teach optimizing performance of solid-state drives using neural networks; Yoon et al. teach predicting remaining lifetime of nonvolatile memory; and Zheng et al. teach machine learning-enabled management of storage media access.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Kachare et al., Yoon et al., and Zheng et al. before him/her, to modify the combined teachings of Kachare et al. and Yoon et al. with the Zheng et al. teachings of controller on a semiconductor die because such a modification would have amounted to little more than combining "familiar elements according to known methods" and would have been obvious because it would have done "no more than yield predictable results." (MPEP 2143 I.A.) Including a controller on a semiconductor die would improve performance of the neural network.
Allowable Subject Matter
Claim 15 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims and rewritten to overcome the 35 U.S.C. 112(a) rejection.
Response to Arguments
Applicant's arguments filed March 17, 2026 have been fully considered but they are not persuasive.
Applicant argues that Kachare et al. do not disclose the new limitation “wherein the controller is configured to internally measure condition features of the non-volatile memory or operation features of the non-volatile memory” (Remarks page 11). The examiner disagrees. Kachare et al. disclose that the DNN module 161 of controller 110 may detect host access patterns using not only the current input vector but also a plurality of input vectors that are received prior to the current input vector as the host access patterns may be identified over the plurality of input vectors ([0031]). Therefore, Kachare et al. discloses the controller is internally measuring the host access patterns based on current inputs and previous inputs.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TRACY A WARREN whose telephone number is (571)270-7288. The examiner can normally be reached M-Th 7:30am-5pm, Alternate F.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Arpan P. Savla can be reached at 571-272-1077. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/TRACY A WARREN/Primary Examiner, Art Unit 2137
Prosecution Insights