DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
The amendment filed on 02/24/2026 has been entered. Claims 1, 4, 7, 12, 15-16, 18 and 20 have been amended. Claim 21 has been added. Claims 1-8 and 10-21 are pending.
Response to Arguments
Applicant’s arguments, see pages 8-12 of the Remarks, filed 02/24/2026, with respect to the rejection(s) of claim(s) 1-8 and 10-20 under 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Zhang et al (CN 202211058743 as US Pub. 20250218361).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-8, 10-14 and 16-21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US Pub. 20230260448) in view of Zhang et al (CN 202211058743 as US Pub. 20250218361).
Regarding claim 1, Lee discloses:
A display device, (at least refer to fig. 20 and paragraph 121. Describes a display device 700) comprising:
A display panel including a sub-pixel, (at least refer to fig. 20 and paragraph 122. Describes the display panel 710 may include a plurality of pixels PX); and
A display panel driver configured to drive the display panel, (at least refer to fig. 20 and paragraph 121. Describes a display device 700 according to embodiments may include a display panel 710, a data driver 720, a scan driver 730)
Wherein the sub-pixel includes: a driving transistor generating a driving current, the driving transistor including a control electrode, a first electrode and a second electrode, (at least refer to fig. 2, 16 and paragraph 69. Describes the first transistor T1 may be referred to as a driving transistor for driving the light emitting element EL. In some embodiments, the first transistor T1 may include a gate coupled to the first node N1, a first terminal (e.g., a drain) coupled to a first power supply voltage line ELVDDL for transferring a first power supply voltage ELVDD (e.g., a high-power supply voltage), and a second terminal (e.g., the source) coupled to the second node N);
A storage capacitor connected between the control electrode of the driving transistor and the second electrode of the driving transistor, (at least refer to fig. 2, 16 and paragraph 69. Describes the first capacitor Cst may be coupled between the first node N1 and the second node N2);
A write transistor connected between a data line and the control electrode of the driving transistor, the write transistor writing a data voltage to the storage capacitor in response to a write gate signal, (at least refer to fig. 2, 16 and paragraph 70. Describes the first capacitor Cst may be referred to as a storage capacitor that stores a data voltage transferred from a data line DL through the second transistor T2);
A first emission transistor connected between a first power voltage line and the first electrode of the driving transistor, the first emission transistor providing a first power voltage to the first electrode of the driving transistor in response to a first emission signal, (at least refer to fig. 16 and paragraph 112. Describes the seventh transistor T7 disposed between a first power supply voltage line ELVDDL and a first terminal of the first transistor T1);
A hold capacitor connected between the first power voltage line and the second electrode of the driving transistor, (at least refer to fig. 2, 16 and paragraph 78. Describes the second capacitor Chold may be coupled between a first power supply voltage line ELVDDL and a second node N2);
A light emitting element connected to the driving transistor, (at least refer to fig. 2, 16 and paragraph 74. Describes the light emitting element EL may emit light based on the light emission current generated by the first transistor T1) and
A first initialization transistor connected between a first initialization voltage line and the light emitting element, the first initialization transistor providing a first initialization voltage to the light emitting element in response to an initialization gate signal, (at least refer to fig. 2, 16 and paragraph 89. Describes a sixth transistor T6 may transfer the initialization voltage VINT to an anode of the light emitting element EL in response to the third signal GI having the active level)
Wherein the first emission signal has an active level during a first portion of first periods within one frame and has the active level during second periods subsequent to the first periods, (at least refer to fig. 16-17 and paragraph 114. Describes the fifth signal EM2 may have an active level (e.g., a high level) in a threshold voltage compensation period VCP, may have the active level in a current characteristic compensation period CCP, and may have the active level in an emission period EP), and
Lee does not disclose:
Wherein the initialization gate signal applied to the first initialization transistor and the write gate signal applied to the write transistor have active levels at the same time of at least one of the first periods.
Zhang teaches:
Wherein the initialization gate signal applied to the first initialization transistor and the write gate signal applied to the write transistor have active levels at the same time of at least one of the first periods, (at least refer to fig. 5-7 and paragraph 60. Describes Phase One S1: Under a condition that the scan signal Scan(n−2) and the scan signal Scan(n) are at a high potential, the write-in transistor T2 and the second initialization transistor T6 are turned on, and the low potential of the data signal Data and the second initialization signal respectively reset nodes Q and C).
The two references are analogous art because they are related with the same field of invention of display panel.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the initialization gate signal and write gate signal to an active level in a same time for as taught by Zhang with the display device as disclose by Lee. The motivation to combine the reference of Zhang is to stabilize the potential of the source or drain of the driving transistor and improve the flickering phenomenon caused by the periodic changes in the potentials of the source and/or drain of the driving transistor.
Regarding claim 16, Lee discloses:
A method of driving a display device, (at least refer to fig. 3, 17 and paragraphs 87, 111. Describes an example of an operation of a pixel of a display device) the method comprising:
Writing a data voltage to a sub-pixel in a first sub-period, (at least refer to fig. 3, 17 and paragraph 71. Describes the second transistor T2 may transfer a data voltage provided from the data line DL to the first node N1 in response to a first signal GW);
Providing the sub-pixel with a first emission signal having an active level, thereby allowing a light emitting element of the sub-pixel to emit light in a second period subsequent to the first sub-period, (at least refer to fig. 17 and paragraph 114. Describes accordingly, the seventh transistor T7 may be turned on in response to the fifth signal EM2 having the active level in the emission period EP to couple the first terminal of the first transistor T1 to the first power supply voltage line ELVDDL); and
Providing the sub-pixel with the first emission signal having the active level, thereby allowing the light emitting element to emit light in a second period subsequent to the second sub-period, (at least refer to fig. 11, 17 and paragraphs 98, 114. Describes accordingly, the seventh transistor T7 may be turned on in response to the fifth signal EM2 having the active level in the emission period EP to couple the first terminal of the first transistor T1 to the first power supply voltage line ELVDDL. Para. 98, describes: the fifth transistor T5 may be turned on in response to the fourth signal EM having the active level to couple or connect the second node N2 to the anode of the light emitting element EL. Further, the first transistor T1 may be turned on based on the voltage stored between the first and second electrodes of the first capacitor Cst to provide the light emission current IEL to the light emitting element EL. The light emitting element EL may emit light based on the light emission current IEL)
Wherein the sub-pixel includes a first initialization transistor connected between a first initialization voltage line and the light emitting element, the first initialization transistor providing a first initialization voltage to the light emitting element in response to an initialization gate signal, (at least refer to fig. 2, 16 and paragraph 89. Describes a sixth transistor T6 may transfer the initialization voltage VINT to an anode of the light emitting element EL in response to the third signal GI having the active level)
Lee does not disclose:
Wherein the initialization gate signal and a write gate signal concurrently have active levels.
Park teaches:
Wherein the initialization gate signal and a write gate signal concurrently have active levels, (at least refer to fig. 5-7 and paragraph 60. Describes Phase One S1: Under a condition that the scan signal Scan(n−2) and the scan signal Scan(n) are at a high potential, the write-in transistor T2 and the second initialization transistor T6 are turned on, and the low potential of the data signal Data and the second initialization signal respectively reset nodes Q and C).
Regarding the rejection of claim 16, refer to the motivation of claim 1.
Regarding claim 21, Lee discloses:
An electronic device, (at least refer to fig. 20 and paragraph 121. Describes a display device 700) comprising:
A processor connected to a display device through buses, (at least refer to fig. 21 and paragraph 128-129. Describes an electronic device 1100 may include a processor 1110, a memory device 1120, a storage device 1130, an input/output (“I/O”) device 1140, a power supply 1150, and a display device 1160. Para. 129, describes: The processor 1110 may be coupled to other components via an address bus, a control bus, a data bus, etc.);
A display device connected to the processor through the buses to display an image corresponding to visual information of the electronic device, (at least refer to fig. 20-21 and paragraph 126, 131. Describes the controller 750 may generate the output image data ODAT, the data control signal DCTRL, the scan control signal SCTRL and the emission control signal EMCTRL based on the input image data IDAT and the control signal CTRL. Para. 131, describes: The display device 1160 may be coupled to other components through the buses or other communication links); and
Wherein the display device comprises: a display panel including a sub-pixel, (at least refer to fig. 20 and paragraph 122. Describes the display panel 710 may include a plurality of pixels PX); and
A display panel driver configured to drive the display panel, wherein the sub-pixel includes: a driving transistor generating a driving current, the driving transistor including a control electrode, a first electrode and a second electrode, (at least refer to fig. 2, 16 and paragraph 69. Describes the first transistor T1 may be referred to as a driving transistor for driving the light emitting element EL. In some embodiments, the first transistor T1 may include a gate coupled to the first node N1, a first terminal (e.g., a drain) coupled to a first power supply voltage line ELVDDL for transferring a first power supply voltage ELVDD (e.g., a high-power supply voltage), and a second terminal (e.g., the source) coupled to the second node N);
A storage capacitor connected between the control electrode of the driving transistor and the second electrode of the driving transistor, (at least refer to fig. 2, 16 and paragraph 69. Describes the first capacitor Cst may be coupled between the first node N1 and the second node N2);
A write transistor connected between a data line and the control electrode of the driving transistor, the write transistor writing a data voltage to the storage capacitor in response to a write gate signal, (at least refer to fig. 2, 16 and paragraph 70. Describes the first capacitor Cst may be referred to as a storage capacitor that stores a data voltage transferred from a data line DL through the second transistor T2);
A first emission transistor connected between a first power voltage line and the first electrode of the driving transistor, the first emission transistor providing a first power voltage to the first electrode of the driving transistor in response to a first emission signal, (at least refer to fig. 16 and paragraph 112. Describes the seventh transistor T7 disposed between a first power supply voltage line ELVDDL and a first terminal of the first transistor T1);
A hold capacitor connected between the first power voltage line and the second electrode of the driving transistor, (at least refer to fig. 2, 16 and paragraph 78. Describes the second capacitor Chold may be coupled between a first power supply voltage line ELVDDL and a second node N2);
A light emitting element connected to the driving transistor, (at least refer to fig. 2, 16 and paragraph 74. Describes the light emitting element EL may emit light based on the light emission current generated by the first transistor T1) and
A first initialization transistor connected between a first initialization voltage line and the light emitting element, the first initialization transistor providing a first initialization voltage to the light emitting element in response to an initialization gate signal, (at least refer to fig. 2, 16 and paragraph 89. Describes a sixth transistor T6 may transfer the initialization voltage VINT to an anode of the light emitting element EL in response to the third signal GI having the active level)
Wherein the first emission signal has an active level during a first portion of first periods within one frame and has the active level during second periods subsequent to the first periods, (at least refer to fig. 16-17 and paragraph 114. Describes the fifth signal EM2 may have an active level (e.g., a high level) in a threshold voltage compensation period VCP, may have the active level in a current characteristic compensation period CCP, and may have the active level in an emission period EP) and
Wherein the initialization gate signal applied to the first initialization transistor and the write gate signal applied to the write transistor have active levels at the same time of at least one of the first periods.
Lee does not disclose:
Wherein the initialization gate signal applied to the first initialization transistor and the write gate signal applied to the write transistor have active levels at the same time of at least one of the first periods.
Park teaches:
Wherein the initialization gate signal applied to the first initialization transistor and the write gate signal applied to the write transistor have active levels at the same time of at least one of the first periods, (at least refer to fig. 5-7 and paragraph 60. Describes Phase One S1: Under a condition that the scan signal Scan(n−2) and the scan signal Scan(n) are at a high potential, the write-in transistor T2 and the second initialization transistor T6 are turned on, and the low potential of the data signal Data and the second initialization signal respectively reset nodes Q and C).
Regarding the rejection of claim 21, refer to the motivation of claim 1.
Regarding claim 2, Lee discloses:
Wherein the first emission signal is toggled between the active level and an inactive level in each of the first periods, (at least refer to fig. 17 and paragraph 114. Describes the fifth signal EM2 may have an inactive level (e.g., a low level) in an initialization period IP, may have an active level (e.g., a high level) in a threshold voltage compensation period VCP, may have the inactive level in a data writing period WP, may have the active level in a current characteristic compensation period CCP, and may have the active level in an emission period EP).
Regarding claim 3, Lee discloses:
Wherein the first periods include a first sub-period in which the data voltage is written to the sub-pixel and a second sub-period different from the first sub-period, (at least refer to fig. 17 and paragraph 114. Describes accordingly, the seventh transistor T7 may be turned off in response to the fifth signal EM2 having the inactive level in the data writing period WP to separate the first terminal of the first transistor T1 from the first power supply voltage line ELVDDL, may be turned on in response to the fifth signal EM2 having the active level in the current characteristic compensation period CCP to couple the first terminal of the first transistor T1 to the first power supply voltage line ELVDDL).
Regarding claim 4, Lee discloses:
Wherein the initialization gate signal has the active level in a second portion of the second sub-period, in which the first emission signal has an inactive level, (at least refer to fig. 16-17 and paragraphs 89, 114. Describes in the initialization period IP, a second signal GR and a third signal GI may have an active level (e.g., a high level), and a first signal GW and a fourth signal EM and may have an inactive level (e.g., a low level). Para. 114, describes: the fifth signal EM2 may have an inactive level (e.g., a low level) in an initialization period IP).
Regarding claim 5, Lee discloses:
Wherein the initialization gate signal has an inactive level in the first portion of the second sub-period, (at least refer to fig. 16-17 and paragraph 98. Describes In the emission period EP, the fourth signal EM may have the active level, and the first signal GW, the second signal GR and the third signal GI may have the inactive level).
Regarding claim 6, Lee discloses:
Wherein the initialization gate signal has an active level in the first portion of the second sub-period, (at least refer to fig. 15, 19 and paragraph 110. Describes the sixth transistor T6′ may be turned on in response to the second signal GR having the active level during the initialization period IP and the threshold voltage compensation period VCP, and thus the anode of the light emitting element EL may be sufficiently initialized).
Regarding claim 7, Lee discloses:
Wherein each of the first periods include a first sub-period in which the data voltage is written to the sub-pixel and a second sub-period different from the first sub-period, (at least refer to fig. 17 and paragraph 114. Describes accordingly, the seventh transistor T7 may be turned off in response to the fifth signal EM2 having the inactive level in the data writing period WP to separate the first terminal of the first transistor T1 from the first power supply voltage line ELVDDL, may be turned on in response to the fifth signal EM2 having the active level in the current characteristic compensation period CCP to couple the first terminal of the first transistor T1 to the first power supply voltage line ELVDDL)
Wherein the initialization gate signal has the active level in a second portion of at least one of the second sub-periods in which the first emission signal has an inactive level, (at least refer to fig. 16-17 and paragraphs 89, 114. Describes in the initialization period IP, a second signal GR and a third signal GI may have an active level (e.g., a high level), and a first signal GW and a fourth signal EM and may have an inactive level (e.g., a low level). Para. 114, describes: the fifth signal EM2 may have an inactive level (e.g., a low level) in an initialization period IP).
Regarding claim 8, Lee discloses:
Wherein the first periods include a first sub-period in which the data voltage is written to the sub-pixel and a second sub-period different from the first sub-period, (at least refer to fig. 17 and paragraph 114. Describes accordingly, the seventh transistor T7 may be turned off in response to the fifth signal EM2 having the inactive level in the data writing period WP to separate the first terminal of the first transistor T1 from the first power supply voltage line ELVDDL, may be turned on in response to the fifth signal EM2 having the active level in the current characteristic compensation period CCP to couple the first terminal of the first transistor T1 to the first power supply voltage line ELVDDL) and
Wherein the write gate signal has an active level in at least a portion of the first sub-period, and has an inactive level in the second sub-period and the second periods, (at least refer to fig. 16-17 and paragraphs 93, 98. Describes in the data writing period WP, the first signal GW may have the active level, and the second signal GR, the third signal GI and the fourth signal EM may have the inactive level. Para. 98, describes: In the emission period EP, the fourth signal EM may have the active level, and the first signal GW, the second signal GR and the third signal GI may have the inactive level).
Regarding claim 10, Lee discloses:
Wherein the sub-pixel further includes a reference transistor connected between a reference voltage line and the control electrode of the driving transistor, the reference transistor providing a reference voltage to the storage capacitor in response to a reference gate signal, (at least refer to fig. 2, 17 and paragraph 72. Describes the third transistor T3 may include a gate for receiving the second signal GR, a first terminal for receiving the reference voltage VREF, and a second terminal coupled to the first node N1).
Regarding claim 11, Lee discloses:
Wherein the first periods include a first sub-period in which the data voltage is written to the sub-pixel and a second sub-period different from the first sub-period, (at least refer to fig. 17 and paragraph 114. Describes accordingly, the seventh transistor T7 may be turned off in response to the fifth signal EM2 having the inactive level in the data writing period WP to separate the first terminal of the first transistor T1 from the first power supply voltage line ELVDDL, may be turned on in response to the fifth signal EM2 having the active level in the current characteristic compensation period CCP to couple the first terminal of the first transistor T1 to the first power supply voltage line ELVDDL) and
Wherein the reference gate signal has an active level in at least a portion of the first sub-period, and has an inactive level in the second sub-period and the second periods, (at least refer to fig. 16-17 and paragraphs 90, 98. Describes In the threshold voltage compensation period VCP, the second signal GR may have the active level, and the first signal GW, the third signal GI and the fourth signal EM may have the inactive level. Para. 98, describes: In the emission period EP, the fourth signal EM may have the active level, and the first signal GW, the second signal GR and the third signal GI may have the inactive level).
Regarding claim 12, Lee discloses:
Wherein the initialization gate signal has the active level in a period in which the first emission signal and the reference gate signal have the active level, (at least refer to fig. 15, 17, 19 and paragraphs 114, 119. Describes Accordingly, the seventh transistor T7 may be turned on in response to the fifth signal EM2 having the active level in the threshold voltage compensation period VCP to couple the first terminal of the first transistor T1 to the first power supply voltage line ELVDDL. Para. 119, describes: The sixth transistor T6′ may be turned on in response to the second signal GR having an active level during an initialization period and a threshold voltage compensation period VCP, and thus an anode of the light emitting element EL may be sufficiently initialized).
Regarding claim 13, Lee discloses:
Wherein the sub-pixel further includes a second emission transistor connected between the driving transistor and the light emitting element, the second emission transistor connecting the driving transistor to the light emitting element in response to a second emission signal, (at least refer to fig. 2, 16 and paragraph 75. Describes the fifth transistor T5 may include a gate for receiving the fourth signal EM, a first terminal coupled to the second node N2, and a second terminal coupled to the anode of the light emitting element EL).
Regarding claim 14, Lee discloses:
Wherein the first periods include a first sub-period in which the data voltage is written to the sub-pixel and a second sub-period different from the first sub-period, (at least refer to fig. 17 and paragraph 114. Describes accordingly, the seventh transistor T7 may be turned off in response to the fifth signal EM2 having the inactive level in the data writing period WP to separate the first terminal of the first transistor T1 from the first power supply voltage line ELVDDL, may be turned on in response to the fifth signal EM2 having the active level in the current characteristic compensation period CCP to couple the first terminal of the first transistor T1 to the first power supply voltage line ELVDDL) and
Wherein the second emission signal has an inactive level in at least a portion of the first sub-period, and has an active level in the second sub-period and the second periods, (at least refer to fig. 3, 17 and paragraphs 91, 98. Describes in the threshold voltage compensation period VCP, the fifth transistor T5 may be turned off in response to the fourth signal EM having the inactive level to separate the second node N2 from the anode of the light emitting element EL. Para. 98, describes: In the emission period EP, the fourth signal EM may have the active level, and the first signal GW, the second signal GR and the third signal GI may have the inactive level).
Regarding claim 17, Lee discloses:
Wherein the sub-pixel, (at least refer to fig. 20 and paragraph 122. Describes the display panel 710 may include a plurality of pixels PX) includes:
A driving transistor generating a driving current, (at least refer to fig. 2, 16 and paragraph 69. Describes the first transistor T1 may be referred to as a driving transistor for driving the light emitting element EL. In some embodiments, the first transistor T1 may include a gate coupled to the first node N1, a first terminal (e.g., a drain) coupled to a first power supply voltage line ELVDDL for transferring a first power supply voltage ELVDD (e.g., a high-power supply voltage), and a second terminal (e.g., the source) coupled to the second node N);
A storage capacitor connected to a control electrode of the driving transistor, (at least refer to fig. 2, 16 and paragraph 69. Describes the first capacitor Cst may be coupled between the first node N1 and the second node N2);
A write transistor writing the data voltage to the storage capacitor in response to a write gate signal, (at least refer to fig. 2, 16 and paragraph 70. Describes the first capacitor Cst may be referred to as a storage capacitor that stores a data voltage transferred from a data line DL through the second transistor T2);
A first emission transistor providing a first power voltage to a first electrode of the driving transistor in response to the first emission signal, (at least refer to fig. 16 and paragraph 112. Describes the seventh transistor T7 disposed between a first power supply voltage line ELVDDL and a first terminal of the first transistor T1); and
A hold capacitor including a first electrode receiving the first power voltage and a second electrode connected to a second electrode of the driving transistor, (at least refer to fig. 2, 16 and paragraph 78. Describes the second capacitor Chold may be coupled between a first power supply voltage line ELVDDL and a second node N2) and
Wherein the light emitting element emits light by receiving the driving current from the driving transistor, (at least refer to fig. 2, 16 and paragraph 74. Describes the light emitting element EL may emit light based on the light emission current generated by the first transistor T1).
Regarding claim 18, Lee discloses:
Providing the sub-pixel with the first emission signal toggled between the active level and an inactive level in a second sub-period subsequent to the second period, (at least refer to fig. 17 and paragraph 114. Describes accordingly, the seventh transistor T7 may be turned on in response to the fifth signal EM2 having the active level in the current characteristic compensation period CCP to couple the first terminal of the first transistor T1 to the first power supply voltage line ELVDDL, and may be turned on in response to the fifth signal EM2 having the active level in the emission period EP to couple the first terminal of the first transistor T1 to the first power supply voltage line ELVDDL); and
Applying the first initialization voltage to the light emitting element in a portion of the second sub-period in which the first emission signal has an inactive level, (at least refer to fig. 16-17 and paragraphs 89, 114. Describes in the initialization period IP, a second signal GR and a third signal GI may have an active level (e.g., a high level), and a first signal GW and a fourth signal EM and may have an inactive level (e.g., a low level). Para. 114, describes: the fifth signal EM2 may have an inactive level (e.g., a low level) in an initialization period IP).
Regarding claim 19, Lee discloses:
Applying the first initialization voltage to the light emitting element in a portion of the second sub-period in which the first emission signal has an active level, (at least refer to fig. 17 and paragraph 114. Describes accordingly, the seventh transistor T7 may be turned on in response to the fifth signal EM2 having the active level in the emission period EP to couple the first terminal of the first transistor T1 to the first power supply voltage line ELVDDL).
Regarding claim 20, Lee discloses:
Wherein, when a data voltage is written to the sub-pixel, the first initialization voltage is applied to the light emitting element, (at least refer to fig. 16-17 and paragraph 89. Describes a sixth transistor T6 may transfer the initialization voltage VINT to an anode of the light emitting element EL in response to the third signal GI having the active level. Accordingly, the anode of the light emitting element EL may be initialized based on the initialization voltage VINT).
Allowable Subject Matter
Claim 15 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/IFEDAYO B ILUYOMADE/Primary Examiner, Art Unit 2624 03/16/2026