DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Species II (fig. 2) directed to claims 1-8 & 10-17 in the reply filed on 8/11/2026 is acknowledged. The traversal is on the ground(s) that “While the Office alleges a serious burden imposed by concurrent examination of all enumerated Species, a review of the claims and the Species Election Requirement suggests that this would not be the case. For, example, a search for flexible circuit board, as recited in independent claims 1 and 10, is certain to include reference to several configurations, shapes, and regions of conductive layers, as shown in FIGS. 1-4”.
This is not found persuasive because as specified/described in the Restriction dated 8/30/2026 each of the Species 1-7 has distinct structural features that do not overlap and would require distinct individual searches and search strategies. Applicants own specification in the “Brief Description of the Drawings” states, “first embodiment”, “second embodiment”, “other embodiment” and “yet another embodiment” and then described each of the species with different structural features in the specification. There will be a burden to search each of these embodiments.
Additionally Examiner points to claims 5 and 12 both discussing “a fourth region”. This fourth region is only discussed in conjuncture with figure 4 (specie 7), which is a non-elected species therefore claims 5 & 12, and 6 & 13 (which is dependent off of claims 5 and 12) will be considered withdrawn.
The requirement is still deemed proper and is therefore made FINAL.
Claims 5-6, 9 and 12-13 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected subject matter
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 and 3 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Runyon et al. (US PG. Pub. 2005/0252681).
Regarding claim 1 – Runyon teaches a flexible circuit board (fig. 1; The preamble of the claim(s) is not considered a limitation and is of no significance to claim construction. See Pitney Bowes, Inc. v. Hewlett-Packard Co., 182 F.3d 1298, 1305, 51 USPQ2d 1161, 1165 (Fed. Cir. 1999). See MPEP § 2111.02.) for chip integration, comprising: an insulating substrate (16 [paragraph 0009] Runyon states, “printed circuit board 16”); a conductive copper layer (14 [paragraph 0009] Runyon states, “substrate 14…substrate that is formed of copper”), having a patterned circuit (see “patterned circuit” shown in figure 1) and located on the insulating substrate (16), the conductive copper layer (14) having a first region (24 [paragraph 0010] Runyon states, “central section 24”) and a second region (26 [paragraph 0011] Runyon states, “perimeter 26 of substrate 14”) electrically connected with each other (see fig. 1); a first tin layer (30 [paragraph 0011] Runyon states, “solder joint 30…solder alloy is composed of near-eutectic tin-lead alloy”), located above the first region (24) of the conductive copper layer(14), the first tin layer (30) having a first tin thickness (t1); and a second tin layer (34), located above the second region (26) of the conductive copper layer (14), the second tin layer (30) having a second tin thickness (t2); wherein the first tin layer (32) has a first tin surface (top surface of tin layer 30 shown to be in contact with component 12) opposite to and not in contact with the conductive copper layer (14; claimed structure shown in figure 1), the second tin layer (34) has a second tin surface (top surface of tin layer 30) opposite to and not in contact with the conductive copper layer (14), and the first tin surface and the second tin surface are substantially level (figure 1 shows the top surface of the tin layer 30 being “substantially level”), wherein the first tin thickness (t1) is less than the second tin thickness (t2 [paragraph 0011] Runyon states, “central thickness t1 is less than the perimeter thickness t2”).
Regarding claim 3 – Runyon teaches the flexible circuit board according to claim 1, wherein the conductive copper layer (fig. 1, 14) located in the first region (24) has a first copper thickness (h1), the conductive copper layer (14) located in the second region (26) has a second copper thickness (h2), and the first copper thickness (h1) is greater than the second copper thickness (h2 [paragraph 0010] Runyon states, “central section 24 of substrate 14 has a height h1 perpendicular to board 16 that is greater than the height h2 of the perimeter”).
Claim(s) 10 and 11 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tsukamoto (US PG. Pub. 2017/0372997)
Regarding claim 10 – Tsukamoto teaches a flexible circuit board for chip integration (fig. 1A-1B; The preamble of the claim(s) is not considered a limitation and is of no significance to claim construction. See Pitney Bowes, Inc. v. Hewlett-Packard Co., 182 F.3d 1298, 1305, 51 USPQ2d 1161, 1165 (Fed. Cir. 1999). See MPEP § 2111.02.), comprising: an insulating substrate (14 [paragraph 0029] Tsukamoto states, “insulating layer 14”); a conductive copper layer (wiring layer 15 including metal layer 32 [paragraph 0055] Tsukamoto states, “As the materials of the metal film 31 and the metal layers 32 and 33, for example, copper and copper alloys can be used”), having a patterned circuit (see pattern shown of wiring layer 1A) and located on the insulating substrate (14), the conductive copper layer (32) having a thickness ranging between 2 μm and 20 μm ([paragraph 0029] Tsukamoto states, “the thickness of the wiring layer 15 can be set to, for example, about 2 μm to 5 μm”), the conductive copper layer (32) having a first region (thickest region of 15) and a second region (peripheral region of 15) electrically connected with each other (see figs. 1A-1B), wherein the conductive copper layer (32) located in the first region has a first copper thickness, the conductive copper layer (32) located in the second region has a second copper thickness, and the first copper thickness is greater than the second copper thickness (claimed structure shown in annotated figure 1B below).
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Regarding claim 11 – Furusawa teaches the flexible circuit board according to claim 10, wherein the conductive copper layer (figs. 1A-1B, 32) further has a third region (see inclined region in annotated figure 1B above), the third region is located between the first region and the second region, and a thickness of the conductive copper layer (32) located in the third region is between the first copper thickness and the second copper thickness (claimed structure shown in figure 1B).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 7 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Runyon et al. in view of Cho et al. (US PG. Pub. 2016/0044790).
Regarding claim 7 – Runyon teaches the flexible circuit board according to claim 1, but fails to teach wherein the first region is located in a bendable region of the flexible circuit board.
Cho teaches a flexible circuit board (fig. 1B, 20 [paragraph 0073] Cho state, “module substrate 20 may be flexible”) having a conductive layer (26 [paragraph 0073] Cho states, “The pads 25 and 26 may include a conductive material”) with a first region (central region of the conductive layer 26) wherein the first region is located in a bendable region (22 [paragraph 0073] Cho states, “curved portion 22”)of the flexible circuit board (20).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit board having a copper conductive layer with a first region as taught by Runyon with the first region of the conductive layer being located in a bendable region of a flexible circuit board as taught by Cho because Cho states, “as multimedia technology develops, demand for flexible electronic devices is increasing. Thus, mounting a device (e.g., an organic light emitting display (OLED) device, a liquid crystal display (LCD) device, a plasma display panel (PDP), a thin-film transistor (TFT), a micro-processor, and/or random access memory (RAM)) on a flexible substrate is desired.” [paragraph 0004].
Regarding claim 17 – Runyon teaches an electronic device, comprising: the flexible circuit board according to claim 1; but fails to teach a chip, disposed on the flexible circuit board.
Cho teaches an electronic device (fig. 1B, 1), comprising the flexible circuit board (20 [paragraph 0073] Cho states, “module substrate may be flexible 20”) and a chip (12 [paragraph 0072] Cho states, “semiconductor chip 12”), disposed on the flexible circuit board (20).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit board having a copper conductive layer as taught by Runyon with a chip disposed on a flexible circuit board as taught by Cho because Cho states, “as multimedia technology develops, demand for flexible electronic devices is increasing. Thus, mounting a device (e.g., an organic light emitting display (OLED) device, a liquid crystal display (LCD) device, a plasma display panel (PDP), a thin-film transistor (TFT), a micro-processor, and/or random access memory (RAM)) on a flexible substrate is desired…the semiconductor package 10 can be reliably mounted on the module substrate 20 having the curved profile, and moreover, it is possible to realize the semiconductor module 1 with improved reliability.” [paragraph 0004 & 0075].
Claim(s) 10 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Matsui et al. (US PG. Pub. 2024/0164017) in view of Tsukamoto
Regarding claim 10 – Matsui teaches a flexible circuit board for chip integration (fig. 8; The preamble of the claim(s) is not considered a limitation and is of no significance to claim construction. See Pitney Bowes, Inc. v. Hewlett-Packard Co., 182 F.3d 1298, 1305, 51 USPQ2d 1161, 1165 (Fed. Cir. 1999). See MPEP § 2111.02.), comprising: an insulating substrate (fig. 8, 12 [paragraph 0042] Matsui states, “insulating layer 12”); a conductive copper layer (combination of layers 13A & 13B [paragraph 0055 & 0056] Matsui states, “first conductive layer 13A is made of a metal. Examples of the metal include copper…The second conductive layer 13B is made of a material identical to a material of the first conductive layer 13A”), having a patterned circuit (see “patterned circuit” shown in figure 8) and located on the insulating substrate (12), the conductive copper layer (13A/13B) having a first region (see region C) and a second region (see region E) electrically connected with each other (see fig. 8), wherein the conductive copper layer (13A/13B) located in the first region (see region C) has a first copper thickness (see thickness of combined layers 13A and 13B), the conductive copper layer (13A/13B) located in the second region has a second copper thickness (see thickness of 13B in the second region E), and the first copper thickness is greater than the second copper thickness (claimed structure shown in figure 8).
Matsui fails to teach the conductive copper layer having a thickness ranging between 2 μm and 20 μm.
Tsukamoto teaches a circuit board (figs. 1A-1B) having a conductive copper layer (wiring layer 15 including metal layer 32 [paragraph 0055] Tsukamoto states, “As the materials of the metal film 31 and the metal layers 32 and 33, for example, copper and copper alloys can be used”) wherein the conductive copper layer having a thickness ranging between 2 μm and 20 μm ([paragraph 0029] Tsukamoto states, “the thickness of the wiring layer 15 can be set to, for example, about 2 μm to 5 μm”).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit board for chip integration having a conductive copper layer as taught by Matsui with a conductive copper layer having a thickness ranging between 2um and 20um as taught by Tsukmoto because this thickness being relatively thin will allow for increased density of the wirings/pads while still providing a strong electrical/mechanical connection between conductive elements (solder ball, wirings etc.).
Regarding claim 14 – Matsui in view of Tsukamoto teach the flexible circuit board according to claim 10, further comprising: a first tin layer (Matsui; fig. 8, 13C [paragraph 0057] Matsui states, “metal of the protective layer 13C include nickel, gold, and tin”), located above the first region (region at C) of the conductive copper layer (13A/13B); a second tin layer (tin layer shown in second region E), located above the second region (see region E) of the conductive copper layer (13A/13B); and a first solder resist layer (14 [paragraph 0088] Matsui states, “second insulating layer 14”), at least partially covering the first tin layer (13C; figure 8 shows the solder resist layer 14 covering the surface of the first tin layer 13C in the periphery region E).
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Matsui et al. in view of Tsukamoto as applied to claim 14 above, and further in view of Runyon et al.
Regarding claim 15 – Matsui in view of Tsukamoto teach the flexible circuit board according to claim 14, but fail to teach wherein the first tin layer has a first tin thickness, the second tin layer has a second tin thickness, and the first tin thickness is different from the second tin thickness.
Runyon teaches wherein the first tin layer (fig. 1, 30 [paragraph 0011] Runyon states, “solder joint 30…solder alloy is composed of near-eutectic tin-lead alloy”) has a first tin thickness (t1), the second tin layer (34) has a second tin thickness (t2), and the first tin thickness (t1) is different from the second tin thickness ([paragraph 0011] Runyon states, “central thickness t1 is less than the perimeter thickness t2”).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit board having a first tin layer as taught by Matsui in view of Tsukamoto with the first layer having a first thickness and a second tin layer having a second thickness different than the first thickness as taught by Runyon because Runyon states, “so that the relatively thin central portion promoted thermal dissipation to maintain the die within a desired operating temperature range, and the relatively thick perimeter region distributes thermally induced stresses to enhance joint strength and reduce fatigue cracking…the solder layer is greater at the perimeter where stresses due to thermal expansion mismatch tend to accumulate, and so is better able to resist fatigue that might otherwise result in failure of the device.” [Abstract & 0005].
Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tsukamoto in view of Cho et al.
Regarding claim 7 – Tsukamoto teaches the flexible circuit board according to claim 10, but fails to teach wherein the first region is located in a bendable region of the flexible circuit board.
Cho teaches a flexible circuit board (fig. 1B, 20 [paragraph 0073] Cho state, “module substrate 20 may be flexible”) having a conductive layer (26 [paragraph 0073] Cho states, “The pads 25 and 26 may include a conductive material”) with a first region (central region of the conductive layer 26) wherein the first region is located in a bendable region (22 [paragraph 0073] Cho states, “curved portion 22”)of the flexible circuit board (20).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit board having a copper conductive layer with a first region as taught by Tsukamoto with the first region of the conductive layer being located in a bendable region of a flexible circuit board as taught by Cho because Cho states, “as multimedia technology develops, demand for flexible electronic devices is increasing. Thus, mounting a device (e.g., an organic light emitting display (OLED) device, a liquid crystal display (LCD) device, a plasma display panel (PDP), a thin-film transistor (TFT), a micro-processor, and/or random access memory (RAM)) on a flexible substrate is desired.” [paragraph 0004].
Allowable Subject Matter
Claims 2, 4 & 8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Rosch et al. (US PG. Pub. 2019/0393143) discloses a dual trace thickness for single layer routing.
Kim et al. (US PG. Pub. 2010/0122842) discloses a PCB.
Yokobayashi et al. (US PG. Pub. 2008/0157359) discloses a crack-resistant solder joint.
Furusawa (US Patent 6384343) discloses a semiconductor device.
Ohuchi et al. (US Patent 6251704) discloses having a pad with a step portion.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEVEN T SAWYER whose telephone number is (571)270-5469. The examiner can normally be reached M-F 8:30 am - 5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Thompson can be reached at 5712722342. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/STEVEN T SAWYER/Primary Examiner, Art Unit 2847
