DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 10/08/24 and 01/07/25 have been considered by the examiner.
Drawings
The drawings received on 10/08/24 are acceptable.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-3, 5-7, 9-12 and 14-20 of U.S. Patent No. 12,126,251. Although the claims at issue are not identical, they are not patentably distinct from each other because .
US Application No. 18/909,818
US Patent No. 12,126,251
Claim 1. A circuit comprising: a transistor having a gate terminal, a source terminal and a drain terminal; a control circuit coupled to the gate terminal and arranged to change a conductivity state of the transistor; and wherein the control circuit is arranged to cause a turn off of the transistor by changing a voltage at the gate terminal at a first rate of voltage with respect to time from an on- state voltage to a first intermediate voltage, and from the first intermediate voltage to a second intermediate voltage at a second rate of voltage with respect to time, and from the second intermediate voltage to an off-state voltage at a third rate of voltage with respect to time.
Claim 2. The circuit of claim 1, wherein the first rate is higher than the second rate.
Claim 5. The circuit of claim 1, wherein the control circuit comprises: a first pull-down circuit connected to the gate terminal; a second pull-down circuit connected to the gate terminal; and a third pull-down circuit connected to the gate terminal.
Claim 1. A circuit comprising: a transistor having a gate terminal, a source terminal and a drain terminal; a first pull-down circuit connected to the gate terminal; a second pull-down circuit connected to the gate terminal; and a third pull-down circuit connected to the gate terminal; wherein the first, the second and the third pull-down circuits are arranged to cause a turn off of the transistor by changing a voltage at the gate terminal at a first rate of voltage with respect to time from an on-state voltage to a first intermediate voltage, and from the first intermediate voltage to a second intermediate voltage at a second rate of voltage with respect to time, and from the second intermediate voltage to an off-state voltage at a third rate of voltage with respect to time, wherein the first rate is higher than the second rate.
Claim 3. The circuit of claim 1, wherein the third rate is higher than the second rate.
Claim 2. The circuit of claim 1, wherein the third rate is higher than the second rate.
Claim 4. The circuit of claim 1, wherein the transistor comprises gallium nitride (GaN).
Claim 3. The circuit of claim 1, wherein the transistor comprises gallium nitride (GaN).
Claim 6. The circuit of claim 5, wherein the first pull-down circuit comprises a first pull-down transistor.
Claim 5. The circuit of claim 3, wherein the first pull-down circuit comprises a first pull-down transistor.
Claim 7. The circuit of claim 6, wherein the second pull-down circuit comprises a second pull-down transistor coupled to a diode-connected transistor
Claim 6. The circuit of claim 5, wherein the second pull-down circuit comprises a second pull-down transistor.
Claim 8. The circuit of claim 7, wherein the third pull-down circuit comprises a third pull-down transistor and a logic circuit.
Claim 7. The circuit of claim 6, wherein the second pull-down circuit further comprises a diode-connected transistor
Claim 9. The circuit of claim 8, wherein the logic circuit is coupled to a gate terminal of the third pull-down transistor, and wherein the logic circuit is arranged to control an operation of the third pull-down transistor.
Claim 9. The circuit of claim 8, wherein the logic circuit is coupled to a gate terminal of the third pull-down transistor, and wherein the logic circuit is arranged to control an operation of the third pull-down transistor
10. A method of operating a circuit, the method comprising: providing a power transistor with a gate terminal, a source terminal and a drain terminal, the gate terminal arranged to control operation of the power transistor; providing a control circuit coupled to the gate terminal and arranged to change a conductivity state of the power transistor; and receiving, control circuit, a turn-off signal, wherein in response to receiving the turn-off signal the control circuit controls a voltage at the gate terminal such that the voltage at the gate terminal changes at a first rate of voltage with respect to time from a first voltage to a first intermediate voltage, and at a second rate of voltage with respect to time from the first intermediate voltage to a second intermediate voltage, and at a third rate of voltage with respect to time from the second intermediate voltage to second voltage.
Claim 11. The method according to claim 10, wherein the first rate is higher than the second rate and the third rate is higher than the second rate.
Claim 10. A method of turning off a power transistor, the method comprising: providing a power transistor with a gate terminal, a source terminal and a drain terminal, the gate terminal arranged to control operation of the power transistor; providing a turn-off circuit, the turn-off circuit coupled to the gate terminal; and receiving, by the turn-off circuit, a turn-off signal, wherein in response to receiving the turn-off signal the turn-off circuit controls a voltage at the gate terminal such that the voltage at the gate terminal changes at a first rate of voltage with respect to time from a first voltage to a first intermediate voltage, and at a second rate of voltage with respect to time from the first intermediate voltage to a second intermediate voltage, and at a third rate of voltage with respect to time from the second intermediate voltage to second voltage, wherein the first rate is higher than the second rate and the third rate is higher than the second rate
Claim 12. The method according to claim 10, wherein the first voltage is an on-state voltage of the power transistor that enables current to flow through the power transistor and the second voltage is an off-state voltage of the power transistor that prevents current from flowing through the power transistor.
Claim 11. The method according to claim 10, wherein the first voltage is an on-state voltage of the power transistor that enables current to flow through the power transistor and the second voltage is an off-state voltage of the power transistor that prevents current from flowing through the power transistor.
Claim 13. The method according to claim 12, wherein the control circuit comprises a first pull-down circuit, a second pull-down circuit, and a third pull-down circuit.
Claim 12. The method according to claim 10, wherein the turn-off circuit comprises a first pull-down circuit, a second pull-down circuit, and a third pull-down circuit.
Claim 14. The method according to claim 13, wherein the first pull-down circuit comprises a first pull-down transistor
Claim 14. The method according to claim 12, wherein the first pull-down circuit comprises a first pull-down transistor.
15. The method according to claim 14, wherein the second pull-down circuit comprises a second pull-down transistor.
Claim 15. The method according to claim 14, wherein the second pull-down circuit comprises a second pull-down transistor
16. The method according to claim 15, wherein the second pull-down circuit further comprises a diode-connected transistor.
16. The method according to claim 15, wherein the second pull-down circuit further comprises a diode-connected transistor
Claim 17. A power converter circuit comprising: a power transistor with a gate terminal, a drain terminal and source terminal, the gate terminal arranged to control operation of the power transistor, and the drain terminal coupled to a first node of a first winding of a primary side of a transformer; a control circuit coupled to a first node of a second winding of the primary side of the transformer and coupled to the gate terminal; and wherein the control circuit is arranged to change a voltage at the gate terminal at a first rate of voltage with respect to time from a first voltage to a first intermediate voltage, and to change the voltage at the gate terminal at a second rate of voltage with respect to time from the first intermediate voltage to a second intermediate voltage, and to change the voltage at the gate terminal at a third rate of voltage with respect to time from the second intermediate voltage to a second voltage.
Claim 17. A power converter circuit comprising: a power transistor with a gate terminal, a drain terminal and source terminal, the gate terminal arranged to control operation of the power transistor, and the drain terminal coupled to a first node of a primary side of a transformer; a control circuit coupled to a second node of the primary side of the transformer; and a turn-off circuit coupled to the gate terminal and arranged to change a voltage at the gate terminal at a first rate of voltage with respect to time from a first voltage to a first intermediate voltage, and to change the voltage at the gate terminal at a second rate of voltage with respect to time from the first intermediate voltage to a second intermediate voltage, and to change the voltage at the gate terminal at a third rate of voltage with respect to time from the second intermediate voltage to a second voltage, the first rate being higher than the second rate.
Claim 18. The power converter circuit of claim 17, wherein the first voltage is an on- state voltage of the power transistor that enables current to flow through the power transistor and the second voltage is an off-state voltage of the power transistor that prevents current from flowing through the power transistor.
Claim 18. The power converter circuit of claim 17, wherein the first voltage is an on- state voltage of the power transistor that enables current to flow through the power transistor and the second voltage is an off-state voltage of the power transistor that prevents current from flowing through the power transistor
19. The power converter circuit of claim 18, wherein the first rate is higher than the second rate and the third rate is higher than the second rate.
Claim 19. The power converter circuit of claim 18, wherein the third rate is higher than the second rate.
20. The power converter circuit of claim 19, wherein the control circuit comprises a first pull-down circuit, a second pull-down circuit and a third pull down circuit.
Claim 20. The power converter circuit of claim 19, wherein the turn-off circuit comprises a first pull-down circuit, a second pull-down circuit and a third pull down circuit.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Jia et al. (US 12,438,528 B2) disclose a transistor DV/DT control circuit.
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/ADOLF D BERHANE/Primary Examiner, Art Unit 2838