Prosecution Insights
Last updated: May 29, 2026
Application No. 18/909,883

DISPLAY DEVICE

Non-Final OA §103
Filed
Oct 08, 2024
Priority
Mar 25, 2024 — TW 113110940
Examiner
CHUNG, DAVID Y
Art Unit
2871
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Hannstar Display Corporation
OA Round
2 (Non-Final)
70%
Grant Probability
Favorable
2-3
OA Rounds
1y 3m
Est. Remaining
77%
With Interview

Examiner Intelligence

Grants 70% — above average
70%
Career Allowance Rate
487 granted / 700 resolved
+1.6% vs TC avg
Moderate +8% lift
Without
With
+7.8%
Interview Lift
resolved cases with interview
Typical timeline
2y 10m
Avg Prosecution
24 currently pending
Career history
726
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
85.4%
+45.4% vs TC avg
§102
9.7%
-30.3% vs TC avg
§112
1.9%
-38.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 700 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-2, 4-8 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Murata et al. (US 2023/0251522) in view of CN111443531A and Yonemura et al. (US 2018/0173034). As to claim 1, Murata discloses in figure 9: a display panel 20; and a viewing angle controlling panel 10 (anti-peeping panel) disposed at one side of the display panel, the viewing angle controlling panel comprising: a first substrate 150; a second substrate 110 disposed on the first substrate; a liquid crystal layer 130 disposed between the first substrate and the second substrate. Murata does not disclose a plurality of first spacers disposed between the first substrate and the second substrate, and a plurality of second spacers disposed between the first substrate and the second substrate. CN111443531A discloses in figures 2-4: a plurality of first spacers 3 disposed between the first substrate 2 and the second substrate 1, wherein the plurality of first spacers are arranged in a plurality of columns, and four adjacent first spacers in the plurality of first spacers and four virtual lines define a closed unit, wherein two ends of each of the virtual lines are connected with two adjacent first spacers of the four adjacent first spacers, and the closed unit has a unit area, wherein a first density is a ratio of a sum of areas of bottom surfaces of the four adjacent first spacers in the closed unit to the unit area of the closed unit; and a plurality of second spacers 4 disposed between the first substrate and the second substrate, wherein the plurality of second spacers are randomly distributed between the first substrate and the second substrate, wherein a second density is a ratio of a sum of areas of bottom surfaces of the second spacers in the closed unit to the unit area of the closed unit. CN111443531A discloses that the arrangement of the first spacers 3 and the second spacers 4 can satisfy the unordered and uniform arrangement requirement. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Murata by providing a plurality of first spacers and a plurality of second spacers as disclosed by CN111443531A in order to satisfy the unordered and uniform arrangement requirement. CN111443531A does not disclose wherein a ratio of the first density to the second density ranges from 1:2 to 1:8. Yonemura discloses in figure 3, a liquid crystal panel 100 comprising main spacers 180a (first spacers) and sub spacers 180b (second spacers). Yonemura discloses in paragraph [0007], in order to effectively exhibit a function of the dual spacer structure, i.e., a function of suppressing failures such as downward bulging failures at a high temperature and foaming failures at a low temperature, it is necessary to appropriately select an area density of the main spacers, or a ratio between the main spacers and the sub spacers to control a compression deformation amount of the main spacers. Yonemura further discloses in paragraph [0066], optimizing the area density of the main spacers 180a and sub spacers 180b. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify Murata wherein a ratio of the first density to the second density ranges from 1:2 to 1:8 in order to optimize the area density of the first and second spacers to suppress downward bulging failures at high temperature and foaming failures at low temperature as disclosed by Yonemura. See MPEP 2144.05, Section II. CN111443531A does not disclose wherein the second density is greater than or equal to 0.2% and less than or equal to 0.56%. Yonemura discloses in paragraph [0066], the area density of the sub spacers is set as the density which provides desired robustness in case where a plane pressing stress is applied to the liquid crystal panel. Therefore, Yonemura discloses optimizing the second density to provide a desired robustness when external force is applied to the liquid crystal panel. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify Murata wherein the second density is greater than or equal to 0.2% and less than or equal to 0.56%, in order to optimize the second density to provide a desired robustness when external force is applied to the liquid crystal panel. See MPEP 2144.05, Section II. As to claim 2, Murata in view of CN111443531A and Yonemura discloses all of the elements of the claimed invention discussed above regarding claim 1. CN111443531A further discloses in figures 2-3, wherein the plurality of first spacers 3 are arranged in a plurality of rows, each of the columns extends along a first direction, each of the rows extends along a second direction, and the first direction is perpendicular to the second direction. As to claim 4, Murata in view of CN111443531A and Yonemura discloses all of the elements of the claimed invention discussed above regarding claim 1. CN111443531A further discloses in figure 4, wherein the first spacers 3 have a first height, and the second spacers 4 have a second height, and the first height is greater than the second height. As to claim 5, Murata in view of CN111443531A and Yonemura discloses all of the elements of the claimed invention discussed above regarding claim 1. Murata further discloses in figure 1, wherein the viewing angle control panel 10 (anti-peeping panel) further comprises: a first transparent conductive layer 152 disposed between the first substrate 151 and the liquid crystal layer 130; a first alignment film 140 disposed between the first transparent conductive layer and the liquid crystal layer; a second transparent conductive layer 112 disposed between the plurality of first spacers and the second substrate 111 and between the plurality of second spacers and the second substrate; and a second alignment film 120 covering the plurality of first spacers and the plurality of second spacers. As to claim 6, Murata in view of CN111443531A and Yonemura discloses all of the elements of the claimed invention discussed above regarding claim 1. Murata further discloses in figure 11, a backlight module 30, wherein the display panel 20 is disposed between the backlight module 30 and the viewing angle control panel 10 (anti-peeping panel). As to claim 7, Murata in view of CN111443531A and Yonemura discloses all of the elements of the claimed invention discussed above regarding claim 6, but does not disclose a touch component, wherein the anti-peeping panel is disposed between the touch component and the display panel. However, it was well known to provide a touch component on the top surface of the display device in order to provide touch functionality. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify Murata by providing a touch component on the top surface of the display device in order to provide touch functionality. Providing a touch component on the top surface of the display device shown in figure 11 of Murata results in the viewing angle control panel 10 (anti-peeping panel) being disposed between the touch component and the display panel 20. As to claim 8, Murata in view of CN111443531A and Yonemura discloses all of the elements of the claimed invention discussed above regarding claim 1. Murata further discloses in figure 9, a backlight module 30, wherein the viewing angle control panel 10 (anti-peeping panel) is disposed between the backlight module 30 and the display panel 20. As to claim 10, Murata in view of CN111443531A and Yonemura discloses all of the elements of the claimed invention discussed above regarding claim 1. As discussed above regarding claim 1, Yonemura discloses in paragraphs [0007], optimizing the area density of the first spacers to suppress downward bulging failures at high temperatures and foaming failures at low temperature. Yonemura discloses in paragraph [0066], optimizing the area density of the second spacers to provide a desired robustness when external force is applied to the liquid crystal panel. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify Murata by optimizing the area density of the first spacers to suppress downward bulging failures at high temperatures and foaming failures at low temperature and optimizing the area density of the second spacers to provide a desired robustness when external force is applied to the liquid crystal panel, such that a sum of the first density and the second density is greater than or equal to 0.3% and less than or equal to 0.63%, because optimization of result-effective variables involved only routine experimentation. See MPEP 2144.05, Section II. Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Murata et al. (US 2023/0251522) in view of CN111443531A and Yonemura et al. (US 2018/0173034) as applied to claim 1 above, and further in view of Li et al. (US 2016/0349575). Murata in view of CN111443531A and Yonemura discloses all of the elements of the claimed invention discussed above regarding claim 1, but does not disclose wherein the first spacers in the odd columns and the first spacers in the even columns are staggered. Li discloses in figure 6, wherein the first spacers 402 in the odd columns and the first spacers 42 in the even columns are staggered. Li discloses in figure 5, wherein the first spacers 402 in the odd columns and the first spacers 402 in the even columns are not staggered. This shows that the two arrangements were art recognized equivalents. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify Murata wherein the first spacers in the odd columns and the first spacers in the even columns are staggered as disclosed by Li because it was an art recognized equivalent to the arrangement disclosed by CN111443531A. Response to Arguments Applicant's arguments filed April 8, 2026 have been fully considered but they are not persuasive. Regarding claim 1, applicant argues that the prior art Yonemura discloses a second density of 0.1%, instead of the claimed second density of 0.2% to 0.56%. However, Yonemura also discloses optimizing the second density to provide a desired robustness when external force is applied to the liquid crystal panel. Therefore, it was known to optimize the second spacer density through routine experimentation. Applicant’s claimed range, although not explicitly disclosed by the prior art, does not patentably distinguish the claims without a showing of criticality, which requires showing that the claimed range achieves unexpected results (MPEP 2144.05, Section III, Part A). To establish unexpected results over a claimed range, applicants should compare a sufficient number of tests both inside and outside the claimed range (MPEP 716.02(d), Section II). Regarding claim 10, applicant argues that the prior art of record does not disclose that a sum of the first density of first spacers and the second density of second spacers is 0.3% to 0.63%. However, Yonemura discloses optimizing the area density of the first spacers to suppress downward bulging failures at high temperatures and foaming failures at low temperature, and optimizing the area density of the second spacers to provide a desired robustness when external force is applied to the liquid crystal panel. By optimizing the first density and the second density through routine experimentation, a sum of the first density and the second density would have also been optimized. Applicant’s claimed range, although not explicitly disclosed by the prior art, does not patentably distinguish the claims without a showing of criticality, which requires showing that the claimed range achieves unexpected results (MPEP 2144.05, Section III, Part A). To establish unexpected results over a claimed range, applicants should compare a sufficient number of tests both inside and outside the claimed range (MPEP 716.02(d), Section II). Conclusion THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to David Chung whose telephone number is (571)272-2288. The examiner can normally be reached Monday - Friday, 8:30 am - 5:00 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Michael Caley can be reached at (571)272-2286. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /DAVID Y CHUNG/Examiner, Art Unit 2871
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Prosecution Timeline

Oct 08, 2024
Application Filed
Aug 27, 2025
Non-Final Rejection mailed — §103
Nov 11, 2025
Response Filed
Feb 06, 2026
Non-Final Rejection mailed — §103
Apr 08, 2026
Response Filed

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12638713
DISPLAY MODULE AND MOBILE TERMINAL
2y 1m to grant Granted May 26, 2026
Patent 12638706
DISPLAY PANEL AND MANUFACTURING METHOD THEREOF
2y 11m to grant Granted May 26, 2026
Patent 12638724
Light Modulating Device
3y 4m to grant Granted May 26, 2026
Patent 12641987
Display Substrate, Manufacturing Method Therefor, and Display Device
3y 1m to grant Granted May 26, 2026
Patent 12641202
ELECTRO-OPTICAL DEVICE AND ELECTRONIC APPARATUS
3y 1m to grant Granted May 26, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

2-3
Expected OA Rounds
70%
Grant Probability
77%
With Interview (+7.8%)
2y 10m (~1y 3m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 700 resolved cases by this examiner. Grant probability derived from career allowance rate.

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