DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings received on 10/08/2024 have been accepted by the examiner.
Information Disclosure Statement
Acknowledgment is made of applicant's Information Disclosure Statement (IDS) Form PTO-1449, filed 11/27/2025. The information disclosed therein was considered.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-8 & 11-13 is/are rejected under 35 U.S.C. 102a(1) as being anticipated by Arakawa et al (US20190214098).
Regarding claim 1, Arakawa discloses a dynamic random-access memory (DRAM) device(FIG 1 & 3; [0022] DRAM 10/100), comprising: at least one slave DRAM chip, wherein each of the at least one slave DRAM chip comprises:(FIG 1-3; [0006 & 0027] discloses 300 slave chip comprising memory arrays), a slave control circuit(330/340 a slave control circuit ), configured to generate a slave control signal according to a slave category signal and a setting signal(FIG 3; 340 connected to CP_S able to disable and enable based on Vin and Vcp); and a slave power circuit, coupled to the slave control circuit and configured to stop generating at least one of a plurality of slave voltages in response to a first value of the slave control signal and generate the plurality of slave voltages in response to a second value of the slave control signal(300/CP_S configured to enabled selected memory chip and disabled unselected memory chip); and a master DRAM chip, coupled to the at least one slave DRAM chip and configured to control an operation of the at least one slave DRAM chip(200), wherein the master DRAM chip comprises: a master control circuit, configured to generate a master control signal according to a master category signal and the setting signal(CP_M), and to control the master DRAM chip to generate a plurality of master voltages according to the master control signal, wherein the slave category signal is different from the master category signal (240 controlling CP_M according to Vin and Vcp).
Regarding claim 2, Arakawa discloses wherein: a logical value of the slave category signal is a first logical value, and a logical value of the master category signal is a second logical value (FIG 3; [0005] selecting slave side based on high level logic (01) and master side based on low level logic (00)).
Regarding claim 3, Arakawa discloses wherein: when the logical value of the setting signal is the first logical value, the logical value of the slave control signal is the first logical value (fig 3; [0005] logic 0), and when the logical value of the setting signal is the second logical value, the logical value of the slave control signal is the second logical value (logic 1).
Regarding claim 4, Arakawa discloses wherein: the first logical value is a high logical value (FIG 1; [0005] slave at high logic), the second logical value is a low logical value (low logic), and the slave control circuit performs a logical AND operation on the slave category signal and the setting signal to generate the slave control signal (FIG 7; [0038-0039]; 410).
Regarding claim 5, Arakawa discloses further comprising: a setting circuit, coupled to the slave control circuit and the master control circuit (14 coupled to 240 and 340 connected to 200 and 300), and configured to generate the setting signal according to a setting operation of the DRAM device (FIG 1 & 3; [0005-0006 & 0027] configured to n sets of pumps circuits charger pump circuits CP_S and CP_M).
Regarding claim 6, Arakawa discloses wherein the setting circuit is implemented by a fuse circuit (FIG 1 & 3; [0005] the master/slave setting is performed by a fuse).
Regarding claim 7, Arakawa discloses wherein the setting circuit is disposed in one of the at least one slave DRAM chip (FIG 3 & 7; [0037] n sets of being in CP_S that is connected to slave chip 300).
Regarding claim 8, Arakawa discloses wherein the setting circuit is disposed in the master DRAM chip FIG 3 & 7; [0037] n sets of being in CP_M that is connected to master chip 200).
Regarding claim 11, Arakawa discloses wherein the slave power circuit comprises (330 comprising CP_S): a charge pump, coupled to the slave control circuit and configured to stop generating at least one pumping voltage of the plurality of slave voltages in response to a first value of the slave control signal and generate the at least one pumping voltage in response to a second value of the slave control signal (FIG 1-3; [0005-0007] 340 connected to CP_S configured to enabled selected memory chip and disabled unselected memory chip based on high and low logic levels based on Vins and Vcps).
Regarding claim 12, Arakawa discloses wherein the master DRAM chip further comprises: a master power circuit, coupled to the master control circuit and configured to stop generating at least one of the plurality of master voltages in response to a first value of the master control signal and generate the plurality of master voltages in response to a second value the master control signal (FIG 1-3; [0005-0007] 220/ 240 connected to CP_M configured to enabled selected memory chip and disabled unselected memory chip based on high and low logic levels based on Vins and Vcps).
Regarding claim 13, Arakawa discloses wherein: the at least one slave DRAM chip and the master DRAM chip are stacked on each other (FIG 1-3; [0006] stacked memory configurations shown in 10 is also in 100).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 9 & 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Arakawa et al in view of Lee et al (US20210336623).
Regarding claim 9, Arakawa discloses wherein the slave power circuit comprises: coupled to the slave control circuit and configured to stop generating at least one voltage of the plurality of slave voltages in response to a first value of the slave control signal and generate the at least one voltage of in response to a second value of the slave control signal(FIG 1-3; [0005-0007] 340 connected to CP_S configured to enabled selected memory chip and disabled unselected memory chip based on high and low logic levels based on Vins and Vcps).
However, Arakawa does not disclose a bandgap reference voltage generation circuit, generating at least one bandgap reference voltage and one bandgap reference voltage.
In the same field of endeavor, Lee discloses a bandgap reference voltage generation circuit, generating at least one bandgap reference voltage and one bandgap reference voltage ((FIG 7; [0098] discloses a bandgap reference voltage generator 230 generating Vbgr).
Arakawa and Lee are analogous art because they are all directed to an electronic device comprising master and slave chips(circuits), and one of ordinary skill in the art would have had a reasonable expectation of success by modify Arakawa to include Lee because they are from the same field of endeavor.
Therefore, it would be obvious to include the teachings of Lee in the teachings of Arakawa for the benefits avoiding malfunction in electronic circuits. [0003 Lee].
Regarding claim 10, Arakawa discloses wherein the slave power circuit comprises: coupled to the slave control circuit and configured to stop generating at least one power supply voltage of the plurality of slave voltages in response to a first value of the slave control signal and generate the at least one power supply voltage in response to a second value of the slave control signal(FIG 1-3; [0005-0007] 340 connected to CP_S configured to enabled selected memory chip and disabled unselected memory chip based on high and low logic levels based on Vins and Vcps).
However, Arakawa does not disclose a voltage regulator.
In the same field of endeavor, Lee discloses a voltage regulator (FIG 7; 250).
Arakawa and Lee are analogous art because they are all directed to an electronic device comprising master and slave chips(circuits), and one of ordinary skill in the art would have had a reasonable expectation of success by modify Arakawa to include Lee because they are from the same field of endeavor.
Therefore, it would be obvious to include the teachings of Lee in the teachings of Arakawa for the benefits avoiding malfunction in electronic circuits. [0003 Lee].
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Lee et al (US20090179785 FIG 2 & 14; discloses charge pump and write bandgap voltage reference).
Marinca et al (US7173407 FIG 3-4; claim 25; discloses bandgap voltage reference circuit, current mirror circuit including a master and a slave transistor).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MUNA A TECHANE whose telephone number is (571)272-7856. The examiner can normally be reached 571-272-7856.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at 571-272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MUNA A TECHANE/Primary Examiner, Art Unit 2827
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